INTEGRATED CIRCUIT PACKAGING, ASSEMBLY AND INTERCONNECTIONS INTEGRATED CIRCUIT PACKAGING, ASSEMBLY AND INTERCONNECTIONS William J. Greig Consultant Somerville, New Jersey, USA William J. Greig Consultant 10 Imperial Drive Somerville, NJ 08876 Integrated Circuit Packaging, Assembly and Interconnections Library of Congress Control Number: 2006927423 ISBN 0-387-28153-3 e-ISBN 0-387-33913-2 ISBN 978-0387-28153-7 e-ISBN 978-0387-33913-9 Printed on acid-free paper. © 2007 Springer Science+Business Media LLC All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks and similar terms, even if the are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. 9 8 7 6 5 4 3 2 1 springer.com DEDICATION To my family, my wife Joan and our children, their spouses and grandchildren Karen – Christopher, Ryan, Kevin Billy and Cathy – Alli, Jeff, Shauna Joni and Fred – Danny, Kerri, Traci Jo Jimmy and Colleen – Maggie, Molly, Katie, Claire Ronny and Meryl – RJ, Connor Steven Kenny Table of Contents List of Figures ........................................................................................................ xiii List of Tables...........................................................................................................xxi Preface .................................................................................................................. xxiii Acknowledgements ................................................................................................xxv About the Author................................................................................................ xxvii 1 Electronic Manufacturing and the Integrated Circuit............... 1 1 — MICROELECTRONICS AND THE TRANSISTOR................................1 1.1 — The Integrated Circuit and Moore’s Law (2-5) .......................................1 1.2 — Electronics Manufacturing and the Technology Drivers.........................3 1.3 — A Technology Driver—The Integrated Circuit .......................................8 1.4 — The International Roadmap for Semiconductors (ITRS) ......................10 2 Integrated Circuit Manufacturing: A Technology Resource... 15 2 — IC MANUFACTURING TECHNOLOGIES ...........................................15 2.1 — Overview of the IC Manufacturing Processes.......................................15 2.2 — The Manufacturing Environment ..........................................................17 2.3 — The Photolithographic Process..............................................................20 2.4 — IC Methodologies and Packaging, Assembly, Interconnections ...........28 3 Packaging the IC—Single Chip Packaging ............................... 31 3 — THE IC PACKAGE....................................................................................31 3.1 — Trends in IC Packaging.........................................................................32 3.2 — Area Array Packages—PGA, BGA ......................................................36 3.3 — BGA Surface Mount Assembly.............................................................41 3.4 — BGA Attributes .....................................................................................42 3.5 — BGA Concerns ......................................................................................42 3.6 — The Future.............................................................................................43 3.7 — Lead-Free Manufacturing......................................................................43 viii viii Integrated Circuit Packaging, Assembly and Interconnections 4 The Chip Scale Package .............................................................. 47 4 — THE CHIP SCALE PACKAGE, CSP ......................................................47 4.1 — Chip Scale Package Manufacturing Technologies................................48 4.2 — The µBGATM.........................................................................................52 4.3 — Wafer Level Packaging—The WLP......................................................55 4.4 — Reliability Concerns .............................................................................57 4.5 — Summary...............................................................................................58 5 Multichip Packaging.................................................................... 61 5 — MULTICHIP PACKAGING (MCP).........................................................61 5.1 — MCP Substrate/Package Technologies .................................................62 5.2 — The Hybrid Circuit ................................................................................62 5.3 — The Multichip Module (MCM).............................................................65 5.4 — 3-D Packaging.......................................................................................67 5.5 — 3-D Packaging and the Flex Circuit ......................................................71 5.6 — Die Stacking Using Silicon Thru-Vias..................................................75 5.7 — System in Package (SiP)/System on Package (SoP) .............................77 5.8 — Summary—Benefits of Multichip Packaging .......................................79 6 Known Good Die (KGD) ............................................................. 81 6 — THE KGD STORY .....................................................................................81 6.1 — The Semiconductor Assembly/Packaging/Test Process........................81 6.2 — The Bare Die Problem...........................................................................83 6.3 — Addressing the Bare Die Problem—Wafer Lot Acceptance Testing ....86 6.4 — Known Good Die (KGD)......................................................................86 6.5 — Wafer Level Burn-in and Test (WLBT)................................................90 6.6 — Industry Responsiveness .......................................................................92 7 Packaging Options—Chip on Board.......................................... 93 7 — DIRECT CHIP ATTACH (DCA) AND CHIP ON BOARD (COB).......93 7.1 — The COB Process..................................................................................94 7.2 — Flip Chip On Board (FCOB).................................................................98 7.3 — Summary.............................................................................................101 8 Chip & Wire Assembly.............................................................. 103 8 — CHIP & WIRE ASSEMBLY ..................................................................103 8.1 — Die/Wire Bonding and Bonder Equipment Development...................103 8.2 — Impact of the IC on Bonding and Bonder Development.....................105 8.3 — The Chip and Wire Assembly Process................................................105 ix Table of Contents ix 8.4 — Bonding Wire: Au, Al, and Cu............................................................106 8.5 — Bonding Methods................................................................................108 8.6 — Types of Bonds ...................................................................................110 8.7 — The Ball Bonding Process...................................................................110 8.8 — Wedge Bonding...................................................................................111 8.9 — Obstacles to Quality and Reliable Wire Bonding................................112 8.10 — Metallurgical Concerns and Surface Finishes ...................................114 8.11 — Handling and Storage........................................................................118 8.12 — Verifying Wire Bonding Quality.......................................................118 8.13 — Responding to the IC and End Product .............................................120 8.14 — Wire Bonding on Organic Substrates, The PBGA and PWB............125 8.15 — Summary...........................................................................................127 9 Tape Automated Bonding—TAB ............................................. 129 9 — BACKGROUND—MINIMOD................................................................129 9.1 —Tape Automated Bonding ....................................................................129 9.2 — The TAB Tape ....................................................................................129 9.3 — TAB Assembly....................................................................................134 9.4 — Reliability Concerns............................................................................138 9.5 — Areas of Applications..........................................................................139 9.6 — Summary.............................................................................................140 10 Flip Chip—The Bumping Processes...................................... 143 10 — BACKGROUND .....................................................................................143