4 IC DEVICE AND PACKAGING TECHNOLOGY TRENDS

IC DEVICE TECHNOLOGY OVERVIEW

There are a variety of major manufacturing process technologies (Figure 4-1) used in design and fabrication of silicon-based integrated circuits (ICs). These include metal-oxide-semiconductor (MOS), bipolar, and combined bipolar and complementary-MOS (BiCMOS). While silicon-based processing dominates in semiconductor manufacturing, gallium arsenide (GaAs), a compound- semiconductor material, is a niche alternative to silicon for some applications.

Marketshare IC (Percent of Total Dollars) Manufacturing 1997 Status Process 1997 2002 1970 1980 1990 Technologies (EST) (FCST) MOS (total): 35 52 75 ~69 ~87 PMOS Obsolete 31 5 — — —

NMOS/HMOS Virtually obsolete 2 37 10 <1 <1

CMOS Mainstream MOS technology, with continued 2 10 65 69 86 growth.

Bipolar (total): 65 48 24 ~12 ~10

ECL Fastest silicon-based process, but losing to 3 3 3 <1 <1 GaAs. Virtually obsolete.

TTL Virtually obsolete. 29 8 2 <1 —

S/LS TTL Virtually obsolete, having lost to MOS ASICs 7 13 4 1 <1 designs.

LINEAR Mainstream analog technology, but 26 24 15 11 8 competition from CMOS, and GaAs.

BiCMOS: Offers both MOS and bipolar advantages, but — — 1 18 5 slipping from high cost/complexity.

GaAs: Still niche technology, but future potential. — — <1 1 1

Source: ICE 11218W

Figure 4-1. Market Share Overview of IC Manufacturing Process Technologies

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Within MOS and bipolar manufacturing process technologies, device design variations have emerged and declined as IC applications and complexities have changed. Historically, back in 1970 bipolar was the major technology of choice; it was used for almost 66 percent of the total IC market. By 1980, that share had fallen to less than 50 percent. Last year, in 1997, bipolar ICs accounted for less than 14 percent of the IC dollar volume shipped.

Interestingly, while bipolar ICs rep- resent a small proportion of today’s

MOS IC market, they still represent nearly Logic half the ICs (i.e., unit volume) 24% shipped in 1997 (Figure 4-2). In addition, bipolar linear technology, Bipolar 1997 MOS* Analog which is the mainstream technology 57.3B 53% 41% Bipolar 47% (EST) for analog ICs, easily accounts for MOS the largest number of IC units Memory 13% shipped in all technology categories.

MOS BiCMOS offers IC designers both Micro 12% bipolar and CMOS advantages; ICs can be designed with the best Bipolar devices for each part of the circuit. Digital MOS/BiMOS 6% Analog However, the process complexity of 4% * Includes BiCMOS BiCMOS, which requires more Source: ICE 21390B wafer-fabrication processing steps,

Figure 4-2. MOS and Bipolar IC Unit Volumes has kept it from rising in the semi- conductor industry and is the reason behind its anticipated decline.

From 1997 to 2002, ICE forecasts that BiCMOS ICs will show a –3 percent cumulative-average annual growth rate (CAGR), declining from its current level at $18.9 billion to $16.1 billion or only five percent of the forecasted 2002 IC market. Specifically, this decline is a result of one manufac- turer, Intel’s plan to convert its Pentium and Pentium Pro microprocessors from BiCMOS to CMOS technology.

The emphasis in 1998 is still on CMOS technology, as it has been throughout the 1990s. ICE esti- mates that CMOS-based ICs will represent 69 percent of the final IC market for 1997 (Figure 4-3). By the year 2002, the market share forecast for CMOS ICs will likely increase to 86 percent of the total IC dollar volume.

4-2 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Device and Packaging Technology Trends

Other 6%

Bipolar 8%

Other 19%

Bipolar 1997 (EST) 2002 (FCST) 12% $127.2B $349.5B

CMOS 69% CMOS 86%

Source: ICE 20282E

Figure 4-3. CMOS IC Process Technology Dominance

No technology of the past has dominated the IC market like CMOS does today; it is the technol- ogy behind news-grabbing multi-million transistor ICs and the systems that use them. The wide- spread use of CMOS comes from the combination of high density (i.e., sub-micron circuit features), low power dissipation, and scalability. The latter gives a manufacturer the capability to reduce the size of a given IC design one or more times thereby enhancing manufacturing produc- tivity and corporate profitability.

The dominance of CMOS, at the expense of other IC design and process technologies, cannot be ignored (Figure 4-4). However, as it first did in 1996, in 1997 the market share of CMOS ICs dropped from its previous year value. This is not an indicator of declining CMOS applications, but is due to continuing lower prices for MOS memories, dynamic random access memories (DRAMs) in particular. It can also be attributed to a growing BiCMOS IC market, a result of the strength in demand for BiCMOS-based Pentium microprocessors, prior to Intel’s planned switch to CMOS. Clearly, the dominance of CMOS ICs will turn its market share up again in 1998 as it climbs to 86% by 2002.

While physics dictates that CMOS technology is inherently slower than the emitter-coupled logic (ECL) bipolar technology, for example, so much research and development has gone into CMOS design and process technologies, that today its speed and output drive capabilities rival that of some bipolar devices (Figure 4-5).

All IC manufacturing processes go through a bell-curve life cycle (Figure 4-6). What is interesting about CMOS technology is that it has been at the maturity stage since the mid-1980s with little movement. ICE expects that CMOS will still be in its maturity stage well into the twenty-first cen- tury. Through the end 1997, there was no new technology that showed the potential to dethrone CMOS as the mainstream IC process in the foreseeable future. Cost effectiveness, steadily increas- ing performance, and consistently high levels of investment in research and development by IC manufacturers will keep CMOS the mainstream technology throughout the 1990s and beyond.

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<1% <1% ECL <1% TTL <1% 1% 1% GaAs 100 AND OTHER 4% ECL 4% 8% BIPOLAR 1% <1% 90 TTL AND 12% 11% 11% 19% OTHER 1% 80 <1% <1% BIPOLAR 20% 70 ANALOG 22% 60 <1% PMOS 86% 69% 2% 24% 50 71%

PERCENT MOS 40 NMOS 41% 30

20 39%

10 CMOS BiCMOS 18% 12% 16% 5% 0 1982 1987 1996 2002 $10.2B $29.0B $117.9B $349.5B (FCST) 1997 $127.2B YEAR (EST) Source: ICE 12070V

Figure 4-4. 1982-2002 IC Technology Market Trends ($)

Logic Families Typical Commercial Parameter (0° to 70°C) TTL/ABT CMOS ECL LS ALS ABT FAST MG HC FACT LVC LCX 10KH 100K ECLinPS Lite Speed "OR"-Gate Prop. Delay (tPLH) (ns) 9 7 2.7 3 25 8 5 3.3 3.3 1 0.75 0.33 0.22 D Flip-Flop Toggle Rate (MHz) 33 45 200 125 4 45 160 200 200 330 400 1,000 2,800 Output Edge Rate (ns) 6 3 3 2 100 4 2 3.7 3.6 1 0.7 0.5 0.25 Power Consumption (per gate) Quiescent (mW) 5 1.2 0.005 12.5 0.0006 0.003 0.003 0.0001 0.0001 25 50 25 73 Operating (at 1 MHz) (mW) 5 1.2 1.0 12.5 0.04 0.6 0.8 0.6 0.3 25 50 25 73 Supply Voltage (V) 4.5 to 4.5 to 4.5 to 4.5 to 3 to 2 to 2 to 1.2 to 2 to Ð4.5 to Ð4.2 to Ð4.2 to Ð4.5 to 5.5 5.5 5.5 5.5 18 6 6 3.6 3.6 Ð5.5 Ð4.8 Ð5.5 Ð5.5 Output Drive (mA) 8 8 32/64 20 1 4 24 24 24 50-Ω load 50- Ω load 50-Ω load 50-Ω load DC Noise Margin High Input (%) 22 22 22 22 30 30 30 30 30 28 41 28/41 33 Low Input (%) 10 10 10 10 30 30 30 30 30 31 31 31/31 33 Functional Device Types 190 210 50 110 125 103 80 35 27 64 44 48 40 Price/Gate (relative, 1 to 25 qty) 0.9 1 1.6 1 0.9 0.9 1.4 1.8 1.8 2 10 25 32 (LS) Motorola Low-Power Schottky TTL (FACT) Motorola Advanced CMOS (ALS) Texas Instruments Advanced Low-Power Schottky TTL (LCX) Motorola Low-Voltage CMOS (ABT) Philips Semiconductor Advanced BiCMOS (LVC) Philips Low-Voltage CMOS (FAST) Motorola Advanced Schottky TTL (10KH) Motorola 10KH Series ECL (MG) Motorola 14000 Series Metal-Gate CMOS (100K) National 100K Series ECL (HC) Motorola High-Speed Silicon-Gate CMOS (ECLinPS and ECLinPS Lite) Motorola Advanced ECL Source: Electronic Products/ICE 21745

Figure 4-5. Comparison of CMOS, Bipolar, and BiCMOS Logic Families

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CMOS

BIPOLAR BiCMOS ANALOG GaAs S/LS TTL

ECL

HMOS TTL Diamond SiGe PMOS NMOS

Introduction Growth Maturity Saturation Decline Obsolete

Source: ICE 16809J

Figure 4-6. Process Technology Lifecycle (1997)

MOS ICs

Figures 4-7 and 4-8 show the various MOS IC markets in dollars; evidence of the dominance and popularity of CMOS is clear in this data.

100 4% PMOS <1% <1% <1% <1% 90

80 40% NMOS 70

74% 60 >99% >99% >99% 50 PERCENT 40

30 60%

20 CMOS

10 22%

0 1982 1987 1996 2002 $5.5B $18.4B $83.9B $299.7B 1997 (FCST) $87.7B (EST) Year Source: ICE 12072V

Figure 4-7. 1982-2002 MOS (Excluding BiCMOS) Technology Market Trends

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2002 1987 - 2002 1987 1996 1997 Technology ($M, CAGR ($M) ($M) ($M, EST) FCST) (Percent)

NMOS and PMOS 7,350 475 445 150 Ð23

CMOS 11,050 83,395 87,270 299,591 25

Total 18,400 83,870 87,715 299,741 20

Source: ICE 16811N

Figure 4-8. MOS Technology Market Trends (1987-2002)

It is common industry knowledge that n-channel MOS (NMOS) replaced the slower and more power-hungry p-channel MOS (PMOS) technology in the 1970s, and CMOS supplanted NMOS in the 1980s. Today, as the data show, CMOS represents basically all of the total MOS market. Historically, CMOS became the technology of choice for MOS memory as memory density reached and surpassed 1 megabit (1M). In addition, the swelling complexity and density of other IC types like microprocessors and application specific ICs (ASICs) require the scalability and low power consumption benefits of CMOS. All 1M and denser DRAMs have thus far been produced using CMOS technology.

The inherent advantages of CMOS include:

• Design and process experience. • Available from numerous device manufacturers. • Lowest price per function compared to other technologies at the same geometry. • Low power consumption. • High scalability with lithography process evolution. • Relatively good noise immunity and soft error protection. • Low threshold bias sensitivity. • Design simplicity and relatively easy layout, especially for ASICs. • Capability for lower power analog and digital circuitry on the same chip.

ICE projects that CMOS will dominate the semiconductor industry well into the future. Indeed, CMOS seems to have the life it needs to continue evolving to meet the majority of IC performance demands. We have already seen a decline from conventional 5V power supply to 3.3V, and lower, on devices with 0.35 µm geometries and gate oxides less than 100Å (Figure 4-9). Now, with the industry moving to feature sizes of 0.25µm and below, a 3.3V power supply is becoming imprac- tical and designers are looking at 2.5V or even 1.8V (Figure 4-10).

The trend with CMOS supply voltage is a good illustration of the degree of synergy that has been required over the past few years between system designers and IC designers. In the transition from 5V to lower voltage systems, system designers have been using several voltages on the same printed circuit board (Figure 4-11); this trend peaked in 1996 and is now declining. Still, however,

4-6 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Device and Packaging Technology Trends

semiconductor manufacturer Lucent Technologies, for example, offers a standard cell library that allows the user to mix and match 5V and 3V cells on the same chip. Other companies that are con- tinuing to help bridge the 5V to lower-voltage gap with mixed-voltage ICs include Oki, Texas Instruments (TI), Toshiba, Atmel, and Symbios Logic.

160

140 Published Data Trend Line 120 ) Å 100

80

60

Gate Oxide Thickness ( 40

20

0 0 0.1 0.2 0.3 0.4 0.5 0.6 Gate Length (µm) Source: Intel 20284A

Figure 4-9. Gate Oxide Versus Gate Length

For 1998, the transition to voltage supplies other that 5V and the decline of mixed voltage systems continues. It is estimated that most of the 2002 IC market will be served by 3.3V; already all 64M DRAMs are designed for 3.3V power supply.

One of the drawbacks to moving to lower voltage levels is the difficulty in improving performance at the same rate as was accomplished using 5V. As shown in Figure 4-12, low-voltage technology performance is expected to double every four generations as opposed to every two generations when using 5V. Figure 4-13 looks at some of the driving factors affecting the move to low-voltage device technology.

Even in 1997, the first ICs based on ≤0.25µm CMOS technology were coming to market, about a year earlier than expected. Figure 4-14 compares several microprocessor-oriented 0.25µm processes. The routing index shown in the figure was calculated by MicroDesign Resources in an attempt to capture the circuit density of the processes. This index and the tabulated values sug- gest that IBM’s CMOS-6X and TI’s C07 offer the best circuit density, but IBM’s process is more costly because of its additional metal layer and local interconnect.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-7 IC Device and Packaging Technology Trends

6

5 Published Data

Trend Line 4

3

2 Operating Voltage (V)

1

0 0 0.1 0.2 0.3 0.4 0.5 0.6 Gate Length (µm)

Source: Intel 20285A

Figure 4-10. Gate Length Versus Operating Voltage

100

90

80

70 5V 60

50

40 3V

30 Percentage of Design Starts

20 5/3V 10 2.xV 0 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 Year Source: VLSI Technology 19179A

Figure 4-11. Transition from 5V to 3V Systems

4-8 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Device and Packaging Technology Trends

1.0 350 0.9 315 0.8 280 0.7 245 0.6 Speed Doubles Every 210 2 Generations 0.5 175

0.4 140

0.3 105 3.3V 2.2V 1.5V 0.2 5V 70

Gate Delay (Arbitrary Units) (Low Power) 3.3V Unloaded Inverter Delay (ps)

Speed Doubles Every 4 Generations (High Speed) 2.2V 0.1 35 2µm 1µm 0.5µm 0.25µm 0.13µm

Technology Generation Source: ISSCC94/UC Berkeley 19499

Figure 4-12. Low Power Speed Lag

Primary Feature Feature Driver Products Pros and Cons

Continued requirements for DRAMs Slowest voltage versus time higher integration density evolution SRAMs Integration density drives scaling Not a driver for revolutionary Device device technology changes Physics Scaling drives device physics Not a good test bed for non- Device physics limit operating device power reduction voltage, resulting in lower power techniques

High integration density circuits MPUs Basic cell performance may operating at maximum start to diminish; power limited performance bump against DSPs performance not compensated High package power constraint by scaling Performance ASICs Reduced power achieved by Increased performance will lower operating voltage or Full custom require non-device and non- design modifications scaling solutions: systems circuits

Battery life as key operator MCUs Fastest voltage versus time driver

May compromise integration DSPs Non-traditional technology driver density Portable Frequency Drives revolutionary device Products May not require peak Control technologies: GaAs, modified performance (frequency, CMOS, mixed technologies delays, MIPS) RF/Analog and Digital Lacks industry infrastructure and Some specialized products volume support base

Source: Motorola 20287A

Figure 4-13. Voltage Reduction Drivers

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Vendor AMD Digital Fujitsu IBM* IDT Intel TI Process Name CS-44 CMOS-7 CS-70 CMOS-6X CEMOS-10+ P856 C07 Example Product K6+ 21264+ n/a PPC 60x+ n/a Deschutes n/a First Production 2H97 1H98 2H97 2H97 1H98 3Q97 3Q97 Supply Voltage 2.5V 1.8V 2.5V 1.8V 2.5V 1.8V 1.8V I/O Voltage (Max) 3.3V 3.3V 3.3V 3.3V 3.3V 2.5V 3.3V Gate length (Drawn) 0.25µm 0.25µm 0.24µm <0.25µm 0.25µm <0.25µm 0.21µm Channel length (Effective) 0.18µm 0.16µm 0.18µm n/a 0.20µm n/a 0.17µm Gate Oxide Thickness n/a 45Å 55Å 40Å 65Å 45Å 40Å Number of Metal layers 5 metal 6 metal 5 metal 6 metal 4 metal 5 metal 5 metal Local Interconnect? yes no yes yes no no no Stacked Vias? yes yes yes yes yes yes yes M1 Contacted Pitch 0.88µm 0.84µm 0.9µm 0.7µm 0.94µm 0.64µm 0.85µm M2 Contacted Pitch 0.88µm 0.84µm 0.9µm 0.9µm 1.1µm 0.93µm 0.85µm M3 Contacted Pitch 0.88µm 1.7µm 0.9µm 0.9µm 1.1µm 0.93µm 0.85µm M4 Contacted Pitch 1.13µm 1.7µm 0.9µm 0.9µm 1.1µm 1.6µm 0.85µm M5 Contacted Pitch 3.0µm 1.7µm 2.7µm 0.9µm 1.4µm 2.6µm 2.5µm SRAM Cell Size n/a 11.5µm2 n/a 8.6µm2 11.2µm2 10.3µm2 10.5µm2 Routing Index 0.60µm2 1.1µm2 0.62µm2 0.53µm2 1.0µm2 0.67µm2 0.56µm2 Wafer Cost Index $4.0 $3.5 $4.0 $4.7 $3.6 $4.0 $4.1 * Motorola's PPC4 is similar to CMOS-6X but may have smaller gates. + indicates shrink version. Source: MicroDesign Resources 21747A

Figure 4-14. A Look at Some 0.25µm Processes

Gate Length The development of next-genera- Drawn 0.18µm tion 0.18µm CMOS technology is Effective 0.13µm already well underway with Inverter Delay 25ps/stage volume production of ICs with Power Consumption 11.6nW/µm 0.18µm geometries (drawn gate Supply Voltage 1.8V length) expected to start as early as Cutoff Frequency pFET 40GHz 1999, two years earlier than nFET 72GHz expected. TI released details of a Number of Metal Layers 6 0.18µm CMOS logic process in Gate Oxide Thickness 4nm June, 1997. Characteristics of the Other Features A new low-k insulating material, process are shown in Figure 4-15. low-resistivity metal, shallow trench isolation, and a sputtered TI believes potential applications tungsten-silicide step for the process include single-chip Source: EETimes/TI 22747 digital radios and optical commu- nications chips. Figure 4-15. A Peek at TI’s Next-Generation 0.18µm Process Technology

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While 0.1µm CMOS technology is not expected to be in widespread use before 2000, many large IC producers with advanced research labs are already releasing data on such devices. Figure 4-16 shows Fujitsu’s preliminary 0.1µm CMOS process parameters.

Parameter NMOS PMOS

Starting Material 10Ωcm p-type (100) 10Ωcm p-type (100)

Well Twin Well Twin Well

Isolation 350nm LOCOS 350nm LOCOS

Channel Implant B+, 40keV, 7 x 1012 As+, 180keV, 5 x 1012

Gate Oxide 3.9nm (800°C) 3.9nm (800°C)

Gate Stack Poly-Si 160nm + SiO2 50nm Poly-Si 160nm + SiO2 50nm + 13 + 14 Shallow Junction Implant As , 10keV, 4 x 10 BF2 , 5keV, 1 x 10 Spacer SiN 60nm SiN 60nm + 15 + 15 Deep Junction Implant As , 30keV, 3.2 x 10 BF2 , 20keV, 5 x 10 Anneal 850°C, 5 minutes 850°C, 5 minutes Source: Fujitsu/IEDM 19214A

Figure 4-16. Process Parameters of 0.1µm CMOS

Bipolar ICs

Figures 4-17 and 4-18 show the bipolar IC market in dollars. Although the bipolar segment is shrinking in IC market share (from an estimated 11 percent in 1997 to about eight percent in 2002), the total bipolar dollar volume is forecast to display a 13 percent CAGR from 1997 to 2002.

Bipolar IC technology has survived along side the dominance of CMOS IC technology to remain strong on two fronts: for analog ICs and for very high speed driver ICs. Both these product areas exploit the inherent capabilities of the bipolar transistor.

Bipolar technology remains popular in analog ICs because of the better gain and power handling capabilities of the bipolar transistor, as well as the fact that bipolar analog chips tend to be more rugged than their CMOS counterparts.

For digital applications, bipolar ICs still find design wins in very high speed applications, such as communications and mainframe computers. In other digital applications, on the other hand, bipolar technology has lost most of the advantages it once had over CMOS. Bipolar ICs consume a great deal of power per logic function, so when the highest absolute speed is not required, CMOS is the better solution. Figure 4-19 shows that the market for digital bipolar ICs is declining in each of the product areas listed.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-11 IC Device and Packaging Technology Trends

1%

100 5% 4% 10% ECL 12% 2% 7% 90 9%

80

TTL AND 70 42% OTHER

60

97% 50 89% 97% Percent 86% 89% 86% 40

30 56% ANALOG 56% 48% 20

10

0 1982 1987 1996 2002 $4.6B $10.6B $14.5B $31.0B 1997 (FCST) $15.4B (EST) Year Source: ICE 12073V

Figure 4-17. 1982-2002 Bipolar Technology Trends ($)

1987 Ð 2002 1987 1996 1997 2002 Technology CAGR ($M) ($M) ($M, EST) ($M, FCST) (Percent)

ECL 1,265 735 660 375 Ð8

TTL and Other 3,400 1,270 990 463 Ð12

Bipolar Analog 5,935 12,525 13,735 30,122 11

Total 10,600 14,530 15,385 30,960 7

Source: ICE 16812N

Figure 4-18. Bipolar Technology Market Trends (1987-2002)

For digital applications, inherently, bipolar ECL devices are very uniform, stable, and generate low noise. Also, ECL requires only a 1V swing in 3-4ns compared with a typical bipolar transis- tor-transistor logic (TTL) chip that requires a 5V swing in the same time frame. ECL-based ICs include gate array ASICs, standard and special purpose logic devices, and static random access memory (SRAM) ICs (Figure 4-20).

4-12 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Device and Packaging Technology Trends

1996 - 2002 1996 1997 2002 Product CAGR ($M) ($M, EST) ($M, FCST) (Percent)

General Purpose Logic 895 785 438 Ð11 Special Purpose Logic 365 230 90 Ð21 Gate Array/Std. Cell 510 460 245 Ð12 MPU/MCU/MPR 10 5 — Ð100 FPL 65 40 11 Ð26 Memory 160 130 54 Ð17 Total 2,005 1,650 838 Ð14

Source: ICE 18881H

Figure 4-19. Digital Bipolar IC Market

Logic* 15% Memory 1992 19% $1,320M ASIC 66%

Memory Memory 15% 13% 1997 2002 ASIC (EST) ASIC (FCST) 49% Logic* $660M 50% Logic* $375M 35% 38%

*Includes General and Special Purpose Logic Source: ICE 21085D

Figure 4-20. ECL IC Market by Product Group

Japanese semiconductor manufacturers have traditionally had the largest ECL IC market share primarily because of their emphasis on mainframe computers. However, computer manufactur- ers NEC and Fujitsu have revamped their mainframe lines to use CMOS ICs, and Hitachi has moved to BiCMOS parts.

The movement to using other technologies besides ECL for high-speed systems is especially dev- astating to the large military ECL IC market. The lackluster military IC market coupled with the increasing use of CMOS, GaAs, and BiCMOS ICs will heavily contribute to the declining ECL IC industry through the end of the 1990s.

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BiCMOS ICs

BiCMOS technology has long been thought of as a high-speed replacement for pure CMOS because it offers a performance edge by implementing both CMOS and bipolar transistors on the same chip. Through the selective use of CMOS and bipolar circuitry, high-performance paths can be created with bipolar, while lower-performance, high-density paths can be created with CMOS gates. More recently though, the growth in demand for mixed-signal ICs has been driving greater use of BiCMOS technology.

BiCMOS architecture that consists of a small percentage of bipolar transistors is called CMOS- based. For this architecture, non-critical paths on the majority of the chip consist of CMOS gates, while bipolar transistors are used mainly for driving long metal lines and as output buffers for critical paths. This is the most common type of BiCMOS technology.

Bipolar-based BiCMOS IC architecture consists of predominantly bipolar transistors with CMOS transistors available for the implementation of large storage elements. The resulting IC offers excellent performance and density with a high level of programmability.

The main disadvantage of BiCMOS is the manufacturing cost penalty created by the complicated process of building both bipolar and MOS transistors into a single IC. It is partly because of this increased complexity that Intel is moving its Pentium microprocessor (MPU) series from a 20- mask BiCMOS process to a 16-mask pure CMOS process technology. Another reason stated by the company is that while bipolar transistors provide some performance boost at 3.3V, the gain is insignificant at 2.5V and below.

Because the performance advantage of BiCMOS decreases with lower voltage levels, the future of BiCMOS in the systems of the late-1990s depends on the ability to economically produce spe- cialized BiCMOS processes. For example, Motorola has a specialized BiCMOS process that tar- gets ASIC, very high-speed, and low-voltage applications. The supply voltage versus 0.5µm BiCMOS manufacturing complexity issues will especially challenge the BiCMOS producers in the late-1990s.

As shown in Figure 4-21, the BiCMOS market was led by microcomponent (i.e., Pentium like) products in 1997. The total BiCMOS IC market is expected to decline at a three percent average annual rate from 1997-2002, and represent only five percent of the total IC market in 2002. This decline is due to Intel’s plan to move its advanced microprocessor products from BiCMOS to CMOS in the late 1990s. Intel’s first pure-CMOS Pentiums started to appear in 1997, as the com- pany moved into a 0.28µm process. In summary, the timing and completeness of Intel’s conver- sion will have a tremendous impact on the total BiCMOS market figures in the late 1990s.

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Standard Gate Arrays Standard 2% Logic Logic SRAMs 1% 3% Other 2% Gate Other Microcomponents 1% Standard <1% 6% Arrays 4% Analog/ Cell 3% SRAMs Mixed Signal 6% 15% Analog/ 1997 (EST) 2002 (FCST) Mixed Signal $23,300M Standard Cell $16,100M 63% 17% Microcomponents 77%

Source: ICE 13643S

Figure 4-21. Worldwide BiCMOS Market

Besides the Pentium-dominated microcomponent area, the analog-mixed-signal IC segment is a strong market for BiCMOS ICs. In fact, by the turn of the century, analog-mixed-signal ICs are expected to take over the top market share position in the BiCMOS market. BiCMOS is also pop- ular for very high-speed SRAMs, with the access times of some BiCMOS SRAMs stated to be half those of most CMOS SRAMs of the same density. Furthermore, ECL SRAMs can’t match BiCMOS densities.

As shown in Figure 4-22, Intel is by far the largest producer of BiCMOS ICs. Two European semi- conductor manufacturers—Philips and SGS-Thomson—are also heavily involved in BiCMOS technology, with the focus of both being on analog and mixed-signal ICs. Motorola’s BiCMOS ICs encompass a variety of products, including memory, ASIC, logic, and analog ICs.

Company 1996 Sales ($M)

Intel 14,160 SGS-Thomson 1,390 Philips 1,100 Texas Instruments* 370 Motorola 350 Fujitsu 160 NEC 160 Analog Devices 130 Alcatel-Mietec 110 Others 950 Total 18,880 *Acquired the major BiCMOS IC supplier, Silicon Systems, in 1996. Source: ICE 21084D

Figure 4-22. Major BiCMOS IC Suppliers

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The following are the past-year’s significant BiCMOS business and technology announcements:

• Exponential Technology canceled its PowerPC-compatible X704 BiCMOS microprocessor program and closed its main office in San Jose. The super high performance chip design was complete and ready to begin shipments at speeds of 410MHz, but, the primary customer for the part, Apple Computer, withdrew its plans to ship X704-based systems. Apple reportedly decided to stick with the multisourced PowerPC microprocessor that fits into standard sys- tems rather than modifying its products to deal with the extra heat and unique socket of the single-sourced Exponential microprocessor.

• Micro Linear announced the addition of four new products to its family of 10Base-FL Ethernet transceiver products that are implemented in an advanced BiCMOS process. The company claims that the use of a BiCMOS process results in a reduction in power dissipa- tion of up to 35 percent.

• NEC introduced four 200MHz 4M synchronous SRAMs implemented in a 0.35µm BiCMOS process. The SRAMs are intended for use as cache memory for reduced instruction set com- puting (RISC) processors in high-end workstations.

Gallium-Arsenide ICs

Gallium-arsenide (GaAs) compound-semiconductor material has an inherent speed advantage over silicon. However, for years the relative high cost of GaAs wafers, problems with breakage during processing (the material is very brittle), and the higher defect density with the corre- sponding lower device yields have kept market penetration lower than anticipated. Today, due mainly to the booming telecommunications end-use market over the past several years, GaAs IC manufacturers are experiencing healthy double digit market growth.

GaAs technology continues to advance by shrinking device geometries and using more industry standard low-cost packaging, and through GaAs IC manufacturers developing a better under- standing of how to work with this compound semiconductor material. All these factor continue to help make GaAs ICs approach cost competitiveness with silicon.

The total GaAs market (excluding development funding) is forecast to have a 1997-2002 CAGR of 27 percent, growing to about $2.7 billion in 2002 (Figure 4-23). As also shown in the figure, growth in the demand for analog GaAs ICs is expected to significantly outpace that for digital GaAs ICs into the next century, as it has over the past years. Analog ICs represented about 72 percent of the GaAs IC market in 1997, and that share is expected to increase to 83 percent by 2002.

4-16 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Device and Packaging Technology Trends

2,800 2,765

2,600 Analog IC Sales 2,400

Digital IC Sales 2,160

2,200

2,000 Development Funding

1,800 1,690 1,600 2,295

1,400 1,330 1,775 1,200 1,055 Millions of Dollars 1,000 885 1,365 800 720 1,055 590 820 600 520 640 435 500

400 395 395

240 55 60 60 365 450 200 2020203052020 95 120 140 160 185 215 255 100 90 0 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 Year *Includes development funding. Source: ICE 17134K

Figure 4-23. Worldwide GaAs IC Merchant Market* Forecast

Figure 4-24 shows the GaAs IC market by end-use market. Clearly, the current growth of GaAs semiconductor technology is a direct result of telecommunications applications. Some of today’s most attractive market areas for GaAs technology are cellular phones, digital personal communi- cations systems, local networks, satellites, broad-band tuners, automotive sensors, and sophisti- cated space systems. High-speed computing and fiber-optic applications may offer substantial volumes for high-performance GaAs devices as well. Several applications for analog GaAs ICs are shown in Figure 4-25, while digital GaAs IC applications are shown in Figure 4-26.

Consumer Consumer 8% Military/ 9% Other 6% Aerospace Other 4% 9% Computer Computer 10% 13% Military/ Aerospace 1997 (EST) 2002 (FCST) 17% $825M $2,745M Telecom Telecom 56% 68%

*Not including development funding. Source: ICE 13329Q

Figure 4-24. Total GaAs IC Market* by End Use

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-17 IC Device and Packaging Technology Trends

Mobile Satellite Fiber-Optic Wireless Data Communications Receivers Communications Communications

¥ Cellular Telephones ¥ Global Positioning System ¥ Long-Haul ¥ Wireless LANs ¥ Cordless Telephones ¥ Very Small Aperture Terminals ¥ LANs ¥ WANs ¥ Personal Communications Networks ¥ Mobile Satellite Systems ¥ WANs ¥ Pagers ¥ Microwave Radio Links ¥ Fixed Satellite Systems ¥ Local Loop

Source: Epitaxial Products International 21749

Figure 4-25. Communications Applications for GaAs Analog ICs

High Speed Telecommunications: ¥ DEMUX, MUX, high-speed logic paths, decision circuits, and switching. ¥ Require high-speed, low power for SONET, SDW, ATM, and ISDN (up to 2.5GHz). Data Telecommunications: ¥ High-speed serial data communications between mainframes, servers, workstations, and peripherals. ¥ Standards requiring GaAs performance include HiPPI, FDDI, SCI, ESCON, and FCS. Automatic Test Equipment: ¥ Replaces ECL in applications requiring low power, lower cost, and improved performance. High Speed Computing: ¥ Collapse of Cray Computer was big set back.

¥ Some major players still looking at GaAs, including: Fujitsu, HP, Unisys, ARPA (US), and IBM.

Source: Epitaxial Products International 21750

Figure 4-26. Primary Applications for Digital GaAs ICs

Historically, at first the military and aerospace industries were expected to provide a large market for GaAs technology, since customers in those areas would likely pay the higher prices for GaAs ICs to bypass silicon’s speed limits in microwave communications and radar. However, steep government spending cuts on defense put a damper on that expectation. Then, GaAs was expected to make next-generation supercomputers lightning fast, allowing the technology to finally shed its niche-market image. But that expectation faded too because advances in silicon allowed multiple-silicon-chip systems to do it, for less. In recent years, the booming market for communications equipment has led to the commercial success of GaAs IC technology.

High-volume use of analog GaAs ICs in 2.4GHz and higher performance wireless communica- tions is almost guaranteed. At speeds below 500 to 800MHz, silicon is almost always the better choice. However, beginning at 800 to 900MHz and above, the contest is much closer, and above 2.4GHz, GaAs devices are almost always superior. GaAs also offers comparable or better low- noise performance, low-voltage operation, and better system level cost and performance begin- ning in the gigahertz range.

4-18 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Device and Packaging Technology Trends

Currently the GaAs IC industry is dominated by planar-type structured circuits, so-called junction field effect transistor (JFET) and metal semiconductor FET (MESFET) technologies. But, het- erostructure-type circuits, such as heterojunction bipolar transistor (HBT), high-electron-mobility transistor (HEMT), and pseudomorphic HEMT (PHEMT) ICs are gaining wider acceptance. HBTs and HEMTs are generally considered more efficient than conventional MESFETs, especially at high frequencies, but are more difficult and expensive to manufacture. HBTs and HEMTs are not expected to replace MESFETs, but will be widely used in emerging high-frequency applications.

GaAs MOSFET technology is highly desirable because it could give gallium-arsenide technology the same low power and high density capabilities enabled by silicon-based CMOS technology. In general, the impurity and poor quality of gallium oxides have been the stumbling blocks for GaAs MOSFETs. Work in 1996 at Bell Labs disclosed a special technique for depositing a special formu- lation of gallium oxide as the gate dielectric on a GaAs semi-insulating substrate to fabricate both p-channel and n-channel MOSFETs (Figure 4-27). This is promising work that could accelerate GaAs into what are otherwise still silicon-dominated applications, but there is still much more work to be done before commercial products can be realized.

Oxide (Ga2O3) Gate

Source Drain

P- P- P+ P+

Source: Electronic News 22720

Figure 4-27. P-Channel GaAs MOSFET Fabricated by Bell Labs

Because of strong GaAs IC sales into communications applications, the list of major GaAs manu- facturers continues to show strong growth in sales (Figure 4-28).

The healthy market for GaAs manufacturers is also indicated by their continued capacity expan- sions. For example, Vitesse Semiconductor is building a new $75 million 150mm GaAs wafer fab- rication facility in Colorado Springs, Colorado, which is slated for completion in the second half of 1998. And, previously fabless RF Micro Devices is building its first 100mm GaAs wafer fabri- cation facility in Greensboro, North Carolina, with a start date in the first quarter of 1998.

The following are the past-year’s significant GaAs business and technology announcements:

• TriQuint unveiled a new GaAs process technology for highly integrated RF front ends. Integrating enhancement and depletion-mode MESFETs, power MESFETs, and three layers of metal interconnect, the TQTRx 0.6µm process allows designers to combine transmit and receive circuitry on the same chip.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-19 IC Device and Packaging Technology Trends

• In an attempt to keep up with shorter product design cycles, Fujitsu revealed plans to con- solidate all its compound semiconductor businesses, from development to sales, in one unit at its production subsidiary, Fujitsu Quantum Devices, Yamanashi, Japan.

• Vitesse entered the standard cell ASIC business with the introduction of its SLX family of prod- ucts. The SLX ICs are based on Vitesse’s 0.4µm, four-layer-metal GaAs process and feature 15,000-220,000 raw gates (60-70 percent usable), 87 to 187 I/Os, 100ps worst-case delay, and advanced power management circuitry that powers down inactive portions of the chip.

• Anadigics introduced a dual-mode, dual-band amplifier that allows designers of digital cel- lular handsets to switch between 800MHz AMPS/DAMPS and 1,900MHz PCS operation. The chip is the first in a planned line of devices that the company intends to manufacture to address the issue of switching between the 18 or so existing standards in the cellular market.

1995 Sales* ($M) 1996 Sales* ($M) Company Analog Digital Total Analog Digital Total

Fujitsu 56 36 92 65 35 100 Anadigics 50 — 50 66 — 66 TriQuint 18 28 46 29 31 60 Vitesse 1 38 39 2 57 59 TI 30 5 35 42 3 45 Rockwell 22 6 28 28 7 35 Oki 27 5 32 29 4 33 Pacific Monolithics 22 — 22 30 — 30 UMS** 22 — 22 25 — 25 NEC 25 — 25 25 — 25 Others 122 22 144 159 23 182 Total 395 140 535 500 160 660 * Not including development funding. ** United Monolithic Semiconductors (UMS) is an independent joint venture of Thomson-CSF, TEMIC, and Daimler-Benz Aerospace that was formed in early 1996. Source: ICE 18111K

Figure 4-28. Major GaAs IC Suppliers

Silicon-Germanium ICs

As semiconductor manufacturers struggle to put more transistors on each chip and increase cir- cuit speed, the physical and electrical limitations of silicon become a major concern. For years, it was thought that GaAs would become the new wafer material of choice. However, even though the GaAs IC market is forecast to grow strongly through the end of the decade, it will still con- tinue to represent only a very small percentage of the total IC market.

4-20 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Device and Packaging Technology Trends

Back in 1991, IBM announced it was dropping its gallium-arsenide efforts in favor of silicon-ger- manium (SiGe) technology. Reported work from IBM shows that SiGe technology provides a 200- 300 percent increase in transistor speed with a minimal rise in production cost. Today, IBM is by most evaluations the leader in SiGe research and development, and even pilot production. Shown in Figure 4-29 is a cross section of an IBM high-performance FET designed using a 0.25µm BiCMOS SiGe process.

Source Gate Drain

SiO2

N+ Si

SiGe (30%)

Silicon

Silicon-Germanium (SiGe)

Silicon Channel Two Degree Electron Gas Silicon-Germanium Graded Buffer

Source: IBM Corp. 18736

Figure 4-29. IBM’s High-Performance SiGe FET

The concept behind SiGe is to add, through the doping process, the benefit of germanium’s high carrier mobility compared to silicon; electron mobility in silicon germanium is nearly twice that in pure silicon. (Electron mobility in germanium is 3,900cm2/Vs versus 1,500 in silicon. Hole mobil- ity is germanium is 1,900cm2/Vs versus 475 in silicon.) High mobility benefits both bipolar and field effect transistor (FET) devices.

Over the years, IBM has been working with several other IC manufacturers in the industry to com- mercialize products based on its SiGe process technology. For example, in the forth quarter of 1993, IBM and Analog Devices began working together to develop SiGe ICs targeting the wireless communications market and challenging GaAs applications at frequencies at or above 1GHz.

In addition, European semiconductor manufacturer, Telefunken Semiconductors, began volume production of a SiGe analog RF IC in 1996. The device contains 30 transistors, had a die size of two square millimeters with feature sizes of 1.0µm. It targeted 1.8GHz mobile telecommunica- tions GaAs applications.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-21 IC Device and Packaging Technology Trends

Late in 1997 and into 1998, IBM’s belief in SiGe-based IC technology seems to be paying off. For example, Canadian Nortel and IBM announced an agreement to work together to commercialize SiGe ICs for high-speed telecommunications applications. Nortel will design prototype ICs for fiber transport products and high-speed cellular and PCS wireless applications and IBM will man- ufacture the devices. IBM has a similar agreement with Hughes. ICE believes that in 1998 IBM and others will make similar announcements that will finally launch SiGe-based IC technology into the commercial market.

SiGe will not only be competing with GaAs, but also with BiCMOS and even bipolar technologies in the wireless communications market. The technology that gains the greatest market share will be the one that can economically meet the performance requirements of the growing number of high-performance applications.

Semiconductor Manufacturing Macrotrends

Conventionally, leading-edge technology has been predicted by Moore’s Law where the semicon- ductor industry’s complexity doubles every twenty-four months and semiconductor performance doubles every eighteen. As we enter 1998, this venerable maxim seems to be failing. According to the pending revised SIA National Technology Roadmap for Semiconductors (which was pending publication after ICE Status 1998 went to press) the industry is advancing at a pace that exceeds convention (Figure 4-30); the prediction is that by 1999 the industry will be two years ahead of where Moore’s Law says it should.

The previous 1994 SIA technology roadmap predicted that the 0.18µm device generation would arrive in 2001 and the 0.07µm generation in 2010. The revised roadmap pulls these dates closer, to 1999 and 2007, respectively. Many believe the two-year jump in the roadmap is possible because semiconductor manufacturers have discovered that they can build chips with 0.18µm geometries with the same wafer fabrication equipment that will be used for 0.25µm processing.

The industry’s accelerated move to smaller devices is increasing the need to address critical tech- nological challenges in design methodologies and tools, materials, process technology, processing- equipment development, and other areas before they develop into insurmountable roadblocks. Part of the task of the SIA roadmap’s authoring team of industry experts is to identify the issues and challenges that that the industry faces (Figure 4-31).

Feature Size Trends

Figure 4-32 shows feature sizes for loose and tight production resolutions (i.e., routine and advanced); tight production resolution has decreased from about 3µm in 1980 to around 0.25µm for leading-edge 1G DRAMs. This represents about a 15 percent decrease every year. This trend is expected to continue and feature sizes are forecast to be about 0.15µm by 2000 for tight pro- duction resolution.

4-22 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Device and Packaging Technology Trends

1997 1999 2001 2003 2006 2009 2012

Chip Generation (Feature Size in Microns) 0.25 0.18 0.15 0.13 0.10 0.07 0.05 DRAM (Bits) 256M 1G 2G 4G 16G 64G 256G Logic (Millions of Transistors per sq cm) 7 13 18 25 50 90 120 ASICs (Millions of Transistors per sq cm) 4 7 9 12 25 40 64 MPU Chip Size (sq. mm.) Year 1 300 360 400 430 520 620 750 Year 2 240 290 320 340 420 500 600 Year 3 180 220 240 260 310 370 450 DRAM Chip Size (sq mm) Year 1 280 400 480 560 790 1,120 1,580 Year 2 220 320 390 450 630 900 1,300 Year 3 170 240 290 340 480 670 950 Lithography Field Size (mm) 22x22 25x32 25x34 25x36 25x40 25x44 25x52 Number of Pins 512 512 654 768 768 1,024 1,280 On-Chip Clock Speed (MHz) 750 1,250 1,500 2,100 3,500 6,000 10,000 Minimum Mask Count 22 22-24 23 24 24-26 26-28 28

Source: SIA 22770A

Figure 4-30. Draft Version of Revised SIA Technology Roadmap

Process Concerns Component Design ¥ Lack of standards ¥ Built-in self-test ¥ Verification Test ¥ Equipment costs ¥ Testing at high frequencies ¥ Contacts for access Process Integration, ¥ Barrier materials for copper Devices and Structures ¥ Low materials ¥ New insulators and capacitors ¥ Stacking gate and source Factory Integration ¥ $1.4B to $2.4 costs ¥ Investment recovery ¥ Process complexity Front-End ¥ Copper eventually ineffective Process Challenges ¥ How to detect, eliminate material defects at atomic level Interconnect ¥ Reliability ¥ New materials integration Lithography ¥ Production-worthy systems for 0.13 micron ¥ X-ray, e-beam, extreme-UV ¥ Masks ¥ Advanced resists

Source: SIA 22748A

Figure 4-31. Technological Challenges Facing the Industry

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-23 IC Device and Packaging Technology Trends

10

Loose Production Resolution

Tight Production Resolution

µ 256K DRAM (2.0 m) µ (1.6 m) 1M DRAM HMOS II (1.2µm) (2.0µm) µ WE 32100 4M DRAM (1.0 m) 1 32-Bit MPU (0.8µm) µ HMOS IV (1.5 m) 16M DRAM (1.0µm) 4M DRAM (0.5µm) (0.8µm) (0.7µm) 64M DRAM 16M DRAM (0.35µm) 256M (0.5µm) Development DRAM Toshiba 64M DRAM (0.25µm) 1G µ (0.35µm) Microns (0.25 m) IBM DRAM (0.25µm) 256M (0.15µm) Gate Array DRAM Bell Labs µ (X-Ray) (0.25 m) (0.14µm) 1G DRAM 0.1 (0.15µm) Toshiba (0.1µm) 4G MIT (0.06µm) DRAM X-Ray (0.08µm)

Toshiba (0.04µm)

= Laboratory Research 0.01 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 00 02 Year Source: ICE 10981S

Figure 4-32. IC Feature Size Trends

Reportedly, the pending revised SIA National Technology Roadmap will show an interesting development; for the first time, microprocessors and logic ICs will be a generation ahead of DRAMs, the traditional technology driver for the industry (Figure 4-33). According to prelimi- nary roadmap data, pilot production has already begun on wafers with 0.2µm to 0.18µm feature sizes for advanced microprocessors and ASICs, compared to the 0.25µm level for DRAMs. By 2003, initial production of logic wafers will be at 0.11µm and DRAMs at 0.13µm. As shown in Figure 4-34, Intel expects that by 2001 about half of its volume production will be at the 0.18µm level, providing further evidence that high-margin products like microprocessors are being aggressively moved to smaller device geometries.

Deep-submicron technology has decreased the significance of gate length when it comes to deter- mining MOS circuit density. Today, a more accurate indicator is metal pitch, which is defined as the sum of the metal linewidth at a via and the space between the via and an adjacent line. It is a measure of how closely the metal lines are placed together. Thus, as shown in Figure 4-35, metal pitch sets the drain-to-source pitch in an individual transistor and the drain-to-drain pitch of isolated transistors.

Deep-submicron technology is closely linked to wafer fabrication lithography capability. Having survived various forecasted practical limits to its resolution, optical lithography is now on another threshold. But, once again, due to its relative low cost, familiarity and technical advancements,

4-24 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Device and Packaging Technology Trends

optical lithography is now forecast to be viable to 0.15µm, possibly 0.1µm. Despite the continu- ous predictions of its limitations, most see optical lithography as the mainstream technology into the turn of the century.

0.35 Existing Roadmap for all Devices

0.30 m)

µ 0.25

Proposed 0.20

Feature Size ( DRAM Roadmap

0.15 Proposed MPU/Logic Roadmap

0.10 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 Year

Source: Semiconductor Business News/SIA 22749

Figure 4-33. New SIA Roadmap Shows Logic Taking Over Memory as Technology Driver

Beyond this, a significant amount of research is being performed on extreme ultraviolet (EUV) lithography, which is expected to allow for the fabrication of ICs with feature sizes of 0.1µm and below. X-ray exposure techniques are also being aggressively developed for this region of pro- duction lithography. Interestingly, as occurred at past thresholds of optical lithography’s limits, the choices between optical, EUV, and x-ray, and even electron beam and ion beam technologies, are widely debated. Lithography is a complex mix of tools, energy sources, mask making, and resist chemistry; the latter always seems to lag the race, but has always arrived on time for opti- cal lithography in the past. Most experts cite 1998 as the decision year for determining which lith- ography technique will emerge for features sizes below 0.15µm.

The following are some of the past-year’s business and technology announcements that reflect production linewidth trends in the semiconductor industry:

• Hitachi Semiconductor America of Texas began installing wafer fab equipment to support 0.25µm processing. This technology will be used to launch production of the SH-4 300 MIPS RISC microcontroller.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-25 IC Device and Packaging Technology Trends

• NEC is investing more than $2 million to convert its Roseville, California, wafer fabrication facility into 0.18µm and 0.25µm lines to manufacture a third generation of 16M DRAM chips, high-performance ASICS and microcontrollers.

• Singapore’s Chartered Semiconductor Manufacturing, Taiwan Semiconductor Manufacturing, and Taiwan’s United Microelectronics all announced plans to convert from 0.35µm to 0.25µm wafer processing technology.

100 0.18µ µ 90 0.25 0.35µ 80 0.5µ and above

70

60

50

Percentage 40

30

20

10

0 1996 1997 1998 1999 2000 2001 Year Source: Intel 22750

Figure 4-34. Intel’s Expected Output by Geometry

Wiring Levels

The number of aluminum metal wiring levels has tripled in the last decade for both logic and memory products. For example, Figure 4-36 shows historical wiring level trends for IBM’s logic IC products through the mid-1990s. Today, five layers are common with 0.25µm process technol- ogy, with some companies using six.

The degree of difficulty with this number of aluminum wiring levels is eased somewhat with chemical mechanical polishing (CMP), which smoothes the surface of each interlayer dielectric insulator; CMP has been adopted by most manufacturers of high-performance ICs. With CMP, the surface of the IC remains planar, and thus, metal layers can be stacked vertically without the con- ventional problems associated with fabricating conformal metal patterns over steps.

4-26 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Device and Packaging Technology Trends

Gate Gate

Source Drain Drain Source

Source: Computer Design/VLSI Technology 21244

Figure 4-35. Influence of Metal Pitch on Deep-Submicron Device Layout

7

6

5

4

3

2 Number of Wiring Levels 1

0 '75 '77 '79 '81 '83 '85 '87 '89 '91 '93 '95 Year Source: IBM 21757

Figure 4-36. Historical Logic IC Wiring Level Trends

However, beyond five or six aluminum wiring levels, additional levels may not reduce die size enough to offset higher processing cost. For many years the talked about and sought after solu- tions have revolved around replacing aluminum with copper and replacing conventional silicon dioxide with a so-called high dielectric constant insulating layer between levels.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-27 IC Device and Packaging Technology Trends

Leading manufacturers are now adopting copper wiring; late in 1997 both IBM and Motorola announced use of this technology. ICE expects similar announcements from other semiconductor manufacturers in 1998.

Compared to aluminum, copper saves about two metal layers for a given device generation (Figure 4-37). When copper is combined with a low dielectric constant insulating material, addi- tional wiring levels can be saved. A report from Intel details that converting to copper and low- dielectric material can save four metal levels and postpone reaching an impractical number of wiring levels by two IC generations.

Al, Dielectric Constant = 4 Cu, Dielectric Constant = 4 Al, Dielectric Constant = 2 14 Cu, Dielectric Constant = 2

12 RC = 1.0x s

r Per Generation e

y 10 a

L P = 0.07x

EFF l

a Per Generation t 8 e M

f

o 6

r e b

m 4 u N 2

0 0.35 0.25 0.18 0.13 0.09 Technology Generation (µm) Source: Intel 23258

Figure 4-37. Copper Versus Aluminum Wiring on ICs

IC Integration Density Trends

By shrinking IC feature sizes and adding more layers of metal, IC manufacturers have been able to continually and dramatically increase integration levels (Figure 4-38). MOS memory IC inte- gration levels have increased an average of 50 percent per year for the past 26 years. The 1998 DRAM density level is expected to contain over 256 million transistors. Devices with 1 billion transistors per chip are forecast to appear on the market by 2000.

The transistor count of new microprocessors also continues to increase; here the rate is approxi- mately 35 percent each year. Intel’s Pentium with 3.1 million transistors and Pentium Pro with 5.5 million transistors fell slightly short of the microprocessor-and-logic trend line in 1993 and 1995. However, this should not be taken as an indication that the growth in microprocessor integration levels is slowing. Other microprocessors, such as Digital’s Alpha 21164 with 9.7 million transis- tors and AMD’s K6 with 8.8 million transistors, fall on the escalating IC density trend.

4-28 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Device and Packaging Technology Trends

1G 1G

Pentium Pro LSI Logic 256M MPU and Cache Gate Array Memory Chip 100M 64M

16M P7

10M Pentium Pentium Pro MPU Only 4M IBM 80486 Gate 1M 1M Array LSI Logic 256K 80386 Gate Array 68020 80286 100K 64K

Number of Transistors per Chip 68000

16K 8086

10K 4K 8085 8080 1K = Microprocessor and Logic 4004 = Memory (DRAM) 1K 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 00 02 Year Memory increase = 1.5/year MPU increase = 1.35/year Source: ICE 11745R

Figure 4-38. IC Density Trends

Integration levels in ASICs are also growing rapidly. For example, LSI Logic claims its most recent G11-generation ASIC technology allows for the integration of up to 64 million transistors on a single chip. In comparison, the company’s leading-edge technology in 1988 could pack one mil- lion transistors on a chip. Another leader in ASIC technology, Texas Instruments, claims to have ushered in the 100-million-transistor ASIC era with the introduction of its Timeline technology that is capable of ICs with up to 125 million transistors.

Die Size Trends

With the escalation of transistors per die, average die sizes have also increased. Figure 4-39 shows that the die area of leading-edge ICs, both memory and logic types, has increased about 13 per- cent per year. The trend toward larger die sizes, at least for memory, is forecast to continue at this rate into the early part of the next decade.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-29 IC Device and Packaging Technology Trends

2,000

LSI Logic Pentium Pro P7 1,000 Gate Array MPU and Cache 800 1G IBM Pentium 600 Gate Array Pentium Pro 400 MPU R4000 256M Only 80486 64M

200 16M 80386 68020 80286 4M 100 68000 1M 80

60 256K 8086 Z80 40 16K 64K Chip Area (Thousands of sq mils) 8080 4K 20 = Microprocessor/Logic = Memory 10 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 00 02 Year Memory increase = 1.13/year MPU increase = 1.13/year Source: Intel 11746R

Figure 4-39. IC Die Size Trends

Figure 4-40 provides a look at die sizes of leading-edge DRAMs, which are typically reported at the annual International Solid-State Circuits Conference (ISSCC). The die sizes of 1G DRAMs described at the 1995 and 1996 ISSCC ranged from 901,000 mils2 to 1,451,000 mils2. The NEC 4G DRAM, reported at ISSCC in 1997, is 1,527,000 mils2; interestingly, this is only slightly larger than NEC’s 1G chip. NEC accomplished this using a technology that allows four levels of data to be stored in each cell, as compared to two levels in conventional cells. Figure 4-41 is an example of one of the first working prototypes of the 4G DRAM from NEC. Other DRAM companies are evaluating and developing technologies like multilevel cell techniques to make future-generation DRAMs more economical to produce.

Similarly, by aggressively reducing chip linewidths and using additional metal layers, micro- processor manufacturers have been able to slow the rate of die size increase. In fact, Intel’s next- generation Merced P7 processor is expected to be roughly the same size as the first Pentium Pro.

4-30 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Device and Packaging Technology Trends

Feature Cell Chip Size Access Company Density Organization Conference Size (µm) Size (µm2) (K sq. mils) Time (ns)

Hyundai 256M 0.3 — 561 36 32M x 8 ISSCC '95 Matsushita 256M 0.25 0.72 638 — 16M x 16 ISSCC '94 Mitsubishi1 256M 0.25 0.72 472 34 32M x 8 ISSCC '94 Oki2 256M 0.25 0.72 530 — 32M x 8 ISSCC '94

Mitsubishi3 1G 0.14 0.29 901 32 — ISSCC '96 Samsung4 1G 0.16 — 1,010 — — ISSCC '96 Hitachi 1G 0.16 0.29 1,108 33 64M x 16 ISSCC '95 NEC 1G 0.25 0.54 1,451 — — ISSCC '95

NEC5 4G 0.15 0.23 1,527 — — ISSCC '97 1 Produced using KrF excimer-laser lithography. 2 Packaged in a 64-pin 600-mil TSOP, produced using e-beam lithography. 3 SDRAM produced using synchrotron-generated x-ray lithography. 4 SDRAM produced using KrF excimer-laser lithography. 5 Each cell can store four levels of data, compared to two levels in conventional cells. Source: ICE 20289B

Figure 4-40. ISSCC Advanced DRAMs

Source: NEC 22410

Figure 4-41. A 4-Gbit DRAM

Wafer Size Trends

The forces behind the semiconductor industry’s periodic change to larger silicon wafers is driven by the savings from producing more dice per individual wafer while using the same, or only fraction- ally increased, number of process steps and volume of process materials. As 1998 begins, the world- wide semiconductor industry is on the pilot-line threshold of a transition to 300mm silicon wafers.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-31 IC Device and Packaging Technology Trends

Based on historical trends, peak demand for 200mm wafers, the current leading edge for produc- tion, will be reached around 2003, as shown in Figure 4-42. This wafer-size life-cycle perspective can be used as a guide as the semiconductor industry continues to move to larger wafers.

100,000

rend Model Area T afer 10,000 Total W 1976-2025: 10% CAGR ) 2 1,000 in. 6

100% Pilot Line ear (10 100 33%

10% 450mm 10 200mm Ironman

Area Demand/Y 300mm 125/150mm 1 75/100mm 38/51mm 1998 0 '60 '65 '70 '75 '80 '85 '90 '95 '00 '05 '10 '15 '20 '25 Year Source: VLSI Research, SEMATECH, I300I 22624A

Figure 4-42. Lifecycle of Silicon Wafer Sizes

While silicon-based semiconductor manufacturers are developing the technologies needed for 300mm wafer processing, many GaAs semiconductor manufacturers are undergoing or consider- ing a transition to 150mm wafer processing from 100mm. Some of the leading manufacturers even began using 150mm wafers in 1997. GaAs wafer supplier Simitomo Electric plans for its output of raw 150mm GaAs wafers to reach 3,000 units per month by the end of 1998. Like with silicon- based semiconductor manufacturing, every incremental increase in GaAs wafer size brings with it gains in manufacturing productivity and reductions in IC manufacturing cost.

Wafer size increases are commonly evaluated in terms of increase in wafer area, as shown in Figure 4-43. Interestingly, the move from 100mm wafers to 150mm wafers increased the silicon area by 125 percent—the same relative gain that will be realized when semiconductor companies make the transition from today’s 200mm wafers to 300mm wafers. Beyond 300mm, the same gain requires a jump to 450mm wafers.

4-32 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Device and Packaging Technology Trends

100mm → 125mm 56

→ 100mm 150mm 125

→ 156 125mm 200mm

→ 78

150mm 200mm

200mm → 250mm 56

250mm → 300mm 44

200mm → 300mm 125

Wafer Diameter Transition

→ 300mm 400mm 78

→ 300mm 450mm 125

0 50 100 150 200 Percent Increase

Source: ICE 18603A

Figure 4-43. Wafer Area Increases (Percent)

Early on, semiconductor manufacturers had said they wanted to be in full production of 300mm wafers in 1998. However, issues such as limited funding, the need for longer development time, and the extended life span of 200mm wafers have pushed full-scale production out several years. One of the latest polls shows that several companies, generically identified, expect pilot or low- volume fabrication on 300mm wafers to start in 1998, with high-volume facilities expected to enter production around 2000 (Figure 4-44). Hitachi, IBM, Intel, NEC, Samsung, and Texas Instruments will be among the first to operate 300mm fabs for volume IC production.

Fab Size (Wafers per Month) 1998 1999 2000 2001 2002

High Volume (20,000) — — 5 4 2

Medium Volume (10,000) — 1 4 — 1

Low Volume (2,000) 2 5 — — —

Pilot Line (500-1,000) 9 5 — — —

Source: SEMI 22665

Figure 4-44. Planned 300mm Wafer Fabs

Semiconductor manufacturers have unquestionably stated that 300mm technology development will not be performed solely by the themselves, as it was in previous generations with Intel enabling the transition to 150mm wafers and IBM managing the transition to 200mm wafers. In the case of 300mm wafers, the technical challenges are so involved that they require an unprece- dented level of industry-wide cooperation.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-33 IC Device and Packaging Technology Trends

It is estimated that the industry’s overall cost of making the transition to 300mm wafers will be in the area of $15 billion to $20 billion. This includes development of the wafer processing equipment and techniques, development costs of wafer handling tools, computer integrated manufacturing software, factory automation systems, and cleanroom technology. Texas Instruments estimates that while

Cost Per Square cm 25 - 30% Less 300mm tool costs will increase by Usable Portion of Wafer 3 - 14% More 20-40 percent over 200mm wafers, Cost Per Chip 27 - 39% Less an overall 27-39 percent reduction Labor About Equal in the cost per chip can be realized Tool Capital Cost 20 - 40% More (Figure 4-45). In addition, Texas About Equal Materials Use Instruments estimates that labor Emissions About Equal cost, materials use, and factory Process/Probe Yield Slightly Better

Source: Texas Instruments 22623 emissions should be comparable between the two wafer sizes and Figure 4-45. 300mm Versus 200mm at Maturity that higher yields may be possible.

As of late 1997, the price of a prime 300mm wafer ranged from $1,000 to $1,500, depending on volume. In the early years of the next decade, when 300mm wafer use is expected to be in higher volume, wafer costs are forecast to be in the range of $450 to $600.

Demand for 300 mm wafers is likely to surpass 1.2 million units in 2000, up from about 45,000 wafers in 1998. One-third of the 300mm wafers in 2000 will be silicon epitaxy wafer starts. Understandably, initially over half the 300mm wafers will be test wafers. But part of the success of 300mm production will involve the development of in-situ and on-product-wafer metrology capabilities that preclude the need for test wafers.

Samsung estimates that a 20,000-wafer-per-month 300mm manufacturing facility will cost approx- imately $2.4 billion, and will require a 130,000-square-foot cleanroom. A 30,000-wafer-per-month facility will cost approximately $3.6 billion and require 200,000 square feet of cleanroom space.

Two major industry consortia were formed in 1996 with the goal of lowering the barriers to devel- opment of 300mm technologies. One effort is the International 300mm Initiative, or I300I, formed by United States based Sematech in January, 1996. Participation in I300I is open to U.S. IC manu- facturers and foreign companies with wafer fabs located in the U.S. (Figure 4-46). I300I anticipates having 70-80 wafer processing systems tested and qualified by the end of 1998. Initially funded at $26 million ($2 million from each of its 13 members), I300I’s program goals include:

• providing inputs to international standards activities, • developing consensus on performance metrics and demonstration methods, • demonstrating 300mm equipment and materials for 0.25µm processing, and • defining a program by mid-1998 for demonstrating and qualifying 0.18µm equipment, which will be performed through 2000.

4-34 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Device and Packaging Technology Trends

U.S. Companies Advanced Micro Devices IBM Intel Lucent Technologies Motorola Texas Instruments European Companies Philips SGS-Thomson Siemens Korean Companies Hyundai LG Semicon Samsung Other Companies TSMC (Taiwan) Source: ICE 21753

Figure 4-46. I300I Member Companies

The Japanese formed their own consortium in February, 1996. Called the Semiconductor Leading Edge Technologies venture, or SELETE, it is represented by Japan’s ten largest semiconductor companies (Figure 4-47). SELETE plans to spend roughly $350 million before the turn of the cen- tury. Like I300I, SELETE will first focus on 0.25µm, 300mm wafer manufacturing and subse- quently on 0.18µm fabrication and more stringent requirements. SELETE operates a cleanroom within an existing Hitachi wafer fabrication facility in Yokohama, Japan.

¥ Fujitsu ¥ Oki ¥ Hitachi ¥ Sanyo ¥ Matsushita ¥ Sharp ¥ Mitsubishi ¥ Sony ¥ NEC ¥ Toshiba

Source: ICE 21754

Figure 4-47. SELETE Member Companies

Continuing success in transitioning to 300mm wafers will depend on the level of interaction between organizations like I300I and SELETE for the purpose of developing global industry stan- dards. Developmental wafer specifications have been drafted and specifications for circuit qual- ity wafers are nearing completion. Device manufacturers have yet to agree as to how standards for wafer carriers and tool interfaces should be defined. There are eight possible combinations of lot sizes with 13 or 25 wafers, integral versus removable cassettes, and front-opening or side-open- ing boxes that are being proposed.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-35 IC Device and Packaging Technology Trends

Once standards are in place and equipment is readied, there are additional issues that must be remedied if 300mm wafer processing is to become a reality. A few of the many wafer processing questions or concerns that must be addressed include:

• Ensuring uniformity of deposition and etch. • Ensuring the integrity of wafer flatness across the 300mm diameter. • Developing the necessary ion implantation processes (single wafer or batch) • Reducing or eliminating test wafer use. • Establishing lower furnace process temperatures (300mm wafers will require approximately 900°C maximum versus 1200°C for 200mm wafers). • Optimizing chemical quantities for processing.

Figure 4-48 compares the development time for each new wafer generation. As shown, the time required has increased significantly over prior generations. While it took five years for 200mm wafers to reach an annual production rate of 100 million square-inches per year, it has been esti- mated that eight years will be needed for 300mm wafers.

100mm 3 years

125mm 3 years

150mm 3 years

200mm 5 years

300mm 8 years (EST)

Source: Rose Associates 21192A

Figure 4-48. Wafer Development Time Requirements (Time to Reach 100 Million Square Inch Production Rate)

Longer term, the Japanese industry is already looking at 400mm silicon wafers. Its Super Silicon Crystal Research Institute, formed by seven major silicon wafer makers and the Japan Key Technology Center, is now studying silicon crystal pulling methods, wafer slicing techniques and developing metrics for evaluating the properties of these giant wafers; this project is funded through 2001. So far, this organization believes that the doping properties and quality of 400mm plus wafers can only be controlled with subsequent deposition of epitaxial layers, particularly if they are introduced for DRAM manufacturing.

4-36 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Device and Packaging Technology Trends

The Future of IC Technology

In general, there are several scenarios about advanced IC manufacturing at the turn of the century. The first is that post-2000 ICs will happen as planned and will be manufactured economically as well. The reasoning behind this view lies in historical precedent: Since the 1990s-type ICs appeared impossible in the early 1980s, and yet were created with the assistance of significant advances in manufacturing technology, the impossible appearing post-2000 ICs will follow this same path to fruition. The second scenario reasons that it is not realistic to keep extrapolating his- torical trends in IC technology to infinity. At some point, physical or economic limits will prevail.

While it is easy to find refuge in the second scenario, the message of historical trends and incred- ible advances associated with semiconductor manufacturing cannot be ignored. Indeed, ICE believes that the latest thinking of the industry experts, reflected in the pending new SIA roadmap, indicate a third scenario that defines the likely trend for the turn of the century: The industry is diverting from historical trends, advancing beyond the traditional forecast of Moore’s Law not slowing. Here, the more likely unknown factors involve the economic feasibility of many of the new technologies.

IC PACKAGING TECHNOLOGY OVERVIEW

IC packaging is receiving much more attention now than in the past. Today, systems manufac- turers, as well as IC manufacturers, realize an increasing percentage of system performance, or performance limits, is determined by the IC-and-package combination, rather than just the IC. In addition, packaging is increasingly more costly. ICE forecasts that IC packaging costs will con- tinue to rise significantly into the turn of the century since more of the newer ICs now require high-lead-count, expensive packages.

Analyzing markets of various major packages types (Figures 4-49), the surface-mountable small outline package (SOP) had the greatest market share in 1997; surface mount technology continues to dominate printed circuit boards (PCBs). In was just in 1994 that surface mount packaged ICs first out shipped conventional through-hole packaged ICs. It is expected that by 2002, surface mount packages will have about seven times the unit market share of through-hole packages (Figure 4-50).

The primary advantage of surface mount packaging is improved performance and savings in space at the PCB and system levels. Not only are surface mount packages smaller, they can also be placed on both sides of a PCB. This savings in space can reduce PCB costs by as much as 60 percent, while improving performance at the same time

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-37 IC Device and Packaging Technology Trends

1996 1997 (EST) 1997/1996 2002 (FCST) 1996-2002 Package Percent CAGR Type Units Percent Units Percent Units Percent (M) Of Total (M) Of Total Change (M) Of Total (%) Plastic DIP 13,400 27 14,500 25 8 9,100 10 Ð6 CERDIP 445 1 415 1 Ð7 170 <1 Ð15 Sidebraze DIP 40 <1 35 <1 Ð13 15 <1 Ð15 Ceramic PGA 115 <1 125 <1 9 145 <1 4 Plastic PGA 100 <1 130 <1 30 260 <1 17 BGA/CSP 90 <1 160 <1 78 2,600 3 75 SOP* 23,120 47 28,760 50 24 51,300 58 14 PLCC 2,270 5 2,390 4 5 2,630 3 2 PQFP 6,390 13 7,600 13 19 15,300 17 16 Other** 2,830 6 3,160 6 12 6,700 8 15 Total 48,800 100 57,275 100 17 88,220 100 10 *Includes UTSOPs, QSOPs, TSOPs, and SOJs. **Includes TAB-on-board, COB, flatpacks, metal cans, LLCC, LDCC, etc. Source: ICE 14737R

Figure 4-49. Worldwide Merchant IC Package Marketshare (Units)

Plastic DIP Through Hole 10% Other Other 12% 2% 2%

Plastic Through DIP Surface Hole Mount 25% SOP Other SOP 27% 1997 (EST) 73% 2002 (FCST) 57.3B 50% 30% 88.2B 58% Other 23%

Surface Mount 88%

Source: ICE 16827N

Figure 4-50. IC Package Market Share (Units)

The current driving force on SOPs, especially for memory and logic IC packaging, is to reduce the thickness or profile of the package, particularly for memory applications (Figure 4-51). This will enable portable applications where size and weight are important constraints. For logic IC appli- cations in portable electronic equipment, semiconductor manufacturer TI unveiled a new chip package that uses about 40 to 60 percent less board space than a shrink small outline package (SSOP). TI’s thin very small outline package (TVSOP) features a lead pitch of 0.4mm, compared to SSOP’s 0.5mm pitch, and a mounted height of 1.2mm, which is only 50 percent greater than the thickness of a standard credit card.

4-38 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Device and Packaging Technology Trends

PQFP TQFP UTQFP TSOP UTSOP

mm 3.6 2.0 1.4 1.0 0.5-0.8

Source: Portable Design 22404

Figure 4-51. Package Profile Evolution

Of the various package types, SOPs, ball grid arrays (BGAs) and chip scale packages (CSPs), plas- tic pin grid arrays (PPGAs) and quad flat packs (QFPs) are anticipated to show the strongest growth through 2002. The dominant package types—SOPS, plastic dual inline packages (PDIPs), and plastic quad flat packs (PQFPs)—are forecast to make up about 86 percent of the IC-package unit market in 2002.

The trend shown with estimated 1997 and forecasted 2002 IC markets by product type clearly shows that surface mount technology is gaining almost complete dominance (Figure 4-52). For example, in 1997 MOS memory had a very high 94 percent penetration rate for surface mount. Even where surface mount unit volumes now only represent healthy 67 and 72 percent for analog and MOS logic, both these IC types show a significant increase to surface mount packages by 2002, to 82 and 92 percent respectively.

Percent Surface Market ($B) ASP ($) Unit Volume (B) Surface Mount Mount Units (B) Product 1997 2002 1997 2002 1997 2002 1997 2002 1997 2002 (EST) (FCST) (EST) (FCST) (EST) (FCST) (EST) (FCST) (EST) (FCST)

Digital Bipolar 1.6 0.8 0.48 0.40 3.3 2.0 60 75 2.0 1.5

Analog 19.7 48.0 0.74 1.08 26.7 44.4 67 82 17.9 36.4

Microcomponent 50.6 134.9 8.03 12.73 6.3 10.6 87 98 5.5 10.4

MOS Logic 24.3 61.9 1.76 3.21 13.8 19.3 72 92 9.9 17.8

Memory 31.0 103.9 4.31 8.73 7.2 11.9 94 99 6.8 11.8

Total 127.2 349.5 2.22 3.96 57.3 88.2 73 88 42.1 77.8

CAGR 1997-2002 22% 12% 9% — 13%

Source: ICE 20313E

Figure 4-52. 2002 Surface Mount Package IC Unit Forecast

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-39 IC Device and Packaging Technology Trends

The analog IC segment of the market will contribute over half of the annual increase in total IC and surface mount unit volume shipments through 2002 (Figure 4-53). Since most analog components are low-density devices, the surface mount trend in this segment is primarily directed at SOPs. Overall, analog and memory products will represent the majority of SOP applications in 2002.

Contribution 1997/2002 Contribution 1997/2002 To Total Surface Mount To Total Product Unit Volume Increase Unit Volume Increase Change (B) (Percent) Change (B) (Percent)

Analog 17.7 57 18.5 52

MOS Logic 5.5 18 7.8 22

Microcomponent 4.3 14 4.9 14

Memory 4.7 15 5.0 14

Bipolar Digital Ð1.3 Ð4 Ð0.5 Ð1

1997/2002 30.9 — 35.8 — Net Increase

Source: ICE 20314D

Figure 4-53. Analog and MOS Logic Products Drive Surface Mount Volume

As for package materials, plastic packages will dominate more than 90 percent of packages shipped (Figure 4-54). Ceramic packages have been losing market share to plastic packages for several reasons, including the industry’s move to plastic-packaged flash memories and away from ceramic-packaged electrically programmable read only memories (EPROMs), the U.S. mil- itary’s implementation of plastic IC packages in many of the less-harsh system environments, and Intel’s 1996 decision to change the packaging of its advanced microprocessors from ceramic to plastic. The conductivity and dielectric qualities of laminate packages, which are multilayer plastic packages made of copper and epoxy resin, make them attractive for high-speed chips like Intel’s microprocessors.

Plastic Plastic 93% 92%

1997 (EST) 2002 (FCST) 57.3B 88.2B Ceramic 1%

Other* Ceramic Other* 5% 2% 7% *Includes TAB-on-board, COB, flatpacks, metal cans, bare dice for MCMs, etc. Source: ICE 12061U

Figure 4-54. Worldwide Merchant IC Package Marketshare by Material (Units)

4-40 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Device and Packaging Technology Trends

The increasing density and complexity of ICs are also pushing the state-of-the-art in pin count, especially for various gate arrays and microprocessors (Figure 4-55). Although high-pin count packages currently represent a small percentage of the units shipped (Figure 4-56), the number of packages with pin counts over 68 is steadily increasing. Some packages with pin counts as high as 1,500 may be in production by the end of the decade (Figure 4-57).

104

Bipolar Gate Array CMOS Gate Array Microprocessor SRAM DRAM 103

2

Number of Signal Pins 10

101 102 103 104 105 106 Number of Gates or Bits

Source: University of Arizona 13651A

Figure 4-55. I/O Pin Count Versus Complexity

>208 pins >208 pins 69-208 pins <1% 2% 9% 69-208 pins 13%

1997 (EST) 2002 (FCST) ≤68 pins ≤68 pins 57.3B 88.2B 91% 85%

Source: ICE 21777B

Figure 4-56. IC Package Unit Shipments by Pin Count

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-41 IC Device and Packaging Technology Trends

1,800

1,600

1,400

1,200

1,000

800

600

400

200 Number of I/Os Per Component 0 1994 1995 1996 1997 1998 1999 2000 2001 Year Source: Mentor Graphics/EE Times 21196

Figure 4-57. Pin Count Forecast

As pin counts have increased, the industry has gravitated toward fine-pitch lead technology (FPT). The Institute for Interconnection and Packaging Electronic Circuits (IPC) defines FPT as those devices that have lead pitches ranging from 0.5mm to 0.1mm (20mils to 4mils). Below 0.1mm, the term ultrafine pitch has been suggested. With FPT, package leads are highly sus- ceptibility to damage. Fine-pitch leads cannot be touched before being placed on a board or substrate. In most cases an FPT IC must be placed and held in position until soldering of the leads is completed.

Lead coplanarity and integrity are also critical issues with today’s advanced packages. Special carriers are frequently used to hold a package’s outer leads until immediately before PCB attach- ment. These carriers also provide easily accessible test contacts so that chips can be fully tested before PCB assembly. The delicate nature of fine or ultrafine-pitch packages has many designers considering BGA package options.

Most IC assembly and packaging operations for semiconductor manufacturing are still located in Asia-Pacific (Figure 4-58). This is due primarily to low labor cost. However, the importance of labor cost is decreasing, largely because packaging equipment advances are making packaging operations more automated. This, coupled with the need for shorter lead times, will be a factor in making onshore packaging more attractive. Nevertheless, the existing experienced and sophisti- cated packaging infrastructure as well as economic benefits and tax breaks help to keep Asia- Pacific an attractive region for semiconductor assembly, the so-called back-end operations of semiconductor manufacturing, especially for high-volume IC packaging operations.

4-42 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Device and Packaging Technology Trends

ROW 2% North Europe America 8% 5%

57.3B Asia Pacific Japan 25% Units 60%

Source: Emissarius, Ltd. 20312E

Figure 4-58. Estimated 1997 Final IC Packaging by Location

Ball Grid Arrays

One of the most talked about surface mount packages is the ball grid array (BGA), shown in an exploded view in Figure 4-59. A BGA package, rather than using pins for leads, mounts to a PCB using solder balls located on the underside of the package. The BGA was first introduced by IBM as a ceramic package for its own internal use. It wasn’t until Motorola’s 1989 introduction of a plastic version of the BGA, labeled OMPAC, that the technology began to take hold commer- cially. Motorola worked with Compaq Computer on the first implementation of the package into new products.

Cover

Interconnection Matrix ¥ Wirebond Bare Chip ¥ TAB ¥ Flip-Chip Solder-Bump Mounting Pads BGA Substrate Mounting Pads

Printed Circuit Board Source: Electronic Design 22767A

Figure 4-59. General BGA Construction

Proponents of the BGA say it provides benefits such as small size, good yields, excellent electrical performance, and low profiles—features that have been demanded by system designers. By spreading the contacts over the bottom of the packaged device, the size of the package is reduced compared to QFPs. No longer are there many small, fragile leads jutting out from all sides of the package. The rising number of leads per package and lead pitch limitations are the driving forces behind the increasing popularity of BGAs (Figure 4-60).

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-43 IC Device and Packaging Technology Trends

1.8

1.6 Ball-Grid Array (BGA)

1.4

1.2 Quad Flat Pack (QFP) Technological jump from QFP to BGA 1.0 Technological limit for QFP Limit of what can Pitch (mm) 0.8 fine pitch be done "simply"

0.6 Limit range of what can be 0.4 reasonably accomplished in light of cost considerations 0.2

0 100 200 300 400 500 600 700 800 900 I/Os Source: IBL-Löttechnik 20315

Figure 4-60. Fine Pitch, High I/Os Push Packaging to Ball-Grid Arrays

One of the early concerns with using a BGA was how to effectively inspect the final soldered ball joints that attached these packages to a PCB. With many of the solder joints hidden beneath the package, visual inspection is impossible, making it necessary to use x-ray machines. Recently, companies have found that every solder ball joint does not need to be checked if the process is controlled. The key to good BGA assembly processing is said to be in the solder paste.

Another concern has been the high costs associated with BGAs. Even with increased volumes, BGAs will more than likely command a greater price than QFPs since BGAs have an internal cir- cuit board that holds the chip and fans out the leads. BGAs also add to PCB complexity; although their PCB footprint is relatively small, PCBs accepting BGAs may require more layers. This can serve to increase the cost of the subsystem. Moreover, repairability is also difficult with current BGA packages.

As further experience is gained, BGA packaging is expected to be widely used, especially for logic and memory ICs in high-performance applications, including pagers and cellular phones.

The following are some of 1997’s significant BGA-related business and technology announcements:

• Fujitsu and Toshiba jointly agreed on common specifications for a 48-pad BGA package housing multiple memory chips. The BGA configuration is aimed at encasing flash memory and SRAM ICs in a single multichip package that occupies up to 70 percent less space than conventional methods using two TSOPs. The package targets manufacturers of cellular phones and other mobile products.

4-44 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Device and Packaging Technology Trends

• A new type of area array package was developed by Belgium’s IMEC, in collaboration with Siemens Laboratories, that is said to offer higher density and better thermal handling capa- bilities than conventional PGA and BGA packages. The polymer stud grid array (PSGA) con- sists of a polymer injection molded body with a cavity for chip mounting and metallized polymer studs.

• ProLinx Labs, San Jose, California, announced an agreement with Taiwanese PCB manu- facturer, Unicap Electronics Industrial to build a $42 million facility focused on the produc- tion of BGAs based on ProLinx technologies. To be located in Taiwan, the new plant will implement the Micro-filled Via (MfVia) process used to produce ProLinx’s ViperBGA (VBGA) substrate.

• In late January, 1997, Amkor Electronics announced it would build a 280,000-square-foot BGA assembly facility in Chandler, Arizona. The first phase of the plant was expected to be completed by mid-1997.

• S-MOS Systems added a BGA version to its SED 1560 series of 3V, single-chip LCD drivers and controllers.

Chip-Scale Packages

Chip-scale packaging is one of the hottest topics in the packaging industry (Figure 4-61). In fact, the chip-scale package (CSP) has been called “the choice of the future,” having achieved very widespread acceptance in a very short time. The CSP is only slightly larger than the die itself, typ- ically less than 20 percent larger. CSPs with peripheral leads are suited for low lead-count pack- ages with 50-100 pins, while CSP area arrays are particularly well suited for high lead-count packages, eventually exceeding 1000 pins.

Protective Coating Semiconductor Chip

Compliant Layer

Interconnect

Flex Circuit Bump Array Ð Gold Plated

Printed Circuit Board

The bump array, which is mounted on a compliant layer to reduce the mechanical stress of the solder joint and accommodate surface irregularities on the printed circuit board, uses gold plated bumps for reliability. Source: Tessera 19505A

Figure 4-61. Diagram of a Tessera µBGA Package

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-45 IC Device and Packaging Technology Trends

Chip-scale packaging has been labeled by some to be the solution that offers size and performance benefits of packageless technologies such as flip chip, chip-on-board, and bare die, but at a lower cost and without requiring custom packaging. CSPs combine the best features of bare die assem- bly with the numerous advantages of fully packaged ICs (Figure 4-62). Furthermore, CSPs are showing some promise to driving IC packaging costs below the much sought after benchmark price of one cent per pin or lead.

Bare Chip Chip Scale Packaging Traditional IC Packaging Technologies* Technology Technology

Die Size Die Size Standard Foot Prints Standard Foot Prints Short Electrical Path Short Electrical Path Low Cost Low Cost High I/O Capability High I/O Capability Assembly Infrastructure Assembly Infrastructure Thermal Management Thermal Management** Alpha Particle Protection Alpha Particle Protection Ease of Test Ease of Test Protection for Die Protection for Die Immunity to Die Shrink** Immunity to Die Shrink Reworkable Reworkable

* Flip-chip is generally considered to be superior to chip-and-wire technology in all listed categories and is therefore the primary reference for the chart above. ** Attributes will vary from CSP type to CSP type. Source: Semiconductor International 21775

Figure 4-62. CSP Offers Best of Both

One disadvantage of CSPs is that some of the fine-pitch manufacturing problems solved in tran- sitioning from QFPs to BGAs are being reintroduced. In addition, the greater density of CSPs, when compared to BGAs, requires more complex sockets for test and burn-in. The resolution of problems such as these will determine how far CSPs take the industry.

Currently, there are in excess of 35 companies offering CSPs using a variety of technologies. Figure 4-63 describes the packages from several of the suppliers. Some of the CSPs that have entered volume production include Tessera’s microBGA (µBGA), the MSMT package offered by ChipScale and produced by Motorola, the CSBGA package from Amkor, TI’s MicroStar BGA, Fujitsu’s small-outline no-lead (SON) package, and an array CSPs from Sharp.

The most visible vendor for CSP is Tessera; for example, Tessera’s µBGA gained a significant amount of momentum in 1996 when Intel and Texas Instruments licensed the technology for use in packaging flash memory ICs. The company’s business plan is to license its technology to assembly, package, and IC suppliers, while providing the technical support and guidance to bring up its customers’ production lines. Semiconductor manufacturers Amkor, Shinko, Intel, AMD, TI, and Hitachi are among the licensees who are ramping up production volume.

4-46 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Device and Packaging Technology Trends

Individual Chip Wafer Level Primary Package Lead Package Supplier Processing Processing Construction Arrangement Capable? Capable?

Amkor Flexible interposer with Area array Yes No compliant encapsulant

ChipScale Silicon sandwich with Peripheral No Yes chevron beam leads leads

Fujitsu Lead on chip wire bonded Peripheral Yes No and molded leads

Matsushita Flip-chip with underfill on Area array Yes No ceramic carrier

Mitsubishi Redistribution wiring on Area array Yes No chip with transfer bumps

Motorola Flip-chip with underfill on Area array Yes No organic carrier

NEC Flex circuit interposer Area array Yes No with bumped leads

Nitto Denko Flex circuit interposer Area array Yes No with bumped leads

Sandia Rigid polyimide film with Area array No Yes redistribution wiring

Sharp Wire bonding onto flex Area array Yes No carrier

ShellCase Silicon and glass with Peripheral No Yes edge wrapped leads leads

Tessera Flexible interposer with Area array Yes Yes complaint encapsulant

TI Wire bonding onto flex Area array No No carrier Source: Semiconductor International 21776

Figure 4-63. Examples of CSP Technologies

Why Intel chose to use the µBGA package is clear in Figure 4-64. The company’s 0.4µm, 8M flash memory packaged in a 5x8 ball matrix µBGA is 80 percent smaller and 17 percent thinner than its 40-lead TSOP counterpart. It is interesting to note, however, that Intel believes the majority or about two-thirds of its flash products will continue to be manufactured in TSOPs for the foresee- able future.

TI has said it is considering using the µBGA to package some of its other ICs. In addition, while Tessera will initially produce the packages for the company, TI plans to eventually produce the packages itself.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-47 IC Device and Packaging Technology Trends

40-Pin TSOP 40-Bump µBGA 1.00x 0.20x Source: Tessera 22766

Figure 4-64. Switching from TSOP to CSP Shrinks Intel’s Flash 80 Percent

Multichip Modules

Virtually every large computer manufacturer, telecommunications manufacturer, high-volume consumer electronics manufacturer, and aerospace systems manufacturer are working on or con- sidering designs that include multichip modules (MCMs). There has been a dramatic increase in activity over the last five years, with entire conferences being dedicated to MCMs. MCMs have gone through three phases in their growth:

Phase one was the widespread use in mainframe and super computers. The primary driving force was performance. These systems were predominantly ECL-IC based, with relatively low integra- tion levels. The MCM implementation allowed the re-integration of large scale integration (LSI) chips into very large scale integration (VLSI) modules, while keeping wiring delays small.

Phase two was the exploration of MCM technologies and the building of an infant infrastructure by the visionaries and champions of a merchant MCM industry. Many of these early pioneers had their start in large system companies. This was a period of high expectations being set. MCMs were viewed as taking over all of packaging. The single-chip package was declared dead. End users of everything from computers to consumer products, such as Sun, Silicon Graphics, Apple Computers, LSI Logic, and Kodak, had designed and built a number of prototype MCMs to eval- uate the vendor base, technology options, and cost-performance benefits to MCMs. A few of these designs actually went into limited production. Figure 4-65 is an example of a four-chip graphics controller module LSI Logic designed for Silicon Graphics, currently in production.

4-48 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Device and Packaging Technology Trends

Courtesy of LSI Logic 22343

Figure 4-65. LSI Logic MCM-C

The third phase rose out of the visionary second phase. This included the establishment of a strong merchant infrastructure and the introduction of MCM designs that are in volume produc- tion, spanning the range from high-end computers to low-end consumer products. It is princi- pally the portable and wireless consumer products that have fueled this third wave of application and integration of MCMs.

Through the pioneering efforts of the early visionary individuals and companies, and stimulated by strong competition from off-shore suppliers, multichip modules are today moving into volume production in the merchant market. As shown in Figure 4-66, the MCM market is forecast to grow from about $1.3 billion in 1998 to near $2.9 billion in 2002, an average annual growth rate of 25 percent (the figures exclude the value of ICs in MCMs).

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-49 IC Device and Packaging Technology Trends

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0 yyyyyy yyyyyy yyyyyyy yyyyyy yyyyyy yyyyyy yyyyyyy yyyyyy yyyyyy yyyyyy yyyyyyy yyyyyy 1991 1992 1993 1994 1995 1996* 1997 1998 1999 2000 2001 2002 Year *About 75% of market was captive Source: ICE 18636E

Figure 4-66. MCM Market Forecast

The generally accepted definition of an MCM is a collection of more than one bare die or micropackage on a common substrate. Based on this definition, the evolving four families of MCMs include:

• Hybrids: traditional thick-film substrates with typically small die and a low density of interconnects, using a custom hermetic can package. An example of a hybrid is shown in Figure 4-67.

• Chip-on-Board (COB): bare dice on organic laminate substrates, such as FR-4, along with other surface mount ICs, both packaged devices and discrete components. The package is typically a small daughter card, such as PC cards, smart cards, or small motherboard. Figure 4-68 is an example of a video subsystem for a laptop computer; the large chip in the center is an ASIC controller surrounded by various peripheral interface chips.

• Few-Chip Packages or Multi-Chip Packages (MCPs): a small module with an external form factor that matches a single-chip package, and typically contains two to five bare dice. The package can be a PQFP, PGA, or BGA. An example of an MCP is shown in Figure 4-69.

• High-End MCMs: includes large, high-density substrates with as many chips as used in mainframe computers and large military hybrids that have multiple high-density dice and a custom package. An example is shown in Figure 4-70.

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Source: Boeing Microelectronics 22563

Figure 4-67. Rocket Control and Monitoring Hybrid

Source: Electronic Packaging & Production 22020

Figure 4-68. Complete VGA Subsystem with COB

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-51 IC Device and Packaging Technology Trends

Source: Fujitsu 22057

Figure 4-69. Wireless Module in a Single Multichip Package (MCP)

Courtesy of Hughes Microelectronics 22562

Figure 4-70. High Performance Avionics Controller with 4 Thin Film MCMs Mounted on One Card

Among these four families of MCMs, there is one common feature that drives their use: the single- chip package is eliminated. This one change allows for four potential gains over the conventional approach of single-chip packages on circuit boards:

• Smaller size • Less weight • Higher performance • Lower cost

The size reduction possible with an MCM implementation is graphically apparent when two iden- tical designs are compared; figure 4-71 shows a direct comparison between single-chip packages on a substrate and the same chip set in an MCM.

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Source: nChip 15882

Figure 4-71. Comparison of Conventional and MCM RISC Microprocessor Chip Sets

The performance of a system can be increased by an MCM implementation only if critical nets exist between chips. If the clock frequency is limited by propagation delays within the core of the chip, no amount of packaging innovations will increase the clock frequency. However, if wiring delays influence the clock frequency, then the delays can be reduced by one-third to one-tenth, simply based on interconnect length reductions. This was the motivation of Intel to use an MCM for the Pentium Pro, shown in Figure 4-72; the proximity of the L2 cache to the CPU helps this model of the Pentium Pro achieve a 200MHz clock frequency.

Another performance benefit that may be gained in an MCM approach over a conventional approach is the reduction in switching noise, which allows for higher bandwidths.

There has been a tendency of associating substrate choice with a type of MCM. The following classifications have been defined by the IPC:

• MCM-L: uses a laminate substrate such as FR-4 • MCM-C: uses a cofired ceramic-based, multilayer substrate, either HTCC or LTCC, but not thick film • MCM-D: uses a thin-film, multilayer, deposited substrate, with substrates of silicon, ceramic or aluminum

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-53 IC Device and Packaging Technology Trends

• MCM-C/D: uses a multilayer cofired ceramic base with thin film built on top • MCM-L/D: uses a laminate base, with thin film built on top—sometimes referred to as build-up multilayer (BUM) or build-up board (BUB) technology • Silicon-on-silicon: uses a silicon substrate and thin-film multilayer interconnects

Source: Intel 20116

Figure 4-72. Pentium Pro Processor

Figures 4-73 and 4-74 compare the major substrate types. As can be seen, MCM-D provides the highest interconnection density and performance, in addition to the lowest weight and size, but also has the highest cost. Since cost is the governing factor effecting widespread use, MCM-Ds have thus far been used only in high-performance and specialized applications.

The MCM industry is combining substrate technologies to optimize technical solutions. In par- ticular, combinations of an MCM-C substrate containing ground and power connections with an MCM-D substrate providing the signal layers have proven viable. ICE expects this trend to con- tinue with the best features of each substrate style used as the application requires (Figure 4-75).

As shown in Figure 4-76, laminate-based MCMs accounted for the majority of MCMs sold in 1997; the figure includes sales of MCM-C/Ds in the MCM-C category and MCM-L/Ds in the MCM-L category. By 2002, MCM-Ls will still make up 55 percent of the multichip module market, but there will be significant movement to MCM-Ds as pricing becomes more competitive for these parts.

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MCM-D (deposited) ¥ High resolution (MCM-D/L) ¥ High density capability (MCM-D/C) ¥ Fine via capability ¥ High performance materials

MCM-L (laminated) MCM-C (co-fired) ¥ Large substrate format ¥ Hermetic packaging ¥ Low substrate cost ¥ Area array I/O compatibility ¥ Parallel processing ¥ Parallel processing ¥ Area array I/O capability

(MCM-L/C)

Source: Advanced Packaging/IPC Technology Roadmap 21768

Figure 4-73. MCM Substrate Materials and Processing Procedures

Characteristics MCM-C MCM-D MCM-L

Density Pitch per layer 10 mils (254 µm) 1 mil (25 µm) 8 mils (200 µm) No. of Layers >60 5 5-25 Materials Alumina Silicon FR-4 Aluminum Nitride Alumina Polyimide Beryllium Oxide Glass Power Dissipation High Medium Low Cost Medium High Low Speed Performance Medium High Low

Source: ICE 19129

Figure 4-74. MCM Substrate Comparison

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-55 IC Device and Packaging Technology Trends

Application Substrate Type

Notebook/Portable PDA MCM-L, MCM-L/D — initially COB then flip chip

Cellular Phones/Pagers MCM-L, MCM-L/D — rapidly going to flip-chip assembly

Camcorders/Games MCM-L, COB — evaluating flip chip

Military MCM-C, MCM-C/D — still need hermetic packaging, chip-and-wire assembly

Medical MCM-C for implantable products, MCM-L for instruments

Telecommunications MCM-D and MCM-L/D for performance — flip chip will be dominant

High-Performance Computing MCM-D and MCM-L/D — silicon Platforms substrates heavily used

Automotive MCM-L — flip chip, well established for MCM-C, will be used with MCM-L, some MCM-C under hood

Smart Cards MCM-L, strong user of TAB, will migrate to flip chip

Displays MCM-D with glass substrate, TAB and direct chip-on-glass with TAB for flip chip

Source: Consultar 19476

Figure 4-75. MCM Applications by Substrate Type

MCM-C 5%

MCM-C 9% MCM-D 1997 (EST) MCM-D 2002 (FCST) 28% MCM-L $950M 40% $2,900M 63% MCM-L 55%

*Not including components. Source: ICE 18526J

Figure 4-76. MCM Market Projections* ($)

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Known Good Die Issues

The availability of known-good die (KGD) continues to improve, but is still the most significant barrier in the bare-die-based MCM market. Even with the wide variation in the industry on what constitutes a KGD, there are increasing numbers of suppliers, both IC manufacturers and third party distributors that are now offering KGD (Figure 4-77).

Functional At-Speed and and DC Full KGD Company At-Temperature Parametric With Burn-In Test Test Advanced Micro Devices x x Allegro MicroSystems x American Microsystems x x Analog Devices x x Calogic x Chip Express x Chip Supply x x x Cypress Semiconductor x x Device Engineering x x Elmo Semiconductor x x x Eltek Semiconductor x Harris Semiconductor x IBM Microelectronics x x Integrated Device Technology x x Intel x x LSI Logic x Micron Technology x x x Minco Technology Labs x Motorola x x x National Semiconductor x x x Rood Testhouse x x x Semi Dice x SGS-Thomson x x Texas Instruments x x x Vitesse Semiconductor x x VLSI Technology x x

Source: EP&P 22388A

Figure 4-77. Bare Die Suppliers

As specifications for KGD standardize and technologies to implement them move up the learning curve, the price adders from KGD will converge. Currently, there is a wide variation among sup- pliers of KGD. National Semiconductor and Samsung offer some die at a lower price than the

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-57 IC Device and Packaging Technology Trends

packaged units; here the range is 0.8 to 1.2 times. Intel offers KGD at parity to packaged die prices in its SmartDie program. Most other suppliers, especially distributors, sell KGD at a 1.5 to 5 times premium justified by the extra efforts associated with acquiring, specifying, testing, and, for some suppliers, burn-in.

Key enablers to even faster proliferation of MCMs is decreasing the cost of KGD and increasing the number of suppliers. One test solution for KGD provides an example of the complexity involved: Texas Instruments teamed with MicroModule Systems (MMS) developed a temporary package called DieMate that allows manufacturers to test bare dice with area pads used in flip- chip technology. MMS supplies the thin-film packages that are custom made for a given chip type. The carrier (Figure 4-78) has contacts and an interconnect pattern laid on it so the chip for which it is made can be placed upside down with its bonding pads matching up to contacts in the carrier. The chip is held to the carrier with pressure during burn-in and testing, and is then released and removed, with an operator knowing whether the die is good or bad.

Force Delivery Mechanism

Die Lid

Die Edge Registration Feature

Carrier

Interconnect Compliant Material

Socket

Source: Semiconductor International/MMS 19228

Figure 4-78. Temporary Carrier for Die-Level Burn-In

Other companies, including Chip Supply, IBM, Intel, Lucent Technologies, Micron, and Motorola, have developed methods of testing known good die as well. Intel claims that revenues from its SmartDie program have been increasing at an average annual rate of 150 percent.

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