8 Evolutionary Advances in Conventional Packaging
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The NASA Electronic Parts and Packaging (NEPP) '02 Workshop
The NASA Electronic Parts and Packaging (NEPP) ‘02 Workshop 1 JPL 400-1015, 04/02 2 The NASA Electronic Parts and Packaging (NEPP) ‘02 Workshop April 30 - May 2, 2002 Hilton Nassau Bay & Marina Houston, TX Organized by: NEPP Information, Management and Dissemination Project 3 Message ________________________ from Chuck Barnes, NEPP Program Manager Welcome to the Annual NEPP Workshop on Electronic Parts, Packaging, and Radiation Characterization for Space Applications! We’re happy you are with us and look forward to talking with you. Let’s start off with a few words about the NASA Electronic Parts and Packaging (NEPP) Program. The NEPP objectives are to: Assess the reliability of newly available electronic parts and packaging technologies for usage on NASA projects through validations, assessments and characterizations and the development of test methods/tools. Expedite infusion paths for advanced (emerging) electronic parts and packaging technologies by evaluations of readiness for manufacturability and project usage considerations. Provide NASA Projects with technology selection, application, and validation guidelines for electronic parts and packaging hardware and processes. Retain and disseminate electronic parts and packaging assurance, reliability validations, tools and availability information to the NASA community. NEPP is organized around three technology concentrations and the Information Management and Dissemination effort. The technology concentrations are Electronic Parts (EPAR), Electronic Packaging (EPAC), and Electronic Radiation Characterization (ERC). The Information Management & Dissemination (IMD) project is responsible for making all NEPP products and deliverables accessible in a controlled manner and is coordinating this conference. The Electronic Parts Project is tied to satisfying the needs of NASA programs/projects for evaluation of newly available and advanced electronic parts and maximizing effectiveness and efficiency through leveraging by teaming and partnering with industry and other agencies. -
Understanding Performance Numbers in Integrated Circuit Design Oprecomp Summer School 2019, Perugia Italy 5 September 2019
Understanding performance numbers in Integrated Circuit Design Oprecomp summer school 2019, Perugia Italy 5 September 2019 Frank K. G¨urkaynak [email protected] Integrated Systems Laboratory Introduction Cost Design Flow Area Speed Area/Speed Trade-offs Power Conclusions 2/74 Who Am I? Born in Istanbul, Turkey Studied and worked at: Istanbul Technical University, Istanbul, Turkey EPFL, Lausanne, Switzerland Worcester Polytechnic Institute, Worcester MA, USA Since 2008: Integrated Systems Laboratory, ETH Zurich Director, Microelectronics Design Center Senior Scientist, group of Prof. Luca Benini Interests: Digital Integrated Circuits Cryptographic Hardware Design Design Flows for Digital Design Processor Design Open Source Hardware Integrated Systems Laboratory Introduction Cost Design Flow Area Speed Area/Speed Trade-offs Power Conclusions 3/74 What Will We Discuss Today? Introduction Cost Structure of Integrated Circuits (ICs) Measuring performance of ICs Why is it difficult? EDA tools should give us a number Area How do people report area? Is that fair? Speed How fast does my circuit actually work? Power These days much more important, but also much harder to get right Integrated Systems Laboratory The performance establishes the solution space Finally the cost sets a limit to what is possible Introduction Cost Design Flow Area Speed Area/Speed Trade-offs Power Conclusions 4/74 System Design Requirements System Requirements Functionality Functionality determines what the system will do Integrated Systems Laboratory Finally the cost sets a limit -
Chap01: Computer Abstractions and Technology
CHAPTER 1 Computer Abstractions and Technology 1.1 Introduction 3 1.2 Eight Great Ideas in Computer Architecture 11 1.3 Below Your Program 13 1.4 Under the Covers 16 1.5 Technologies for Building Processors and Memory 24 1.6 Performance 28 1.7 The Power Wall 40 1.8 The Sea Change: The Switch from Uniprocessors to Multiprocessors 43 1.9 Real Stuff: Benchmarking the Intel Core i7 46 1.10 Fallacies and Pitfalls 49 1.11 Concluding Remarks 52 1.12 Historical Perspective and Further Reading 54 1.13 Exercises 54 CMPS290 Class Notes (Chap01) Page 1 / 24 by Kuo-pao Yang 1.1 Introduction 3 Modern computer technology requires professionals of every computing specialty to understand both hardware and software. Classes of Computing Applications and Their Characteristics Personal computers o A computer designed for use by an individual, usually incorporating a graphics display, a keyboard, and a mouse. o Personal computers emphasize delivery of good performance to single users at low cost and usually execute third-party software. o This class of computing drove the evolution of many computing technologies, which is only about 35 years old! Server computers o A computer used for running larger programs for multiple users, often simultaneously, and typically accessed only via a network. o Servers are built from the same basic technology as desktop computers, but provide for greater computing, storage, and input/output capacity. Supercomputers o A class of computers with the highest performance and cost o Supercomputers consist of tens of thousands of processors and many terabytes of memory, and cost tens to hundreds of millions of dollars. -
Electronic Packaging Technologies 1
ElectronicElectronic PackagingPackaging TechnologiesTechnologies Sergio Lopez-Buedo, Eduardo Boemo Universidad Autonoma de Madrid e-mail: [email protected] Electronic Packaging Technologies 1 Introduction to Electronic Packaging • Electronic Packaging is a multi-disciplinary subject – Mechanical, Electrical and Industrial Engineering, Chemistry, Physics and even Marketing • Electronic Packaging: Housing and interconnection of integrated circuits to form electronic systems • Electronic Packaging must provide – Circuit support and protection – Heat dissipation – Signal distribution – Manufacturability and serviceability – Power distribution Electronic Packaging Technologies 2 Issues in Electronic Packaging Electrical analysis and testing Mechanical analysis and Reliability, Chemistry, testing Physics, Mat. performance, cost, Eng.. market need/timing, manufacturability, yields…other Thermal Manufacturing analysis and and Industrial testing Eng.. Market analysis Electronic Packaging Technologies 3 Hierarchy of Interconnection Levels • Level 0 – Gate-to-gate interconnections on the silicon die • Level 1 – Connections from the chip to its package • Level 2 – PCB, from component to component or to external connector • Level 3 – Connections between PCBs, including backplanes or motherboards • Level 4 – Connections between subassemblies, for example a rack • Level 5 – Connections between physically separate systems, using for example an Ethernet LAN Electronic Packaging Technologies 4 Blue Gene: Example of Connection Hierarchy Electronic -
2005 Injection Molded & Micro Fabrication Electronic Packaging
2005 INJECTION MOLDED & MICRO FABRICATION ELECTRONIC PACKAGING Dr. Ken Gilleo ET-Trends LLC Warwick, RI Dennis Jones Matrix, Inc. Providence, RI Abstract Thermoset epoxies, discovered nearly 80 years ago, remain the workhorse plastic for electronic packaging and printed circuit boards, but this could change with increasing technical, economic and regulatory demands. Modern halogen-free thermoplastics now boast superior properties and highly automated high-efficiency high-volume processes. Injection molding can readily produce intricate 3D structures suitable for electronic component packaging and 3D molded circuits. Although there is a well-established packaging infrastructure tied to thermoset epoxies there is a much larger world-wide manufacturing base that excels in thermoplastics. Nearly 16-billion pounds of thermoplastics are molded into various parts each year in the USA alone; 30 times higher than for epoxies. We believe that the time is right for adding thermoplastic packages, interconnects and circuitry to 21st century electronics. This paper will discuss concepts, novel designs, new processes and the advancements for injection molded packaging and highlight their impressive attributes; the lowest moisture uptake, the fastest processing and the highest stability in the world of polymers. While MEMS (Micro-Electro-Mechanical Systems) packaging will be a central theme, general component packaging will also be discussed including power packages and digital camera modules. The discussion will include the development of new BGA concepts that utilize automatic insert-molding of tiny metal balls to create the 1st (to chip) and 2nd level (to circuit board) interconnect system. Assembly topics will cover package sealing methods that include laser welding. New Multi-Chip Package (MCP) ideas based on insert-molded flexible circuitry will be described that could find use in stackable designs. -
Photovoltaic Couplers for MOSFET Drive for Relays
Photocoupler Application Notes Basic Electrical Characteristics and Application Circuit Design of Photovoltaic Couplers for MOSFET Drive for Relays Outline: Photovoltaic-output photocouplers(photovoltaic couplers), which incorporate a photodiode array as an output device, are commonly used in combination with a discrete MOSFET(s) to form a semiconductor relay. This application note discusses the electrical characteristics and application circuits of photovoltaic-output photocouplers. ©2019 1 Rev. 1.0 2019-04-25 Toshiba Electronic Devices & Storage Corporation Photocoupler Application Notes Table of Contents 1. What is a photovoltaic-output photocoupler? ............................................................ 3 1.1 Structure of a photovoltaic-output photocoupler .................................................... 3 1.2 Principle of operation of a photovoltaic-output photocoupler .................................... 3 1.3 Basic usage of photovoltaic-output photocouplers .................................................. 4 1.4 Advantages of PV+MOSFET combinations ............................................................. 5 1.5 Types of photovoltaic-output photocouplers .......................................................... 7 2. Major electrical characteristics and behavior of photovoltaic-output photocouplers ........ 8 2.1 VOC-IF characteristics .......................................................................................... 9 2.2 VOC-Ta characteristic ........................................................................................ -
COSC 6385 Computer Architecture - Multi-Processors (IV) Simultaneous Multi-Threading and Multi-Core Processors Edgar Gabriel Spring 2011
COSC 6385 Computer Architecture - Multi-Processors (IV) Simultaneous multi-threading and multi-core processors Edgar Gabriel Spring 2011 Edgar Gabriel Moore’s Law • Long-term trend on the number of transistor per integrated circuit • Number of transistors double every ~18 month Source: http://en.wikipedia.org/wki/Images:Moores_law.svg COSC 6385 – Computer Architecture Edgar Gabriel 1 What do we do with that many transistors? • Optimizing the execution of a single instruction stream through – Pipelining • Overlap the execution of multiple instructions • Example: all RISC architectures; Intel x86 underneath the hood – Out-of-order execution: • Allow instructions to overtake each other in accordance with code dependencies (RAW, WAW, WAR) • Example: all commercial processors (Intel, AMD, IBM, SUN) – Branch prediction and speculative execution: • Reduce the number of stall cycles due to unresolved branches • Example: (nearly) all commercial processors COSC 6385 – Computer Architecture Edgar Gabriel What do we do with that many transistors? (II) – Multi-issue processors: • Allow multiple instructions to start execution per clock cycle • Superscalar (Intel x86, AMD, …) vs. VLIW architectures – VLIW/EPIC architectures: • Allow compilers to indicate independent instructions per issue packet • Example: Intel Itanium series – Vector units: • Allow for the efficient expression and execution of vector operations • Example: SSE, SSE2, SSE3, SSE4 instructions COSC 6385 – Computer Architecture Edgar Gabriel 2 Limitations of optimizing a single instruction -
Book of Knowledge (BOK) for NASA Electronic Packaging Roadmap
National Aeronautics and Space Administration Book of Knowledge (BOK) for NASA Electronic Packaging Roadmap Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Pasadena, California Jet Propulsion Laboratory California Institute of Technology Pasadena, California JPL Publication 15-4 2/15 National Aeronautics and Space Administration Book of Knowledge (BOK) for NASA Electronic Packaging Roadmap NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Pasadena, California NASA WBS: 724297.40.43 JPL Project Number: 104593 Task Number: 40.49.02.24 Jet Propulsion Laboratory 4800 Oak Grove Drive Pasadena, CA 91109 http://nepp.nasa.gov i This research was carried out at the Jet Propulsion Laboratory, California Institute of Technology, and was sponsored by the National Aeronautics and Space Administration Electronic Parts and Packaging (NEPP) Program. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise, does not constitute or imply its endorsement by the United States Government or the Jet Propulsion Laboratory, California Institute of Technology. ©2015 California Institute of Technology. Government sponsorship acknowledged. Acknowledgments The author would like to acknowledge many people from industry and the Jet Propulsion Laboratory (JPL) who were critical to the progress of this activity. The author extends his appreciation to program managers of the National Aeronautics and Space Administration Electronics Parts and Packaging (NEPP) Program, including Michael Sampson, Ken LaBel, Dr. Charles Barnes, and Dr. Douglas Sheldon, for their continuous support and encouragement. ii OBJECTIVES AND PRODUCTS The objective of this document is to update the NASA roadmap on packaging technologies (initially released in 2007) and to present the current trends toward further reducing size and increasing functionality. -
Ceramic Leadless Chip Carrier (LCC)
Ceramic,Leadless,Chip,Carrier,(L Ceramic Leadless Chip Carrier (LCC) Literature Number: SNOA023 Ceramic Leadless Chip Carrier (LCC) August 1999 Ceramic Leadless Chip Carrier (LCC) 20 Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E20A © 2000 National Semiconductor Corporation MS101105 www.national.com 20 Lead Ceramic Leadless Chip Carrier NS Package Number EA20B Ceramic Leadless Chip Carrier (LCC) www.national.com 2 Ceramic Leadless Chip Carrier (LCC) 24 Lead Ceramic Leadless Chip Carrier NS Package Number E24B 28 Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E28A 3 www.national.com 28 Lead Ceramic Leadless Chip Carrier, Dual Cavity NS Package Number EA028C Ceramic Leadless Chip Carrier (LCC) www.national.com 4 Ceramic Leadless Chip Carrier (LCC) 32 Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E32A 32 Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E32B 5 www.national.com 32 Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E32C Ceramic Leadless Chip Carrier (LCC) 32 Lead Ceramic Leadless Chip Carrier, Type E NS Package Number EA32B www.national.com 6 Ceramic Leadless Chip Carrier (LCC) 32 Lead Ceramic Leadless Chip Carrier, DIP NS Package Number EA32C 40 Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E40A 7 www.national.com 44 Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E44A Ceramic Leadless Chip Carrier (LCC) 48 Lead Ceramic Leadless Chip Carrier NS Package Number EA48B www.national.com 8 Ceramic Leadless Chip Carrier (LCC) 68 Lead Ceramic -
Rapid Mapping of Digital Integrated Circuit Logic Gates Via Multi-Spectral Backside Imaging
RAPID MAPPING OF DIGITAL INTEGRATED CIRCUIT LOGIC GATES VIA MULTI-SPECTRAL BACKSIDE IMAGING RONEN ADATO1;4;∗, AYDAN UYAR1;4, MAHMOUD ZANGENEH1;4, BOYOU ZHOU1;4, AJAY JOSHI1;4, BENNETT GOLDBERG1;2;3;4 AND M SELIM UNL¨ U¨ 1;3;4 Abstract. Modern semiconductor integrated circuits are increasingly fabricated at untrusted third party foundries. There now exist myriad security threats of malicious tampering at the hardware level and hence a clear and pressing need for new tools that enable rapid, robust and low-cost validation of circuit layouts. Optical backside imaging offers an attractive platform, but its limited resolution and throughput cannot cope with the nanoscale sizes of modern circuitry and the need to image over a large area. We propose and demonstrate a multi-spectral imaging approach to overcome these obstacles by identifying key circuit elements on the basis of their spectral response. This obviates the need to directly image the nanoscale components that define them, thereby relaxing resolution and spatial sampling requirements by 1 and 2 - 4 orders of magnitude respectively. Our results directly address critical security needs in the integrated circuit supply chain and highlight the potential of spectroscopic techniques to address fundamental resolution obstacles caused by the need to image ever shrinking feature sizes in semiconductor integrated circuits. 1. Introduction Semiconductor integrated circuits (ICs) are pervasive and essential components in virtually all modern devices, from personal computers, to medical equipment, to varied military systems and technologies. Their functionality is defined by a massive number (∼ 106 − 109 currently) of in- terconnected logic gates that correspond physically to various nanoscale doped regions, polysilicon and metal (usually copper and tungsten) structures. -
Basic Design of MOSFET, Four-Phase, Digital Integrated Circuits
Scholars' Mine Masters Theses Student Theses and Dissertations 1969 Basic design of MOSFET, four-phase, digital integrated circuits Earl Morris Worstell Follow this and additional works at: https://scholarsmine.mst.edu/masters_theses Part of the Electrical and Computer Engineering Commons Department: Recommended Citation Worstell, Earl Morris, "Basic design of MOSFET, four-phase, digital integrated circuits" (1969). Masters Theses. 5304. https://scholarsmine.mst.edu/masters_theses/5304 This thesis is brought to you by Scholars' Mine, a service of the Missouri S&T Library and Learning Resources. This work is protected by U. S. Copyright Law. Unauthorized use including reproduction for redistribution requires the permission of the copyright holder. For more information, please contact [email protected]. BASIC DESIGN OF MOSFET, FOUR-PHASE, DIGITAL INTEGRATED CIRCUITS By t_fL/ () Earl Morris Worstell , Jr./ J q¥- 2., A Thesis submitted to the faculty of THE UNIVERSITY OF MISSOURI - ROLLA in partial fulfillment of the requirements for the Degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING Ro 11 a , M i sous ri 1969 Approved By i BASIC DESIGN OF MOSFET, FOUR-PHASE, DIGITAL INTEGRATED CIRCUITS by Earl M. Worstell, Jr. Abstract MOSFET is defined as metal oxide semiconductor field-effect transis tor. The integrated circuit design relates strictly to logic and switch ing circuits rather than linear circuits. The design of MOS circuits is primarily one of charge and discharge of stray capacitance through MOSFETS used as switches and active loads. To better take advantage of the possibilities of MOS technology, four phase (4¢) circuitry is developed. It offers higher speeds and lower power while permitting higher circuit density than does static or two phase (2cj>) logic. -
Quad Flat No-Lead (QFN) Evauation Test
National Aeronautics and Space Administration Quad Flat No-Lead (QFN) Evaluation Testing Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Pasadena, California Jet Propulsion Laboratory California Institute of Technology Pasadena, California 6/17 National Aeronautics and Space Administration Quad Flat No-Lead (QFN) Evaluation Testing NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Success Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Pasadena, California NASA WBS: 724297.40.43 JPL Project Number: 104593 Task Number: 40.49.02.35 Jet Propulsion Laboratory 4800 Oak Grove Drive Pasadena, CA 91109 http://nepp.nasa.gov 6/17 This research was carried out at the Jet Propulsion Laboratory, California Institute of Technology, and was sponsored by the National Aeronautics and Space Administration Electronic Parts and Packaging (NEPP) Program. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise, does not constitute or imply its endorsement by the United States Government or the Jet Propulsion Laboratory, California Institute of Technology. Copyright 2017. California Institute of Technology. Government sponsorship acknowledged. Acknowledgments The author would like to acknowledge many people from industry and the Jet Propulsion Laboratory (JPL) who were critical to the progress of this activity including the Rochester Institute of Technology (RIT). The author extends his appreciation to program managers of the National Aeronautics and Space