International Journal of Applied Engineering Research ISSN 0973-4562 Volume 14, Number 8 (2019) pp. 1965-1969 © Research India Publications. http://www.ripublication.com Comparison of Different Configurations of MicroBlaze Soft IP Core

Dr. S.Hema Chitra1, Sarvesh K2, Madhu Preetha BR3, 1Assistant Professor, Department of ECE, PSG College of Technology

2PG Student, Dept. of ECE, PSG College of Technology,

3PG Student, Dept. of ECE, PSG College of Technology

Abstract stated requirements can be satisfied by multi-processor environment. The multi-processor environment is expensive In this paper, Xilinx MicroBlaze soft IP core is configured in and the design time and effort of the development of the same different modes and the performance of the different modes is isalso high. The IP developers have come up with solution of compared in terms of Area Utilization. The soft processors are soft processors. The soft processors are IP core of the the one which enhances the performance in multiprocessor processors which are available as open source or as licensed environment. Soft processor cores enable the customizable version from many vendors. feature in the FPGA, so that the target device can be configured for different performance measures.Hard IP cores The soft processors are readily available in the RTLlevel of on the other hand cannot be customized, they have to be used abstraction and they can be used to program the FPGA to as such. The customizable property of soft IP cores in function as the multi-core processing system. The current different configurations is compared in this work. The processing requirements demands the processor to possess minimum area and maximum performance configurations of many features and most of the time these features are the MicroBlaze core has been analyzed. The comparison applicationspecific.Some examples of soft IP cores are PCI provides the means to select the particular configuration of master-target,32/64bit, PCIe, UART, CORDIC, DDS, MicroBlaze for a target application. The analysis has been FFTVME, USB, CAN, I2C, SPI, NIOS II.[3] done using XilinxVivado2017.1 MicroBlaze, is a soft processor from XILINX [1], is a 32-bit Keywords: MicroBlaze, soft processor, low power, maximum processor and it is available in various customizable performance and maximum area, Intellectual Property (IP) configurations. The presented work discusses the comparison of the different configurations of the MicroBlaze processor,

which helps in mapping the MicroBlaze processor for a 1. INTRODUCTION particular targetapplication. IP which stands for Intellectual Property is widely used in the fast-growing VLSI arena. An IP is a reusable unit of logic or 2. MICROBLAZE & ITS FEATURES A. functionality or a layout design that is normally developed MICROBLAZE with the idea of licensing to multiple vendor for using as building blocks in different chip designs[10]. There are 3 The MicroBlaze soft core processor is highly configurable, kinds of IPs, Hard IPs,Soft IPs and Firm IPs. Hard IPs are the allowing the user to select a specific set of features required ones which are not reconfigurable and soft IPs are the ones by the design[1,2].There are two sets of features in which can be reconfigured according to the given MicroBlaze IP architecture. They are fixed set of features specification. Firm IPs are semi customizable, some features which are present in all modes of configuration and can be customized whereas some are fixed. The main customizable features which can be customized according to advantage of IPs is that they are easily portable, reusable and the mode of configuration selected. they drastically reduce the design time and Time To Market. The fixed feature set of the processor includes thirty-two 32- IP vendors have multiple clients with different requirements. bit general-purpose registers, 32-bit instruction word with Multiple vendors may supply IPs but an extra effort is three operands and two addressing modes, 32-bit address bus, required to interface them. Including an IP can increase chip Single issue pipeline[3] cost but it brings down system cost.[1] The knowledge of the Figure 1 shows the MicroBlaze architecture. The white blocks target market is essential to make such decisions. are the blocks which are present in all modes of configuration The requirement for the high-speed processors is increasing and the colored blocks are the customizable blocks, which are enormously with the requirement for the high data rate, high- chosen according to the mode selected. speed computation and the large data handling. The above

1965 International Journal of Applied Engineering Research ISSN 0973-4562 Volume 14, Number 8 (2019) pp. 1965-1969 © Research India Publications. http://www.ripublication.com

Fig. 1 MicroBlaze Architecture

The MicroBlaze processor is available in different These MicroBlaze architecture in these two modes are configurations they are explored and compared.  Minimum Area: The smallest possible MicroBlaze The MicroBlaze IP is readily available in Xilinx Vivado [1]. core. No caches or debug.[2,3] By instantiating, a MicroBlaze IP is obtained. In order to change the mode of configuration, the IP is double clicked and  Maximum Performance: Maximum possible customizable parameters like frequency, area and performance. Large caches and debug, as well as all performance, as shown in. Based on the requirements, the IP execution units.[2,3] can be customized into the required mode.  Maximum Frequency: Maximum achievable frequency. Small caches and no debug, with few execution units.[2,3] 4. MICROBLAZE CONFIGURATION RESULTS  Linux with MMU: Settings suitable to get high In this section, the configuration of the modes minimum area performance when running Linux with MMU[2,3] and maximum performance are discussed.  Memory Management enabled, large caches and A. Minimum Area Configuration[2,4] debug, and all execution units.[2,3] The minimum area configuration is the one in which the high-  Low-end Linux with MMU: Settings corresponding performance cache is not included and the design offers less to the MicroBlaze Embedded[2,3] performance, the minimum area configuration is considered when the target application has the major concern for area 3. IMPLEMENTATION constraint circuits. The world is moving towards smaller and faster designs. The MicroBlaze is programmed for the minimum area There are area constraints when it comes to smaller designs configuration and the IP core is generated for basic and there is a tradeoff in area when it comes to faster design. microprocessor architecture. The HDL (Hardware Description There is always a tradeoff between speed and area. Designs Language) wrapper is generated for the same and the with faster speed have more area and designs with lower area synthesis of the same is done using Vivado 2017. Fig. 2 shows have lesser speed when compared to bigger designs.[5,6] the MicroBlaze in Minimum area configuration. HDL is the language of choice to describe an FPGA design. A HDL Thus, two modes of configuration are taken into wrapper is basically a top-level description of the system. This consideration, minimum area and maximum performance.

1966 International Journal of Applied Engineering Research ISSN 0973-4562 Volume 14, Number 8 (2019) pp. 1965-1969 © Research India Publications. http://www.ripublication.com wrapper connects the output/input port of the design to the 5. COMPARISON BETWEEN THE TWO MODES physical pin described in the constraint file. OF CONFIGURATION The MicroBlaze processor is implemented in two different configurations in the Xilinx Vivado platform. The MicroBlaze soft processor IP is readily available in the Xilinx, and the different IP blocks are connectedtogether to form a generic processor architecture. The various blocks which have been included in the design are : MicroBlaze, AXI lite interface, The power on reset module, The Clock Generator module, The GPIO block. The above stated blocks are connected together in the generic configuration and the micro blaze is programmed to operate in two differentconfigurations, Minimum Area and Maximum Performance. Fig. 2 Minimum Area Configuration The comparison summaries of the 2 modes are given in the

Tables 1 and 2. Table 1 shows the report generated for B. Maximum Performance Configuration[2,4] Minimum area configuration and Table 2 shows the report for Maximum Performance. The maximum performance configuration of the MicroBlaze includes all the available features of the MicroBlaze processor. The maximum performance configuration includes Table 1: Minimum area Utilization report the high speed cache memory, and high performance data cache is included and it is targeted for the high area, high performance applications. The high performance of the design traded off with the area and power consumption requirements of theprocessor. The maximum performance configuration of the design is used to achieve high-speed, highly efficient processors. It is used for computationally complexalgorithms. The maximum performance mode of configuration is shown in Fig. 3

As shown in Table 1, the design uses 985 slice LUTs, 1334 slice registers, 33 mux and 2 block RAM tiles.

Table 2: Maximum Performance Utilization report

Fig.3 Maximum Performance Configuration As shown in Table2, the design uses 4214 slice LUTs, 4218 By looking at the two figures 1 and 2 it can be noted that Fig. slice registers, 148 mux and 21 block RAM tiles. 1 has less number of blocks without any Cache memory which is the minimum area configuration. Fig. 2 having more no. of blocks, including cache memory and is designed for Table 3 shows the comparison between the two modes of maximum performance. configuration and the percentage increase in area with respect to number of slice LUTs, registers, mux, block RAM used.

1967 International Journal of Applied Engineering Research ISSN 0973-4562 Volume 14, Number 8 (2019) pp. 1965-1969 © Research India Publications. http://www.ripublication.com

Table 3: Comparison between the 2 modes of configuration A.A. and Wolf W., (Eds.), Miltiprocessor Systems-on- Chips, Elsevier, Amsterdam, 2005. Min. Max. Percentage [8] Core Connect Bus Architecture, IBM Area Performan increase in Microelectronics, available at ce area (%) http:==www.ibm.com=chips=products=coreconne ct, January 2006. LUTs 985 4214 327.82 [9] ARM.AMBA Specifications v2.0, 1999, available at http:==www.arm.com, January 2006. Slice 1334 4218 216.19 [10] M. Dalpasso, A. Bogliolo, L. Benini, registers "Hardware/software IP protection", Design Automation Conference 2000. Proceedings 2000, pp. 593-596, 2000. Mux 33 148 348.48 [11] D.D. Gajski, A.C.-H. Wu, V. Chaiyakul, S. Mori, T. Block 2 21 950 Nukiyama, P. Bricaud, "Essential issues for IP reuse", Design Automation Conference 2000. RAM Proceedings of the ASP-DAC 2000. Asia and South tile Pacific, pp. 37-42, 2000 [12] K. Ueda, K. Sakanushi, Y. Takeuchi, M. Imai, "Architecture-level performance estimation for IP- As shown in the above table Minimum area configuration uses based embedded systems", Design Automation and least possible components when compared to the maximum Test in Europe Conference and Exhibition 2004. performance configuration which aims at performance and not Proceedings, vol. 2, pp. 1002-1007 Vol.2, 2004. area utilization. Thus, there is always a tradeoff between area [13] Miguel A. S'nchez, Marisa Lopez-Vallejo, Carlos A. and speed. Iglesias, Carlos A. Lopez-Barrio, "Improving Hardware Reuse through XML-based Interface Encapsulation", Engineering of Complex Computer VI. CONCLUSION Systems (ICECCS) 2012 17th International The comparison of the different configurations gives us the Conference on, pp. 49-56, 2012. aid in choosing the particular configuration for a targeted [14] “A DESIGN METHODOLOGY FOR INTEGRATING application. The same configuration can be implemented in IP INTO SOC SYSTEMS” Philippe Coussy, Adel the Software Development Kit (SDK). The application can be Baganne, Eric Martin LESTER - UniversitC de run over the multiprocessor, to enhance the prototyping and Bretagne Sud - BP 921 16 - 56321 LOMENT Cedex, the targeted application requirements. Thus, the study reveals France { firstname.lastname } @ univ-ubs that the Xilinx MicroBlaze core is suitable for both low area and high-speed applications. [15] R. L. Lysescky, F. Vahid, T. D. Givargis, "Techniques for reducing Read Latency of Core Bus Wrapper 'I, in Proc. ofDATE, March 2000 REFERENCES [16] K. Van Rompaey, D. Verkest, I. Bolsens, H. De [1] http//www.xilinx.com/xilinx2017_2 Man, "Coware A design environment for heterogeneous hw/sw systems", in Proc of [2] http// www.micro-blaze.org EUIPODAC,1996 [3] http// reference.digilentinc.com [17] G. Cyr, G. Bois, M. Aboulhamid, "Synthesis of communication Interfaces for SOC using VSIA [4] Keating M. and Bricaud P., Reuse Methodology recommendation", in Proc. of DATE, 2001 Manual for System-on-a-Chip Designs, 2=E= Kluwer Academic Publishers, Boston, MA, 1999. [18] A. Baganne, J-L. Philippe, E. Martin, "A Formal Technique For Hardware Interface Design", in Proc [5] Ho W.H. and Pinkston T.M., A design methodology of ISCAS, 1997 for efficient application-specific on-chip interconnects, IEEE Trans. Parallel Distributed Syst., [19] D. Gajski, N. Dutt, A. Wu, S. Lin, "High-level 17(2): 174–190, February 2006. synthesis introduction to Chip and Sysrem Design", Kluwer Academic Publishers, Boston, 1992 [6] Horspool N. and Gorman P., The ASIC Handbook, Prentice Hall, PTR, Upper Saddle River, NJ,2001. [20] J. Staunstrup, W. Wolf :"Hardware software Co- design Principles and practice", Kluwer academic [7] Bernini L. and De Micheli G., Networks on chips: A publisher,1997 new paradigm for component-based mpsoc design, chapter 3, pp. 49–80, in Jerraya

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