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ECE 4750 Computer Architecture Topic 1: Microcoding

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ECE 4750 Computer Architecture Topic 1: Microcoding ECE 4750 Computer Architecture Topic 1: Microcoding Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece4750 slide revision: 2013-09-01-10-42 Instruction Set Architecture Microcoded MIPS Processor Microcoding Discussion & Trends Agenda Instruction Set Architecture IBM 360 Instruction Set MIPS Instruction Set ISA to Microarchitecture Mapping Microcoded MIPS Processor Microcoded MIPS Microarchitecture #1 Microcoded MIPS Microarchitecture #2 Microcoding Discussion and Trends ECE 4750 T01: Microcoding 2 / 45 • Instruction Set Architecture • Microcoded MIPS Processor Microcoding Discussion & Trends Instruction Set Architecture I Contract between software & hardware Application Algorithm I Typically specified as all of the Programming Language programmer-visible state (registers & Operating System memory) plus the semantics of instructions Instruction Set Architecture Microarchitecture that operate on this state Register-Transfer Level IBM 360 was first line of machines to Gate Level I Circuits separate ISA from microarchitecture and Devices implementation Physics ... the structure of a computer that a machine language programmer must understand to write a correct (timing independent) program for that machine. — Amdahl, Blaauw, Brooks, 1964 ECE 4750 T01: Microcoding 3 / 45 • Instruction Set Architecture • Microcoded MIPS Processor Microcoding Discussion & Trends Compatibility Problem at IBM I By early 1960’s, IBM had several incompatible lines of computers! . Defense : 701 . Scientific : 704, 709, 7090, 7094 . Business : 702, 705, 7080 . Mid-Sized Business : 1400 . Decimal Architectures : 7070, 7072, 7074 I Each system had its own: . Instruction set . I/O system and secondary storage (tapes, drums, disks) . Assemblers, compilers, libraries, etc . Market niche ECE 4750 T01: Microcoding 4 / 45 • Instruction Set Architecture • Microcoded MIPS Processor Microcoding Discussion & Trends IBM 360: A General-Purpose Register Machine I Processor State . 16 general-purpose 32-bit registers . 4 floating point 64-bit registers . Program counter (PC), condition codes, control flags I Data Format . 8-bit bytes, 16-bit half-words, 32-bit words, 64-bit double-words . IBM 360 is why bytes are 8-bits long today! I Instruction Format . Variable length from 2–6 bytes long I Memory Addressing . 32-bit machine with only 24-bit addressing ECE 4750 T01: Microcoding 5 / 45 • Instruction Set Architecture • Microcoded MIPS Processor Microcoding Discussion & Trends IBM 360: Initial Implementations Model 30 Model 70 Storage 8–64 KB 256–512 KB Datapath 8-bit 64-bit Circuit Delay 30 ns/level 5 ns/level Local Store Main store Transistor registers Control Store Read only 1µs Conventional circuits IBM 360 instruction set architecture (ISA) completely hid the underlying technological differences between various models Significant Milestone: The first true ISA designed as a portable hardware-software interface ECE 4750 T01: Microcoding 6 / 45 • Instruction Set Architecture • Microcoded MIPS Processor Microcoding Discussion & Trends IBM 360: 45 years later ... The zSeries Z196 Microprocessor I 5.2 GHz in IBM 45 nm SOI I 1.4B transistors in 512 mm2 I Four cores per chip I Aggressive out-of-order execution I Four-level cache hierarchy with embedded DRAM L3/L4 I Available in September 2010 I Can still run IBM 360 code! — Hot Chips 2010 ECE 4750 T01: Microcoding 7 / 45 • Instruction Set Architecture • Microcoded MIPS Processor Microcoding Discussion & Trends MIPS32 Instruction Set I Processor State . 32 general-purpose 32-bit registers . 32 SP (16 DP) floating-point regs . Program counter, FP status reg I Data Format . 8-bit bytes, 16-bit half-words, 32-bit words . 32-bit single-precision, 64-bit double-precision floating-point I Instruction Format . Fixed-length 32-bit instructions I Memory Addressing . Data addressing with immediate and indexed . Branch addressing with PC relative and register indirect . Byte addressable memory as big or little endian ECE 4750 T01: Microcoding 8 / 45 • Instruction Set Architecture • Microcoded MIPS Processor Microcoding Discussion & Trends Data FoMIPSrma Datats an Formatsd Mem &o Memoryry Add Addressingresses Data formats: Bytes, Half words, words and double words Some issues Most Significant Least Significant •! Byte addressing Byte Byte Big Endian 0 1 2 3 vs. Little Endian 3 2 1 0 Byte Addresses •! Word alignment Suppose the memory is organized in 32-bit words. Can a word address begin only at 0, 4, 8, .... ? 0 1 2 3 4 5 6 7 ECE 4750 T01: Microcoding 9 / 45 January 24, 2011 CS152 Spring 2011 11 • Instruction Set Architecture • Microcoded MIPS Processor Microcoding Discussion & Trends MIPS Instruction Formats 6 5 5 5 5 6 ALU 0 rs rt rd 0 func R[rd] R[rs] func R[rt] 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 16 ALUI opcode rs rt immediate R[rt] R[rs] op immediate 31 26 25 21 20 16 15 0 6 5 5 16 ST: M[ R[rs] + sext(offset) ] R[rt] LD/ST opcode rs rt offset LD: R[rt] M[ R[rs] + sext(offset) ] 31 26 25 21 20 16 15 0 6 5 5 16 if ( R[rs] == 0 ) BEQZ opcode rs 0 offset PC PC+4 + offset*4 31 26 25 21 20 16 15 0 6 5 5 16 PC R[rs] JR/JALR opcode rs 0 0 JALR also does R[31] PC+8 31 26 25 21 20 16 15 0 6 26 PC jtarg( PC, target ) J/JAL opcode target JAL also does R[31] PC+8 31 26 25 0 ECE 4750 T01: Microcoding 10 / 45 • Instruction Set Architecture • Microcoded MIPS Processor Microcoding Discussion & Trends More Information on MIPS32 I Hennessy & Patterson, “Computer Architecture,” 5th ed, App. A I Harris & Harris, “Digital Design & Computer Architecture,” 2nd ed, Ch. 6, App. B I Sweetman, “See MIPS Run Linux,” 2nd ed I The MIPS32/64 Instruction Set manual (http://www.mips.com) ECE 4750 T01: Microcoding 11 / 45 • Instruction Set Architecture • Microcoded MIPS Processor Microcoding Discussion & Trends ISA to Microarchitecture Mapping Status Application Signals ControlAlgorithm Unit Programming Language Control Signals Operating System Instruction Set Architecture Logic State Logic Datapath Microarchitecture Register-Transfer Level Gate Level Circuits I Microarchitectural Structure:Devices Physics How components are statically connected together I Microarchitectural Function: How data is dynamically processed or stored in components ECE 4750 T01: Microcoding 12 / 45 • Instruction Set Architecture • Microcoded MIPS Processor Microcoding Discussion & Trends Many Microarchitectures are Possible I ISA map to many similar yet distinct microarchitectures & impls . 360 ! IBM 360 Model 30, IBM Z196 . x86 ! Intel 80486, AMD Bobcat, VIA Nano . ARM ! Cellphone implementations from TI, Qualcomm, Samsung . PARC ! Labs: pipelined with stalling, pipelined with bypassing I Architectural design patterns capture common classes of instruction sets and a suitable microarchitectural template . CISC ! microcoded . RISC ! hardwired, pipelined . VLIW ! fixed-latency in-order parallel pipelines . JVM ! software interpretation I ISAs can always be implemented with alternative microarchitectures . Intel Nehalem: Hardwired pipelined CISC proc, w/ some µcode . ARM Jazelle: A hardwired JVM processor . This lecture: A microcoded RISC (MIPS) processor ECE 4750 T01: Microcoding 13 / 45 Instruction Set Architecture • Microcoded MIPS Processor • Microcoding Discussion & Trends Agenda Instruction Set Architecture IBM 360 Instruction Set MIPS Instruction Set ISA to Microarchitecture Mapping Microcoded MIPS Processor Microcoded MIPS Microarchitecture #1 Microcoded MIPS Microarchitecture #2 Microcoding Discussion and Trends ECE 4750 T01: Microcoding 14 / 45 Instruction Set Architecture • Microcoded MIPS Processor • Microcoding Discussion & Trends Why Look Microprogramming at Now? I To show how to build very small processors with complex ISAs I Because it is still used in most common machines I As a gentle introduction to machine structures I To help you understand where CISC machines came from I To help understand how technology drove the move to RISC ECE 4750 T01: Microcoding 15 / 45 Instruction Set Architecture • Microcoded MIPS Processor • Microcoding Discussion & Trends Microcoding: Embed ctrl logic state in memory array holds fixed microcode instructions busy? zero? µcontroller opcode (ROM) Datapath Data Addr Memory enMem (RAM) MemWrt holds user program written in macrocode — Maurice Wilkes, 1954 instructions (e.g., MIPS, x86, etc.) ECE 4750 T01: Microcoding 16 / 45 Instruction Set Architecture • Microcoded MIPS Processor • Microcoding Discussion & Trends Bus-Based Datapath for MIPS Opcode zero? busy ldIR OpSel ldA ldB 32(PC) ldMA 31(Link) rd rt 2 rs RegSel MA rd 3 rt addr addr IR rs A B 32 GPRs ExtSel + PC ... Memory Imm ALU RegWrt MemWrt 2 Ext control ALU 32-bit Reg enReg enImm enALU data data enMem Bus 32 Microinstruction: register to register transfer (17 control signals) MA ← PC means RegSel = PC; enReg=yes; ldMA = yes B ← Reg[rt] means RegSel = rt; enReg=yes; ldB = yes ECE 4750 T01: Microcoding 17 / 45 Instruction Set Architecture • Microcoded MIPS Processor • Microcoding Discussion & Trends Memory Module Assumption: Memory operates independently and is slow compared to addr busy register-to-register transfers (multiple CPU Write(1)/Read(0) RAM we clock cycles per access) Enable din dout bus ECE 4750 T01: Microcoding 18 / 45 Instruction Set Architecture • Microcoded MIPS Processor • Microcoding Discussion & Trends Instruction Execution Steps I 1. Instruction fetch I 2. Decode and register fetch I 3. ALU operation I 4. Memory operation if required I 5. Register write-back if required I — Computation of the next instruction to fetch ECE 4750 T01: Microcoding 19 / 45 Instruction Set Architecture • Microcoded MIPS Processor • Microcoding Discussion & Trends Microprogram Fragments I Instruction Fetch I ALUI . MA PC . A R[rs] . IR Memory . B Imm (sign extend?) . A PC . R[rt] opcode(A,B) . PC A + 4 . do instruction fetch . dispatch on opcode I LW I ALU . A R[rs] . A R[rs] . B Imm (sign extend?) . B R[rt] . MA A + B . R[rd] func(A,B) . R[rt] Memory . do instruction fetch . do instruction fetch ECE 4750 T01: Microcoding 20 / 45 Instruction Set Architecture • Microcoded MIPS Processor • Microcoding Discussion & Trends Microprogram Fragments I J I BEQZ . A PC . A R[rs] . B IR . if zero?(A) then goto br-taken .
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