Simple Computer Example Register Structure

Read pp. 27-85 Simple Computer

• To illustrate how a computer operates, let us look at the design of a very simple computer • Specifications 1. Memory words are 16 bits in length 2. 2 12 = 4 K words of memory 3. Memory can be accessed in one clock cycle 4. Single Accumulator for ALU (AC) 5. Registers are fully connected Simple Computer Continued

4K x 16 Memory

MAR 12 MDR 16 X

PC 12 ALU IR 16

AC Simple Computer Specifications (continued) 6. Control signals • INCPC – causes PC to increment on clock edge - [PC] +1 PC

•ACin - causes output of ALU to be stored in AC • GMDR2X – get memory data register to X - [MDR] X • Read (Write) – Read (Write) contents of memory location whose address is in MAR To implement instructions, control unit must break down the instruction into a series of register transfers (just like a complier must break down C program into a series of machine level instructions) Simple Computer (continued)

• Typical microinstruction for reading memory

State Register Transfer Control Line(s) Next State 1 [[MAR]] MDR Read 2

• Timing State 1 State 2 During State 1, Read set by control unit CLK - Data is read from memory - MDR changes at the Read beginning of State 2 - Read is completed in one clock cycle MDR Simple Computer (continued) • Study: how to write the microinstructions to implement 3 instructions • ADD address • ADD (address) • JMP address ADD address: add using direct addressing 0000 address [AC] + [address] AC ADD (address): add using indirect addressing 0001 address [AC] + [[address]] AC JMP address 0010 address address PC Instruction Format for Simple Computer

IR OP 4 AD 12 AD = address

- Two phases to implement instructions: 1. Fetch – get the instruction from memory 2. Execution – carry out the actions of particular instruction – do required data transfer Microinstructions

State Register Transfer Control Line(s) Next State Fetch instruction 0 [PC] MAR GPC2MAR 1 1 [[MAR]] MDR Read 2 2 [MDR] IR GMDR2IR 3 3 [PC] +1 PC INCPC 4, 8, 11

ADD address 4 [AD] MAR GIR2MAR 5 5 [[MAR]] MDR Read 6 6 [MDR] X GMDR2X 7

7 [X] +[AC] AC ACin 0 ADD (address) 8 [AD] MAR GIR2MAR 9 9 [[MAR]] MDR Read 10 10 [MDR] MAR GMDR2MAR 5 JMP address 11 [AD] PC GIR2PC 0 Topics Motivated by the Simple Computer The simple computer motivates several topics that should be studied carefully throughout this course 1. Organization of instruction and data in the main memory • Instructions are often several words long • Data could be bytes, words or even larger size 2. Ways of memory accessing – addressing mode • More modes than just direct and indirect • With general purpose registers - Register mode, index mode (for table) autoincrement/autodecrement 3. Look at structure of registers • Able to load, clear, increment, decrement 4. Look at interconnection structure between signals • Not fully interconnected • Use buses A More Complicated Processor

• Structure – Eight 32-bit data registers: D0 – D7 – Eight 32-bit address registers: A0 – A7 – Data registers include general purpose accumulators – One 32-bit Program Counter (PC) – One 16-bit Status Register (SR) Reg. Structure (continued) • Operands – 3 different lengths – Word – basic 16 bits – Byte 8 bits – Long word – 32 bits – When accessing byte or word of register – operand from lower bit positions • A0 - A6 – address registers – Used to determine address of memory operands (pointer into memory) – Used as index registers • A7 – A stack pointer • Status Register (SR) – discuss later The Instructions

• Symbolic assembly language is the native language of a processor, and lowest level language of a computer • ADD.L D1, D2 Add all 32 bits Source Destination • Register transfer – [D1] + [D2] D2 Content of D1 + Content of D2 D2 • Instruction stored in the memory as Op Code Add. Inf. for Destin Add. Inf. for Src Instruction (continued)

• Machine Language – language in the binary code

Op Mode

Op Code REG Size ADDR MODE REG 1 1 0 1 0 1 0 0 1 0 0 0 0 0 0 1

Length of the operand D2 Operand in Op Code for 00=byte D1 Source destination 01=word D register ADD with a 10=long word register 0: destination is a register