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Quiz 0 Lecture 2: The Instruction Set Architecture

COS / ELE 375

Computer Architecture and Organization

Princeton University Fall 2015

Prof. David August

1 2

Quiz 0 CD

3 Miles of Music

3 4 Pits and Lands Interpretation

0 1 1 1 0 1 0 1

As Music:

011101012 = 117/256 position of speaker

As Number: Transition represents a bit state (1/on/red/female/heads) 01110101 = 1 + 4 + 16 + 32 + 64 = 117 = 75 No change represents other state (0/off/white/male/tails) 2 10 16 (Get comfortable with base 2, 8, 10, and 16.)

As Text: th 011101012 = 117 character in the ASCII codes = “u”

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Interpretation – ASCII Princeton Science Building West Wall

7 8 Interpretation Binary Code and Data (Hello World!)

• Programs consist of Code and Data • Code and Data are Encoded in Bits IA-64 Binary (objdump) As Music:

011101012 = 117/256 position of speaker

As Number:

011101012 = 1 + 4 + 16 + 32 + 64 = 11710 = 7516

As Text: th 011101012 = 117 character in the ASCII codes = “u”

CAN ALSO BE INTERPRETED AS MACHINE INSTRUCTION!

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Interfaces in Computer Systems Instructions

Sequential Circuit!! Software: Produce Bits Instructing Machine to Manipulate State or Produce I/O information State

Applications • Input/Output (I/O)

Operating System • State (memory) • Computation () Compiler Firmware Instruction Set Architecture Input Output Instruction Set Processor I/O System & Control Computation Digital Design Circuit Design • Instructions instruct processor to manipulate state Layout • Instructions instruct processor to produce I/O in the same way Hardware: Read and Obey Instruction Bits

12 State State – Main Memory

Typical modern machine has this architectural state: Main Memory (AKA: RAM – Random Access Memory) 1. Main Memory • Data can be accessed by address (like a big array) 2. Registers • Large but relatively slow 3. Program • Decent desktop machine: 1 Gigabyte, 800MHz

Address Data 0000 01011001 Architectural – Part of the assembly programmer’s interface 2 0001 F5 (Implementation has additional microarchitectural state) 16 0002 7816

0003 3A16 … …

FFFF 000000002 Byte Addressable

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State – Main Memory State – Main Memory

Address Data Address Data Read: Write: 0000 01011001 0000 01011001 1. Indicate READ 2 1. Indicate WRITE 2 0001 F5 0001 F5 2. Give Address 16 2. Give Address and Data 16 0002 78 0002 78 3. Get Data 16 16 0003 3A16 0003 3A121616 … … … …

FFFF 000000002 FFFF 000000002

Read/Write Read/Write READ WRITE Address Address 0002 0003 Data Data 7816 1216

15 16 State – Registers State – Program Counter

Registers (AKA: ) • Data can be accessed by register number (address) Program Counter (AKA: PC, Instruction Pointer, IP) • Small but relatively fast (typically on processor chip) • Instructions change state, but which instruction now? • Decent desktop machine: 8 32-bit registers, 3 GHz • PC holds of currently executing instruction

Register Data in Reg Address Data in Memory 0 0000000016 Program Counter 0000 010110012 1 F629D9B516 0002 0001 F516 2 7B2D9D0816 0002 ADDinst 3 0000000116 0003 SUBTRACTinst … … … … 8 DEADBEEF16 FFFF 000000002

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State – Program Counter State – Summary

Program Counter (AKA: PC, Instruction Pointer, IP) Typical modern machine has this architectural state: • Instructions change state, but which instruction now? 1. Main Memory – Big, Slow • PC holds address of currently executing instruction 2. Registers – Small, Fast (always on processor chip) • PC is updated after each instruction 3. Program Counter – Address of executing instruction

Address Data in Memory Architectural – Part of the assembly programmer’s

Program Counter 0000 010110012 interface

0003 0001 F516 (implementation has additional microarchitectural state)

0002 ADDinst

0003 SUBTRACTinst … …

FFFF 000000002

19 20 An Aside: State and The Interfaces in Computer Systems

Software: Produce Bits Instructing Machine to Manipulate State or Produce I/O • Core Dump: the state of the

machine at a given time Applications Registers • Typically at program failure Operating System 0 1 2 3 4 5 6 7 • Core dump contains: 0000 0788 B700 0010 0401 0002 0003 00A0 • Register Contents PC 8 9 A B C D E F Compiler Firmware 10 0000 0788 B700 0010 0401 0002 0003 00A0 • Memory Contents Instruction Set Architecture • PC Value Main Memory Instruction Set Processor I/O System 00: 0000 0000 0000 0000 0000 0000 0000 0000 Datapath & Control 08: 0000 0000 0000 0000 0000 0000 0000 0000 10: 9222 9120 1121 A120 1121 A121 7211 0000 Digital Design 18: 0000 0001 0002 0003 0004 0005 0006 0007 20: 0008 0009 000A 000B 000C 000D 000E 000F Circuit Design 28: 0000 0000 0000 FE10 FACE CAFE ACED CEDE Layout . . E8: 1234 5678 9ABC DEF0 0000 0000 F00D 0000 Hardware: Read and Obey Instruction Bits F0: 0000 0000 EEEE 1111 EEEE 1111 0000 0000 F8: B1B2 F1F5 0000 0000 0000 0000 0000 0000 21

Instructions Instructions

Register Data

An ADD Instruction: Instructions: 0 0 add r1 = r2 + r3 (assembly) “The vocabulary of commands” 1 15

Specify how to operate on state 2 1

Opcode Operands 3 2

Example: … …

40: add r1 = r2 + r3 31 0 Parts of the Instruction: 44: sub r3 = r1 - r0 Address Data • (verb) – what operation to perform 48: store M[ r3 ] = r1 0 0 • Operands (noun) – what to operate upon 52: load r2 = M[ 2 ] 1 25 • Source Operands – where values come from 2 5 • Destination Operand – where to deposit data values Program Counter 3 9 40 … …

FFFFFFFF 0 Instructions Instructions

Register Data Register Data Instructions: 0 0 0 0

“The vocabulary of commands” 1 15 1 3

Specify how to operate on state 2 1 2 1 3 2 3 2 Example: … … Example: … … 31 0 40: add r13 = r2 + r3 40: add r1 = r2 + r3 31 0 44: sub r3 = r1 - r0 Address Data 44: sub r3 = r1 - r0 Address Data 48: store M[ r3 ] = r1 48: store M[ r3 ] = r1 0 0 0 0 52: load r2 = M[ 2 ] 52: load r2 = M[ 2 ] 1 25 1 25

2 5 2 5 Program Counter 3 9 Program Counter 3 9 40 … … 40 … …

FFFFFFFF 0 FFFFFFFF 0

Instructions Instructions

Register Data Register Data

Instructions: 0 0 Instructions: 0 0

“The vocabulary of commands” 1 3 “The vocabulary of commands” 1 3

Specify how to operate on state 2 1 Specify how to operate on state 2 1 3 2 3 3 Example: … … Example: … … 40: add r1 = r2 + r3 31 0 40: add r1 = r2 + r3 31 0 44: sub r33 = r1 - r0 Address Data 44: sub r3 = r1 - r0 Address Data 48: store M[ r3 ] = r1 48: store M[ r3 ] = r13 0 0 0 0 52: load r2 = M[ 2 ] 52: load r2 = M[ 2 ] 1 25 1 25

2 5 2 5 Program Counter 3 9 Program Counter 3 9 44 … … 48 … …

FFFFFFFF 0 FFFFFFFF 0 Instructions Instructions

Register Data Register Data

Instructions: 0 0 Instructions: 0 0

“The vocabulary of commands” 1 3 “The vocabulary of commands” 1 3

Specify how to operate on state 2 1 Specify how to operate on state 2 5 3 3 3 3 Example: … … Example: … … 40: add r1 = r2 + r3 31 0 40: add r1 = r2 + r3 31 0 44: sub r3 = r1 - r0 Address Data 44: sub r3 = r1 - r0 Address Data 48: store M[ r3 ] = r1 48: store M[ r3 ] = r1 0 0 0 0 52: load r25 = M[ 2 ] 52: load r2 = M[ 2 ] 1 25 1 25

2 5 2 5 Program Counter 3 3 Program Counter 3 3 52 … … 52 … …

FFFFFFFF 0 FFFFFFFF 0

Instructions Assembly Instructions and C

Register Data main() { Note: 0 0 int a = 15, b = 1, c = 2; 1. Insts Executed in Order 1 3

2. Addressing Modes 2 5 add r1 = r2 + r3 a = b + c; /* a gets 3 */ 3 3

… … Example: sub r3 = r1 - r0 c = a; /* c gets 3 */ 31 0 40: add r1 = r2 + r3 44: sub r3 = r1 - r0 Address Data store M[ r3 ] = r1 *(int *)c = a; 48: store M[ r3 ] = r1 /* M[c] = a */ 0 0 52: load r2 = M[ 2 ] 1 25 load r2 = M[ 2 ] b = *(int *)(2); 2 5 /* b gets M[2] */ Program Counter 3 3 } 52 … …

FFFFFFFF 0 Branching

Suppose we could only execute instructions in sequence.

Recall from our example: 40: add r1 = r2 + r3 44: sub r3 = r1 - r0 48: store M[ r3 ] = r1 52: load r2 = M[ 2 ]

• In a decent desktop machine, how long would the longest program stored in main memory take? • Assume: • 1 instruction per cycle • An instruction is encoded in 4 bytes (32 bits)

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Therefore… Unconditional Branches

• Some instructions must execute more than once • Unconditional branches always update the PC • PC must be updated • AKA: Jump instructions

Example: Example: 40: add r1 = r2 + r3 40: add r1 = r2 + r3 44: sub r3 = r1 - r0 44: sub r3 = r1 - r0 48: store M[ r3 ] = r1 48: store M[ r3 ] = r1 52: load r2 = M[ 2 ] 52: load r2 = M[ 2 ] 56: PC = 40 56: jump 40

• How long with the program take?

35 36 Conditional Branch Conditional Branch

• Conditional Branch sometimes updates PC • What does this look like in C? • AKA: Branch, Conditional Jump • Example “ ” • Example 10: Hello\n ; data in memory 36: arg1 = 10 ; argument memory address is 10 40: r1 = 10 40: r1 = 10 44: r1 = r1 - 1 44: r1 = r1 - 1 48: branch r1 > 0, 44 if r1 is greater than 0, PC = 44 48: call printf ; printf(arg1) 52: halt 52: branch r1 > 0, 44 56: halt • How long will this program take? Details about red instructions/data next time…

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Indirect Branches Branch Summary

• Reduce, Reuse, Recycle (instructions) • Branch address may also come from a register • Branch instructions update state • AKA: Indirect Jump Registers 0 1 2 3 4 5 6 7 Example: 0000 0788 B700 0010 0401 0002 0003 00A0 PC 8 9 A B C D E F 40: add r1 = r2 + r3 10 0000 0788 B700 0010 0401 0002 0003 00A0 44: sub r3 = r1 - r0 Main Memory 48: store M[ r3 ] = r1 ? 00: 0000 0000 0000 0000 0000 0000 0000 0000 08: 0000 0000 0000 0000 0000 0000 0000 0000 52: load r2 = M[ 2 ] 10: 9222 9120 1121 A120 1121 A121 7211 0000 56: jump r4 18: 0000 0001 0002 0003 0004 0005 0006 0007 20: 0008 0009 000A 000B 000C 000D 000E 000F 60: halt 28: 0000 0000 0000 FE10 FACE CAFE ACED CEDE . . E8: 1234 5678 9ABC DEF0 0000 0000 F00D 0000 F0: 0000 0000 EEEE 1111 EEEE 1111 0000 0000 F8: B1B2 F1F5 0000 0000 0000 0000 0000 0000 39 40 A Note on Notation…

• Assembly syntax is somewhat arbitrary • Equivalent “Add” Instructions • add r1, r2, r3 • add r1 = r2, r3 • r1 = r2 + r3 • add r1 = r2 + r3 • add $1, $2, $3 • … • Equivalent “Store Word” Instructions • sw $1, 10($2) • M[r2 + 10] = r1 • st.w M[r2 + 10] = r1 • …

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Specific Instance: MIPS Instruction Set MIPS Usage in Course

• MIPS – SGI Workstations, Nintendo, Sony… • Used throughout book • We will use it on homework and exams State: • For clarity of lecture, MIPS not always used • 32-bit addresses to memory (32-bit PC) • Refer to book for all instructions discussed • 32 32-bit Registers • A “word” is 32-bits on MIPS • Register $0 ($zero) always has the value 0 • By convention, certain registers are used for certain things – more next time…

43 44 Specific Instance: MIPS Instruction Set Specific Instance: MIPS Instruction Set

Some Arithmetic Instructions: Some Memory Instructions: • Add: • Load Word: • Assembly Format: add , , • Assembly Format: lw , () • Example: add $1, $2, $3 • Example: lw $1, 100 ($2) • Example Meaning: r1 = r2 + r3 • Example Meaning: r1 = M[r2 + 100]

• Subtract: • Store Word: • Same as add, except “sub” instead of “add” • Assembly Format: sw , () • Example: sw $1, 100 ($2) • Example Meaning: M[r2 + 100] = r1

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Specific Instance: MIPS Instruction Set How are MIPS Instructions Encoded?

Some Branch Instructions: • Branch Equal:

• Assembly Format: beq , , Applications • Example: beq $1, $2, 100 Operating System • Example Meaning: branch r1 == r2, 100 If r1 is equal to r2, PC = 100 Compiler Firmware Instruction Set Architecture • Branch Not Equal: Same except beq -> bne Instruction Set Processor I/O System Datapath & Control • Jump: Digital Design • Assembly Format: j Circuit Design • Example: j 100 Layout • Example Meaning: jump 100 PC = 100

47 48 MIPS Encodings MIPS Add Instruction Encoding 32-bits/Instruction add $17, $18, $19 add is an R inst

0 18 19 17 0 32

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MIPS Add Instruction Encoding Add and Subtract A little foreshadowing… sub $17, $18, $19 sub is an R inst add sub

0 18 19 17 0 34

51 52 Memory Addressing

View memory as a single-dimensional array 0 8 bits of data Since 1980: Elements of array are 8-bits 8 bits of data 1 2 8 bits of data We say “byte addressable” 3 8 bits of data Assuming 32-bit words: 8 bits of data 4 1. How are bytes laid out in word read? 5 8 bits of data 6 8 bits of data ... 2. Can a word start at any address?

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Memory Organization Addressing Modes Example Meaning • Bytes are nice, but most data items use larger "words" Register Add R4,R3 R4← R4+R3 • For MIPS, a word is 32 bits or 4 bytes. Immediate Add R4,#3 R4 R4+3 ←

0 32 bits of data Displacement Add R4,100(R1) R4 ← R4+Mem[100+R1]

4 32 bits of data Registers hold 32 bits of data Register indirect Add R4,(R1) R4 ← R4+Mem[R1] 32 bits of data 8 Indexed / Base Add R3,(R1+R2) R3 R3+Mem[R1+R2] 12 32 bits of data ← ... Direct or absolute Add R1,(1001) R1 ← R1+Mem[1001] • 232 bytes with byte addresses from 0 to 232-1 Memory indirect Add R1,@(R3) R1 ← R1+Mem[Mem[R3]] • 230 words with byte addresses 0, 4, 8, ... 232-4 • Words are aligned Auto-increment Add R1,(R2)+ R1 ← R1+Mem[R2]; R2 ← R2+d i.e., what are the least 2 significant bits of a word address? Auto-decrement Add R1,–(R2) R2 ← R2–d; R1 ← R1+Mem[R2]

Scaled Add R1,100(R2)[R3] R1 ← R1+Mem[100+R2+R3*d]

56 Hello World Hello World

The Hello World Algorithm: 1. Emit “Hello World” C Program GNU C Compiler 2. Terminate C Program IA-64

Hello World Interfaces in Computer Systems

IA-64 Assembly Language Software

Applications

Operating System

Compiler Firmware Instruction Set Architecture Instruction Set Processor I/O System Datapath & Control Digital Design Circuit Design Layout Hardware Control The Hardware/Software Interface (from the back of a napkin) Software

Applications

Operating System

Compiler Firmware Instruction Set Architecture Instruction Set Processor I/O System Datapath & Control Digital Design Circuit Design Layout Hardware

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The Instruction Set Architecture Some Figure and Text Acknowledgements

“The vocabulary of commands” • Defined by the Architecture () • Dan Connors • Implemented by the Machine (Pentium 4, 3.06 GHz) • David Patterson • An Abstraction Layer: The Hardware/Software Interface • The COS126 Team (Wayne, Sedgewick) • Architecture has longevity over implementation • A. Mason • Example: • Corporation add r1 = r2 + r3 (assembly) • Amazon.com • www.uiuc.edu 001 001 010 011 (binary)

Opcode (verb) Operands (nouns)