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VAX 6000 Platform Technical User's Guide

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VAX 6000 Platform Technical User's Guide VAX 6000 Platform Technical User’s Guide Order Number: EK–600EA–TM-001 This manual serves as a reference for field-level repair or programming for systems based on the VAX 6000 platform. The manual describes the platform architecture, the XMI system bus, the DWMBB XMI-to-VAXBI adapter, and the power and cooling systems found in the H9657-CA/CB/CU cabinet. Digital Equipment Corporation First Printing, May 1991 The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document. The software, if any, described in this document is furnished under a license and may be used or copied only in accordance with the terms of such license. No responsibility is assumed for the use or reliability of software or equipment that is not supplied by Digital Equipment Corporation or its affiliated companies. Copyright ©1991 by Digital Equipment Corporation All Rights Reserved. Printed in U.S.A. The postpaid READER’S COMMENTS form on the last page of this document requests the user’s critical evaluation to assist in preparing future documentation. The following are trademarks of Digital Equipment Corporation: DEMNA PDP VAXcluster DEC ULTRIX VAXELN DEC LANcontroller UNIBUS VMS DECnet VAX XMI DECUS VAXBI dt This document was prepared using VAX DOCUMENT, Version 1.2 Contents PREFACE xiii CHAPTER 1 THE VAX 6000 PLATFORM OVERVIEW 1–1 1.1 SPECIFICATIONS 1–2 1.2 SYSTEM FRONT VIEW 1–4 1.3 SYSTEM REAR VIEW 1–5 1.4 CONFIGURATIONS 1–6 1.5 XMI BACKPLANE AND CARD CAGE 1–7 1.6 CONSOLE LOAD DEVICE 1–9 1.7 DWMBB I/O ADAPTER 1–10 1.8 I/O CONNECTIONS 1–11 1.9 POWER SYSTEM 1–12 1.10 COOLING SYSTEM 1–14 1.11 OPTIONS 1–15 CHAPTER 2 THE XMI 2–1 2.1 XMI OVERVIEW 2–2 2.1.1 XMI System Block Diagram Description 2–2 iii Contents 2.1.2 XMI Corner 2–4 2.1.3 XMI Data Transactions 2–6 2.1.4 XMI Terms 2–7 2.1.5 Wraparound Reads 2–9 2.1.5.1 Octaword Wraparound Read • 2–9 2.1.5.2 Hexword Wraparound Read • 2–9 2.1.6 XMI Interrupt Transactions 2–10 2.1.7 Arbitration 2–11 2.1.8 Bus Integrity 2–11 2.2 XMI ADDRESSING 2–12 2.2.1 XMI Memory Space 2–13 2.2.2 XMI I/O Space 2–14 2.2.2.1 XMI Private Space • 2–14 2.2.2.2 XMI Nodespace • 2–15 2.2.2.3 I/O Address Space • 2–16 2.2.2.4 VAXBI Adapter I/O Address Space • 2–16 2.2.2.5 How to Find a Register in VAXBI Address Space • 2–17 2.3 ARBITRATION CYCLES 2–20 2.4 XMI CYCLES 2–22 2.4.1 Function Codes 2–22 2.4.2 Command Cycles 2–23 2.4.2.1 Command Field • 2–24 2.4.2.2 Mask Field • 2–25 2.4.2.3 Length Field • 2–26 2.4.2.4 Address Field • 2–26 2.4.2.5 Interrupt Priority Level Field • 2–27 2.4.2.6 Node Specifier Field • 2–28 2.4.3 Write Data Cycles 2–29 2.4.4 Good Read Data (GRD) and Corrected Read Data (CRD) Response Cycles 2–29 2.4.5 Locked Response Cycle (LOC) 2–30 2.4.6 Read Error Response Cycle (RER) 2–30 2.4.7 The Null Cycle 2–30 2.5 XMI TRANSACTIONS 2–31 2.5.1 Memory Block State 2–33 2.5.2 Read Transaction 2–34 2.5.3 Interlock Read Transaction 2–35 2.5.4 Ownership Read Transaction 2–37 2.5.5 Write Mask Transaction 2–38 iv Contents 2.5.6 Unlock Write Mask Transaction 2–40 2.5.7 Disown Write Mask Transactions 2–41 2.5.8 Tag Bad Data Transactions 2–42 2.5.9 Interrupt and Identify Transactions 2–43 2.5.10 Implied Vector Interrupt Transactions 2–45 2.5.11 Transaction Examples 2–46 2.5.11.1 Single Quadword Reads • 2–46 2.5.11.2 Multiple Quadword Reads • 2–48 2.5.11.3 Longword and Quadword Writes • 2–50 2.5.11.4 Multiple Quadword Writes • 2–51 2.6 CACHE COHERENCY 2–52 2.7 XMI INITIALIZATION 2–53 2.7.1 Causes of an Initialization 2–54 2.7.2 Power-Up 2–54 2.7.3 System Reset 2–55 2.7.4 Node Reset 2–55 2.8 XMI REGISTERS 2–56 DEVICE REGISTER (XDEV) 2–57 BUS ERROR REGISTER (XBER) 2–58 FAILING ADDRESS REGISTER (XFADR) 2–66 XMI GENERAL PURPOSE REGISTER (XGPR) 2–68 NODE-SPECIFIC CONTROL AND STATUS REGISTER (NSCSR) 2–69 XMI CONTROL REGISTER (XCR) 2–70 FAILING ADDRESS EXTENSION REGISTER (XFAER) 2–72 BUS ERROR EXTENSION REGISTER (XBEER) 2–74 2.9 XMI ERRORS 2–76 2.9.1 Error Conditions 2–76 2.9.1.1 Parity Error • 2–76 2.9.1.2 Inconsistent Parity Error • 2–76 2.9.1.3 Transaction Timeout • 2–77 2.9.1.4 Sequence Error • 2–77 2.9.2 Error Handling 2–78 2.9.3 Error Recovery 2–79 2.9.4 Error Reporting 2–79 v Contents CHAPTER 3 DWMBB ADAPTER 3–1 3.1 DWMBB OVERVIEW 3–2 3.2 ADDRESS TRANSLATION 3–4 3.2.1 DWMBA Compatibility Mode 3–8 3.2.1.1 DWMBA Compatibility Mode DMA Write Transaction • 3–9 3.2.1.2 DWMBA Compatibility Mode DMA Read Transaction • 3–9 3.2.2 40-Bit VAX Address Translation 3–10 3.2.3 40-Bit Address Translation (4-Kbyte Page Size) 3–11 3.2.4 40-Bit Address Translation (8-Kbyte Page Size) 3–13 3.2.5 DMA Write Transactions—Extended Address Modes 3–15 3.2.6 DMA Read Transactions—Extended Address Modes 3–15 3.3 I/O TRANSACTIONS 3–16 3.3.1 I/O References to DWMBB/A Module Registers 3–16 3.3.2 I/O References to the PMRs 3–17 3.3.3 I/O References to DWMBB/B Module Registers or to VAXBI Registers 3–17 3.4 INTERRUPTS 3–18 3.4.1 DWMBB-Detected Error Interrupt Vectors 3–21 3.4.2 VAXBI Node Vector 3–21 3.4.3 Interprocessor Interrupts 3–23 3.4.4 Interrupt Transactions 3–23 3.4.4.1 DWMBB Adapter-Generated Interrupts • 3–23 3.4.4.2 VAXBI-Generated Interrupts • 3–23 3.4.4.3 BIIC-Generated VAXBI Interrupts • 3–23 3.4.4.4 Interprocessor-Generated VAXBI Interrupts • 3–24 3.4.4.5 Passive Release of VAXBI Interrupts • 3–24 3.4.5 IDENT Transactions 3–24 3.4.6 Return Vector Disable Option 3–24 3.4.7 IVINTR Transactions 3–25 3.5 VAXBI WRAPPED READ TRANSACTIONS 3–26 3.6 LOCKOUT MODES 3–28 3.6.1 No Assertion and No Response to XMI Lockout Mode 3–29 3.6.2 Respond to XMI Lockout Mode 3–29 3.6.3 Assert XMI Lockout Mode 3–29 vi Contents 3.6.4 Full XMI Lockout Mode 3–30 3.6.5 Programmable Lockout Limit 3–31 3.6.6 Lockout Deassertion Timer 3–32 3.7 COMMANDER ARBITRATION USING RESPONDER REQUEST 3–33 3.8 PROGRAMMABLE TIMEOUTS 3–34 3.9 PROGRAMMABLE VAXBI I/O WINDOW SPACE 3–36 3.10 ECC PROTECTION ON THE PMR DATA PATH 3–37 3.10.1 ECC Errors Detected During I/O PMR Read Accesses 3–38 3.10.2 ECC Errors Detected During PMR Accesses for DMA Address Translation 3–38 3.11 DWMBB ADAPTER REGISTERS 3–39 DEVICE REGISTER (XDEV) 3–43 BUS ERROR REGISTER (XBER) 3–45 FAILING ADDRESS REGISTER (XFADR) 3–53 RESPONDER ERROR ADDRESS REGISTER (AREAR) 3–54 ERROR SUMMARY REGISTER (AESR) 3–56 INTERRUPT MASK REGISTER (AIMR) 3–64 IMPLIED VECTOR INTERRUPT DESTINATION/DIAGNOSTIC REGISTER (AIVINTR) 3–72 DIAGNOSTIC 1 REGISTER (ADG1) 3–74 UTILITY REGISTER (AUTLR) 3–81 CONTROL AND STATUS REGISTER (ACSR) 3–86 RETURN VECTOR REGISTER (ARVR) 3–91 FAILING ADDRESS EXTENSION REGISTER (XFAER) 3–92 VAXBI ERROR ADDRESS REGISTER (ABEAR) 3–94 PAGE MAP REGISTERS (PMRS) 3–96 CONTROL AND STATUS REGISTER (BCSR) 3–98 ERROR SUMMARY REGISTER (BESR) 3–100 INTERRUPT DESTINATION REGISTER (BIDR) 3–105 TIMEOUT ADDRESS REGISTER (BTIM) 3–106 VECTOR OFFSET REGISTER (BVOR) 3–107 VECTOR REGISTER (BVR) 3–108 DIAGNOSTIC CONTROL REGISTER 1 (BDCR1) 3–109 RESERVED REGISTER (BRSVD) 3–111 DEVICE REGISTER (DTYPE) 3–112 3.12 ERROR HANDLING 3–113 3.12.1 Error Interrupts 3–114 3.12.2 Error Command and Address Logging 3–114 vii Contents 3.12.3 Multiple Errors 3–115 3.12.4 Address Translation Mode Errors 3–115 3.12.4.1 Invalid VAXBI Address • 3–116 3.12.4.2 Invalid PFN • 3–116 3.12.4.3 ECC Errors on PMR Data During DMA Address Translation • 3–117 3.12.4.3.1 Uncorrectable ECC Errors • 3–117 3.12.4.3.2 Correctable ECC Errors • 3–117 3.12.4.4 ECC Errors on PMR Data During I/O Reads to PMR • 3–118 3.12.4.4.1 Uncorrectable ECC Errors • 3–118 3.12.4.4.2 Correctable ECC Errors • 3–118 3.12.5 IBUS Parity Errors 3–119 3.12.5.1 DMA Write C/A or INTR C/A IBUS Parity Error • 3–119 3.12.5.2 DMA Write Data IBUS Parity Error • 3–119 3.12.5.3 DMA Read C/A IBUS Parity Error • 3–120 3.12.5.4 I/O Read Data or IDENT Vector IBUS Parity Error • 3–120 3.12.5.5 DMA Read Data IBUS Parity Error • 3–120 3.12.5.6 I/O Write C/A IBUS Parity Error • 3–121 3.12.5.7 I/O Write Data IBUS Parity Error • 3–121 3.12.5.8 I/O Read C/A IBUS Parity Error • 3–121 3.12.5.9 IDENT IBUS Parity Error • 3–122 3.12.5.10 Undecodable I/O C/A with no IBUS Parity Error Detected • 3–122 3.12.5.11 Undecodable DMA C/A with no IBUS Parity Error Detected • 3–123 3.12.5.12 Undecodable DMA C/A with an IBUS Parity Error Detected • 3–123 3.12.6 XMI Errors 3–124 3.12.6.1 DMA Write C/A XMI Error • 3–125 3.12.6.2 DMA Read C/A XMI Error • 3–125 3.12.6.3 DMA Write Data XMI Error • 3–125 3.12.6.4 DMA Read Data XMI Error • 3–125 3.12.6.5 Parity Errors on the XMI • 3–126 3.12.6.6 I/O Read Data and IDENT Vector Errors on the XMI • 3–126 3.12.6.7 I/O Write Data Error on the XMI • 3–126 3.12.6.8 LOC Response on DMA Read Data • 3–126 3.12.7 VAXBI Errors 3–127 3.12.8 Miscellaneous Errors 3–128 3.12.8.1 Impending Power Fail • 3–128 3.12.8.2 Internal Errors • 3–128 3.12.8.3 PMR Initialization Inhibit Error • 3–128 3.12.8.4 DMA Read Data Parity Error during DWMBB/A Module Loopback • 3–129 3.12.8.5 Cable OK Error • 3–129 3.13 DWMBB INITIALIZATION 3–130 3.13.1 DWMBB/A Module Initialization Sequence 3–131 3.13.2 DWMBB/A Module Gate Array Control Reset 3–131 viii Contents 3.13.3 DWMBB/B Module Initialization Sequence 3–132 3.14 DIAGNOSTIC FEATURES 3–133 3.14.1 Internal Loopback Modes 3–134 3.14.1.1 DWMBB/A Module Loopback • 3–134 3.14.1.2 BIIC Loopback • 3–135 3.14.1.3 DMA Loopback • 3–136 3.14.2 DWMBB/A Module Gate Array Transaction Register Files Testing 3–137 3.14.2.1 Executing DMA Writes and Reads in Loopback Mode • 3–141 3.14.2.2 Transaction Register File in
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