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Digital Technical Journal, Number 7, August 1988: CVAX-Based Systems

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Digital Technical Journal, Number 7, August 1988: CVAX-Based Systems CVAX-based Systems Digital Technical Journal Digital Equipment Corporation umhcr 7 August I9R8 Managing Editor Richard W Beane Editor jane C. Blake Production Staff Produnion Editor- Helen L. Paucrson Designer- Charlo!!<: Bell Typographers- Jonathan !\·f. Uohy Margart:t Burdine lllustrawr- Dt:borah Keeley Advisory Board Samuel H. Fuller, Chairman Robert M. Glorioso John W McCredie Mahendra R. Patel F. Grant Saviers William D. Strecker Victor A. Vyssotsky The Digital Tecbnical jnumal is published by Digital Equipmt:nt Corporation. 77 Reed Road. Hudson. Massachuscus 01749. Changes of address should be sent to Digital E quipment Corporation. aut:ntion: List Maintenance. I 0 Forbes Road. Northboro. MA 015j2. Please includt: the address label with changes marked. Comments on the content of any paper are wclcomt:d. Write to the editor at Mail Stop 1-lLOl-.�/Kil at the published-by address. Comments can also be sent on the ENET to RDV�'X::OIAKE or on the ARPANET to BLA.K.E'X,RDVAX. DEC�)l)ECWRL. Copyright © 1988 Digital Equ ipment Corporation. Copying without fee is permiued providt:d that such copies are made for use in t:duc:uional institmions by faculty members and arc not distributed for commercial advamage. Abstracting with credit of Digital Equipment Corporation's authorship is pcrmiued. Requests for other copies for a fee may be made 10 Digital Press of Digital Equipmem Corporation. All rights reserved. The information in this journal is subject to change without notice and should not be construed as a com­ miunem by Digital E quipment Corporation. Digital Equipment Corporation assumt:s no responsibility for any errors that may appear in this document. lSSN 0898-901 X Documentation Number EY-67•i2E-DI' The following are trademarks of Digital Equipment Corporation: ALL-IN- I. DEQNA. HSC70. J-1 l. MicroVAX, MicroVAX 11, MicroVAX .�000. N•'-'11. NOTES. Q-bus, Q22-bus, RA81. RA82, RD54. RQDX3. RX50. TK50. UITRIX-.�2. VAX. VAX-11/780. VAX-11/782. VAX 6200. Cover Design VAX 6210, V�'( 6220. V�'( 62.10. VAX 6240. VAX 8200, .S)'stems based un Digital's aduanced CMUS technology are V�'( 8300. VAX 8650. VAX flf!OO. VAX HH40. VAXlll, featured in Ibis issue. Tbe graphic on our COI'er includes the VAXELN. V�'( MACRO, V�X SI'M. VAX/VMS. VMS. lattice structure of the silicon nystal. a basic element of Compu-Sharc is a trademark of Compu-Shart:. Inc. this tecbnology. The expansion of the image expresses the GDS 11 is a trademark of Calma Corporation. pe1j'ormance growth and the system e.Yiensibility of the new SPICE is a trademark of the University of California at CVAX-based systenH. lkrkdey Tektronix and DAS arc trademarks of Tt:ktronix. Inc. The COI'er was designed by Barbara Grzeslo and]acquie !look production was done by Digital's Educnional Hockaday 1�[ the Graphic Design Department. Services Media Communicnions Group in Bedford. \·lA. Contents 8 Fo reword Robert M. Supnik CV AX-based Systems 1 0 An Overview of the VA X 6200 Fa mily of Systems Brian R. Allison 19 TheAr chitectural Definition Process of the VAX 6200 Fa mily Brian R. All ison 28 Interfacing a VA X Microprocessor to a High-speed Multiprocessing Bus Richard B. GiUett, Jr. 4 7 The Role of Computer-aided Engineering in the Design of the VAX 6200 System Jean H. Basmaji, Glenn P. Garvey, Masood Heydari , and Arthur L. Singer 57 VMS Symmetric Multiprocessing Rodney N. Gamache and Kathleen D. Morse 64 Performance Evaluation of the VAX 6200 Systems Bhagyam Moses and Karen T. DeGregory 79 Overview of the MicroVAX 3500/3600 Processor Module Gary P Lidington 87 Design of the MicroVAX 3500/3600 Second-level Cache Charles]. DeVane 95 The CVAX 78034 Chip, a 32-bit Second-generation VA X Microprocessor Thomas F. Fox, Paul E. Gronowski, Ani! K. Jain, Burton M. Leary, and Daniel G. Miner 1 09 Development of the CVAX Flo ating Point Chip Edward J. McLellan, Gilbert M. Wolrich, and Robert AJ Yod lowski 121 The System Support Chip, a Multifunction Chip for CVAX Systems Jeff Winston 129 Development of the CVAX Q22-bus Interface Chip Barry A. Maskas 139 The CVAX CMCTL -A CMOS Memory Controller Chip David K. Morgan Editor�s Introduction In the last paper related ro the VAX 6200 system, Bhttgyam Moses and Karen DeGregory describe the development of workloads to measure VAX 6240 performance. As part of their discussion, they include performance measurements and analysis. The second new system based on the CVAX chip set is the low-end MicroVAX -�500/3600 system, which offers three times the performance of irs predecessor, the MicroVAX II. In his over­ view of the major sections of the processor mod­ ule, Gary Lidington relates how schedule and performance requirements influenced product Jane C. Blake design decisions. Editor Charles DeVane then describes the MicroVAX .3500/3600 system's rwo-level cache architecture, The second issue of the Digital Technical journal with emphasis on the design of the second-level (March I 986) fearured papers on the then cache. He also presents some cache performance recently announced MicroVAX II system, a system rest results. based on a single-chip VA.'{ implementation. In The high performance of both the VAX 6200 this seventh issue, we present papers on the sec­ family and the MicroVAX 3500/3600 system is ond generation of that chip set, CVA.'\, the two attributable in great measure tO the CMOS VAX new systems that take advantage of its increased family of chips on which these systems are based. performance capabilities, and a new version of Our five final papers address the design and the VAXfVMS operating system for symmetric development of this chip set. Frank Fox, Paul multiprocessing. Gronowski, Ani! Jain, Mike Leary, and Dan Miner The new mid-range system based on the CVAX begin the discussion with an explanation of how chip set is the VAX 6200 family of compUlers, designers achieved the performance goals for the which utilizes a multiprocessing architecture. single-chip VAX CPU by reducing ticks per The first of rwo papers by Brian Allison is an instruction and machine cycle time. overview of this highly configurable, expandable A companion ro the CVAX CPU, the floating system. Brian's second paper offers insights into point processor chip offers floating point perfor­ the architectural definition process for the 6200. mance equal ro that of the microprocessor for One of the major decisions made by the 6200 integer operations. The approach taken tO attain engineers was to design a new interconnect to this goal and a description of the chip are pre­ support the multiprocessor system. Rick Gillett sented by Ed McLellan, Gil Wolrich, and Bob presents an informative discussion of the com­ Yodlowski. plexities involved in interfacing a microprocessor Jeff Winston then discusses the development of ro a high-speed, multiprocessing bus. the system support chip, which provides a com­ To ensure the availabiliry of first-pass func­ mon core of peripheral system functions. tional parts, a design verification team of engi­ Next, Barry Maskas relates the design effortS of neers worked in parallel with the 6200 module three groups, one in Japan and two in the U.S., designers. Jean Basmaji, Glenn Garvey, Masood that resulted in a single-chip interface between Heydari, and Art Singer discuss the computer­ the CVAX microprocessor and the Q22-bus l/0 aided engineering and verification principles the subsystem. team instituted for the project. ln our final paper, Dave Morgan describes the Rod Gamache and Kathy Morse then describe CVAX memory controller chip, CMCTL, which is the major features of symmetric multiprocessing optimized for Q-bus-based systems. in the VAXjVMS operating system. Of particular interest is their description of a new synchroniza­ tion method implemented in VAXjVMS version 5.0. 2 Biographies Brian R. Allison Brian AJlison, a consultant engineer for mid-range VAX systems, was the system architect responsible for the coordination of the VAX 6200 system definition and design. Prior tO this work, he served as system architect for a project that yielded several products. including DEBNA, DEBNK, and the KA800. As a member of the VAX-11 /750 design team, he wrote various portions of the microcode for that product. Brian holds a BS.E.E. and a B.S.C.S. from Worcester Polytechnic Institute ( 1977). jean H. Basmaji jean Basmaji is the technical director of computer-aided engineering and design-verification testing for the VAX 6200 project. A soft­ ware consultant engineer, he has also been involved with CAE/DVT planning and scheduling, and has served as CAE/DVT project leader for the VAX 6200 CPU module. jean joined Digital after receiving his B.S.E.E. from Lowell Technological Institute in 1977. Karen T. DeGregory A senior software engineer in the Systems Perfor­ mance Analysis Group, Karen DeGregory is project leader of systems perfor­ mance measurement for the VAX 8840 and VAX 6240 systems. In addition to planning and implementing the measurements, she helped develop appro­ priate workloads for these systems. Prior to this work, Karen was a senior software specialist in the Software Services Backup Support Group. She received her B.S. ( 1980) with honors and distinction and her M.S. ( 1981) from Cornell University. Charles J. DeVane Charles DeVane is a senior hardware engineer in the MicroVAX Systems Development Group. For the MicroVA.-'( 3500/3600 pro­ ject, he designed the second-level cache on the KA650 CPU module and guided the process of module system debug and introduction tO manufactur­ ing. Before joining Digital in 1981, Charles received a B.S. E. E. from North Carolina State University in Raleigh, North Carolina.
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