KA680 CPU Module Technical Manual
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KA680 CPU Module Technical Manual Order Number: EK-KA680-TM-001 First Edition, December 1991 The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document. The software described in this document is furnished under a license and may be used or copied only in accordance with the terms of such license. No responsibility is assumed for the use or reliability of software on equipment that is not supplied by Digital Equipment Corporation or its affiliated companies. © Digital Equipment Corporation 1991. All Rights Reserved. The postpaid Reader’s Comments forms at the end of this document request your critical evaluation to assist in preparing future documentation. The following are trademarks of Digital Equipment Corporation: DEC, DECnet, DEQNA, DSSI, LPV11–SA, MicroVAX, PDP, Q–bus, Q22–bus, RRD50, RSTS, ThinWire, ULTRIX, UNIBUS, VAX, VAXELN, VAXstation, VMS, VT, and the Digital logo. This document was prepared using VAX DOCUMENT, Version 2.0. Contents Preface . xxiii 1 Overview 1.1 Introduction . 1–1 1.2 KA680 CPU Module . 1–2 1.2.1 The Central Processing Subsystem . 1–4 1.2.1.1 The NVAX Central Processing Unit (DC246) . 1–4 1.2.1.2 The Cache Memory . 1–5 1.2.2 The System Support Subsystem . 1–5 1.2.2.1 The System Support Chip [SSC (DC511)] . 1–5 1.2.2.2 The Firmware ROMs . 1–6 1.2.2.3 The Boot and Diagnostic Register . 1–6 1.2.2.4 The Station Address ROM . 1–6 1.2.3 The I/O Subsystem . 1–6 1.2.3.1 NVAX CP-bus Bus Adapter [NCA (DC243)] . 1–6 1.2.3.1.1 DSSI Mass Storage Interface [SHAC (DC542)] . 1–7 1.2.3.1.2 Ethernet Interface [SGEC (DC541)] . 1–7 1.2.3.1.3 Q22–bus Interface [CQBIC (DC527)] . 1–7 1.2.4 The Memory Control Subsystem . 1–7 1.2.4.1 NVAX Memory Controller [NMC (DC244)] . 1–8 1.3 MS690 Memory Module . 1–8 1.4 H3604 Console Module . 1–8 2 Installation and Configuration 2.1 Installing the KA680 and MS690 Memory Modules . 2–1 2.2 Module Configuration and Naming . 2–2 2.3 Mass Storage Configuration . 2–3 2.3.1 Changing the Node Name . 2–4 2.3.2 Changing the DSSI Unit Number . 2–5 2.3.3 Accessing RF-series Firmware in VMS Through DUP . 2–6 2.3.3.1 Allocation Class . 2–6 2.4 DSSI Cabling, Device Identity, and Bus Termination . 2–7 2.5 KA680 Connectors . 2–7 3 Central Processor 3.1 Processor State . 3–1 3.1.1 General-Purpose Registers . 3–1 3.1.2 Processor Status Longword . 3–2 3.1.3 Internal Processor Registers . 3–3 3.2 Process Structure . 3–23 3.3 Data Types . 3–23 iii 3.4 Instruction Set . 3–23 3.5 Memory Management . 3–24 3.5.1 Translation Buffer . 3–24 3.5.2 30-bit to 32-bit Physical Address Translations . 3–26 3.5.3 Memory Management Control Registers . 3–28 3.6 Interrupts and Exceptions . 3–29 3.6.1 Interrupts . 3–29 3.6.1.1 Power Fail Interrupt . 3–33 3.6.1.2 Hard Error Interrupts . 3–34 3.6.1.3 Soft Error Interrupts . 3–34 3.7 Exceptions . 3–34 3.7.1 Arithmetic Exceptions . 3–35 3.7.2 Memory Management Exceptions . 3–36 3.7.3 Emulated Instruction Exceptions . 3–37 3.7.4 Vector Unit Disabled Fault . 3–39 3.7.5 Machine Check Exceptions . 3–39 3.7.6 Console Halts . 3–40 3.7.7 Kernel Stack Not Valid Exception . 3–41 3.8 System Control Block (SCB) . 3–41 3.9 System Identification . 3–44 3.9.1 System Identification Register . 3–44 3.9.2 System Identification Extension (SIE) Register (20040004) . 3–45 3.10 CPU References . 3–46 3.10.1 Instruction-Stream Read References . 3–46 3.10.2 Ownership Read References . 3–47 3.10.3 Disown Write References . 3–48 3.10.4 Data-Stream Read References . 3–48 3.10.5 Write References . 3–48 3.11 NVAX Data/Address Lines (NDAL) . 3–48 3.11.1 NDAL Transactions . 3–48 3.11.1.1 Reads and Fills . 3–51 3.11.1.1.1 D-stream Read Requests (DREAD) . 3–51 3.11.1.1.2 I-stream Read Requests (IREAD) . 3–51 3.11.1.1.3 Ownership Read Requests (OREAD) . 3–51 3.11.1.1.4 Read Data Return Cycles (RDR0, RDR1, RDR2, RDR3) . 3–52 3.11.1.1.5 Read Data Error Cycles (RDE) . 3–52 3.11.1.2 Writes . 3–52 3.11.1.2.1 Normal Write Transactions (WRITE) . 3–52 3.11.1.2.2 Disown Write Transactions (WDISOWN) . 3–53 3.11.1.2.3 Write Data and Bad Write Data (WDATA,BADWDATA) . 3–53 3.11.2 Cache Coherency . 3–53 3.11.3 VAX Architecturally-defined Interlocks . 3–55 3.11.3.1 Ownership and Interlock Transactions . 3–55 3.11.4 Errors . 3–55 3.11.4.1 Transaction Timeout . 3–55 3.11.4.2 Nonexistent Memory and I/O . 3–55 iv 4 KA680 Cache Memory Overview 4.1 Cacheable References . 4–2 4.2 Virtual Instruction Cache . 4–2 4.2.1 Virtual Instruction Cache Organization . 4–3 4.2.2 Virtual Instruction Cache Internal Processor Registers . 4–4 4.2.2.1 VIC Virtual Memory Address Register (VMAR) - IPR 208 . 4–4 4.2.2.2 VIC TAG Register (VTAG) - IPR 209 . 4–5 4.2.2.3 VIC Data Register (VDATA) - IPR 210 . 4–6 4.2.2.4 VIC Control and Status Register (ICSR) - IPR 211 . 4–7 4.3 Primary Cache . 4–8 4.3.1 Primary Cache Organization . 4–8 4.3.2 Pcache Control . 4–9 4.3.3 Pcache Hit/Miss Determination . 4–12 4.3.3.1 Hit/Miss Determination.