Digital Technical Journal, Volume 2, Number 4, 1990: VAX 9000 Seies
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Engineering Specification for the KA43 Processor Module Revision 1.0 1–May–1989 COMPANY CONFIDENTIAL RESTRICTED DISTRIBUTION
Engineering Specification for the KA43 Processor Module Revision 1.0 1–May–1989 COMPANY CONFIDENTIAL RESTRICTED DISTRIBUTION COPYRIGHT (c) 1989 by DIGITAL EQUIPMENT CORPORATION This information shall not be disclosed to non-Digital personnel or generally distributed within Digital. Distribution is restricted to persons authorized and designated by the responsible en- gineer or manager. This document shall not be left unattended, and when not in use shall be stored in a locked storage container. The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may occur in this document. The information in this document does not describe any program or product currently available from Digital Equipment Corporation. Nor does Digital Equipment Corporation commit to imple- ment this specification in any program or product. Digital Equipment Corporation makes no commitment that this document accurately describes any product which it might ever make. Digital Equipment Corporation CONTENTS Preface . ........................................................... v Chapter 1 INTRODUCTION .............................................. 1 1.1 Scope of Document ................................................... 1 1.2 General Description .................................................. 1 1.3 Applicable Documents ................................................. 2 Chapter 2 KA43 ROM MEMORY ........................................ -
Chapter 3: Combinational Logic Design
Chapter 3: Combinational Logic Design 1 Introduction • We have learned all the prerequisite material: – Truth tables and Boolean expressions describe functions – Expressions can be converted into hardware circuits – Boolean algebra and K-maps help simplify expressions and circuits • Now, let us put all of these foundations to good use, to analyze and design some larger circuits 2 Introduction • Logic circuits for digital systems may be – Combinational – Sequential • A combinational circuit consists of logic gates whose outputs at any time are determined by the current input values, i.e., it has no memory elements • A sequential circuit consists of logic gates whose outputs at any time are determined by the current input values as well as the past input values, i.e., it has memory elements 3 Introduction • Each input and output variable is a binary variable • 2^n possible binary input combinations • One possible binary value at the output for each input combination • A truth table or m Boolean functions can be used to specify input-output relation 4 Design Hierarchy • A single very large-scale integrated (VLSI) processos circuit contains several tens of millions of gates! • Imagine interconnecting these gates to form the processor • No complex circuit can be designed simply by interconnecting gates one at a time • Divide and Conquer approach is used to deal with the complexity – Break up the circuit into pieces (blocks) – Define the functions and the interfaces of each block such that the circuit formed by interconnecting the blocks obeys the original circuit specification – If a block is still too large and complex to be designed as a single entity, it can be broken into smaller blocks 5 Divide and Conquer 6 Hierarchical Design due to Divide and Conquer 7 Hierarchical Design • A hierarchy reduce the complexity required to represent the schematic diagram of a circuit • In any hierarchy, the leaves consist of predefined blocks, some of which may be primitives. -
Macwise Version 19 User's Manual
[email protected] www.CarnationSoftware.com www.MacWise.com MacWise Version 19 User's Manual You can use Command F to find what you are looking for in this document. Introduction Terminal Emulation MacWise emulates ADDS Viewpoint, Wyse 50, Wyse 60, Wyse 370, Televideo TV 925, DEC VT100, VT220 and Prism terminals. Supports ANSI color. Esprit III color is also supported in Wyse 370 mode. MacWise allows a Macintosh to be used as a terminal -- connected to a host computer directly, by modem, or over the Internet. The emulators support video attributes such as dim, reverse, underline, 132-column modes, protected fields and graphic characters sent from the host computer, as well as enhanced Viewpoint mode. Features include phone list and dialer for modems, on-screen programmable function keys, connection scripts and more. Connectivity 1. Built in Modem 2. Telnet / TCP/IP 3. SSH Secure Shell 4. Serial ports via USB to Serial adaptor . 5. Also communicates directly with the Mac unix shell Telnet Telnet settings are under the Connection Menu. Select "Telnet" to enable telnet. Select "Telnet Connection..." to enter your Host IP address, port number and terminal type. =============================== KERMIT ================================ NOTE: If you are running Mac OS 10.13 or later, you need to also use Kermit. (There should be a check mark on "Kermit" under the Connection Menu.) Kermit is installed automatically when Mac OS 10.13 or later is detected. You can re-install kermit any time by selecting Kermit Installer from the Help Menu in MacWise. Echo Kermit Characters ( under the Connection Menu ) This is normally enabled when Kermit is enabled. -
Next Generation Tool
INSIDE! COMPUTING TRENDS: WHAT ARE TODAY'S CIO'S LOOKING FOR? $7.00 U.S. INTERNATIONAL ® SPECTRUMSPECTRUMTHE BUSINESS COMPUTER MAGAZINE SEPT/OCT 2002 • AN IDBMA, INC. PUBLICATION NextNext GenerationGeneration ToolTool XXCreateCreate OneOne CodeCode BaseBase forfor AnyAny NetworkNetwork Configuration,Configuration, AnyAny OperatingOperatingTT System,System, andand AnyAny DataData SourceSource —— MultiValueMultiValue andand RelationalRelational —— WithoutWithoutTT BeingBeing aa JavaJava Expert!Expert! Come in from the rain Featuring the UniVision MultiValue database - compatible with existing applications running on Pick AP, D3, R83, General Automation, Mentor, mvBase and Ultimate. We’re off to see the WebWizard Starring a “host” centric web integration solution. Watch WebWizard create sophisticated web-based applications from your existing computing environment. Why a duck? Featuring ViaDuct 2000, the world’s easiest-to-use terminal emulation and connectivity software, designed to integrate your host data and applications with your Windows desktop. Caught in the middle? With an all-star cast from the WinLink32 product family (ViaOD- BC, ViaAPI for Visual Basic, ViaObjects, and mvControls), Via Sys- tems’ middleware solutions will entertain (and enrich!) you. Appearing soon on a screen near you. Advanced previews available from Via Systems. Via Systems Inc. 660 Southpointe Court, Suite 300 Colorado Springs, Colorado 80906 Phone: 888 TEAMVIA Fax: 719-576-7246 e-mail: [email protected] On the web: www.via.com The Freedom To Soar. With jBASE – the remarkably liberating multidimensional database – there are no limits to where you can go. Your world class applications can now run on your choice of database: jBASE, Oracle, SQL Server or DB2 without modification and can easily share data with other applications using those databases. -
The Von Neumann Computer Model 5/30/17, 10:03 PM
The von Neumann Computer Model 5/30/17, 10:03 PM CIS-77 Home http://www.c-jump.com/CIS77/CIS77syllabus.htm The von Neumann Computer Model 1. The von Neumann Computer Model 2. Components of the Von Neumann Model 3. Communication Between Memory and Processing Unit 4. CPU data-path 5. Memory Operations 6. Understanding the MAR and the MDR 7. Understanding the MAR and the MDR, Cont. 8. ALU, the Processing Unit 9. ALU and the Word Length 10. Control Unit 11. Control Unit, Cont. 12. Input/Output 13. Input/Output Ports 14. Input/Output Address Space 15. Console Input/Output in Protected Memory Mode 16. Instruction Processing 17. Instruction Components 18. Why Learn Intel x86 ISA ? 19. Design of the x86 CPU Instruction Set 20. CPU Instruction Set 21. History of IBM PC 22. Early x86 Processor Family 23. 8086 and 8088 CPU 24. 80186 CPU 25. 80286 CPU 26. 80386 CPU 27. 80386 CPU, Cont. 28. 80486 CPU 29. Pentium (Intel 80586) 30. Pentium Pro 31. Pentium II 32. Itanium processor 1. The von Neumann Computer Model Von Neumann computer systems contain three main building blocks: The following block diagram shows major relationship between CPU components: the central processing unit (CPU), memory, and input/output devices (I/O). These three components are connected together using the system bus. The most prominent items within the CPU are the registers: they can be manipulated directly by a computer program. http://www.c-jump.com/CIS77/CPU/VonNeumann/lecture.html Page 1 of 15 IPR2017-01532 FanDuel, et al. -
Combinational Logic; Hierarchical Design and Analysis
Combinational Logic; Hierarchical Design and Analysis Tom Kelliher, CS 240 Feb. 10, 2012 1 Administrivia Announcements Collect assignment. Assignment Read 3.3. From Last Time IC technology. Outline 1. Combinational logic. 2. Hierarchical design 3. Design analysis. 1 Coming Up Design example. 2 Combinational Logic 1. Definition: Logic circuits in which the output(s) depend solely upon current inputs. 2. No feedback or memory. 3. Sequential circuits: outputs depend upon current inputs and previous inputs. Memory or registers. 4. Example — BCD to 7-segment decoder: S0 D0 S1 D1 BCD - 7 Seg S2 D2 S3 D3 Decoder S4 S5 S6 3 Hierarchical Design 1. Transistor counts: 2 Processor Year Transistor Count TI SN7400 1966 16 Intel 4004 1971 2,300 Intel 8085 1976 6,500 Intel 8088 1979 29,000 Intel 80386 1985 275,000 Intel Pentium 1993 3,100,000 Intel Pentium 4 2000 42,000,000 AMD Athlon 64 2003 105,900,000 Intel Core 2 Duo 2006 291,000,000 Intel Core 2 Quad 2006 582,000,000 NVIDIA G80 2006 681,000,000 Intel Dual Core Itanium 2 2006 1,700,000,000 Intel Atom 2008 42,000,000 Six Core Xeon 7400 2008 1,900,000,000 AMD RV770 2008 956,000,000 NVIDIA GT200 2008 1,400,000,000 Eight Core Xeon Nehalem-EX 2010 2,300,000,000 10 Core Xeon Westmere-EX 2011 2,600,000,000 AMD Cayman 2010 2,640,000,000 NVIDIA GF100 2010 3,000,000,000 Altera Stratix V 2011 3,800,000,000 2. Design and conquer: CPU ⇒ Integer Unit ⇒ Adder ⇒ binary full adder ⇒ NAND gates 3. -
A Kermit File Transfer Protocol for the Apple II Series Personal Computers : John Patrick Francisco Lehigh University
Lehigh University Lehigh Preserve Theses and Dissertations 1986 A Kermit file transfer protocol for the Apple II series personal computers : John Patrick Francisco Lehigh University Follow this and additional works at: https://preserve.lehigh.edu/etd Part of the Electrical and Computer Engineering Commons Recommended Citation Francisco, John Patrick, "A Kermit file transfer protocol for the Apple II series personal computers :" (1986). Theses and Dissertations. 4628. https://preserve.lehigh.edu/etd/4628 This Thesis is brought to you for free and open access by Lehigh Preserve. It has been accepted for inclusion in Theses and Dissertations by an authorized administrator of Lehigh Preserve. For more information, please contact [email protected]. A KERMIT FILE TRANSFER PROTOCOL FOR THE APPLE II SERIES PERSONAL COMPUTERS (Using the Apple Pascal Operating system) by John Patrick Francisco A Thesis Presented to the Graduate Committee of Lehigh University in Candidacy for the Degree of Master of Science 1n• Computer Science Lehigh University March 1986 This thesis is accepted and approved in partial fulfillment of the requirements for the degree of Master of science.• (date) Professor in Charge -------------- --------------- Chairman of the Division Chairman of the Department • • -11- ACKNOWLEDGEMENTS It would be somewhat of an understatement to say this project was broad in scope as the disciplines involved ranged from Phychology to Electrical Engineering. Since the project required an extensive amount of detailed in formation in all fields, I was impelled to seek the help, advice and opinion of many. There were also numerous t friends and relatives upon whom I relied for both moral and financial support. -
(12) United States Patent (10) Patent No.: US 6,340,897 B1 Lytle Et Al
USOO6340897B1 (12) United States Patent (10) Patent No.: US 6,340,897 B1 Lytle et al. (45) Date of Patent: *Jan. 22, 2002 (54) PROGRAMMABLE LOGICARRAY FOREIGN PATENT DOCUMENTS INTEGRATED CIRCUIT WITH GENERAL EP OO81917 8/1983 PURPOSE MEMORY CONFIGURABLE ASA EP O410759 A2 1/1991 RANDOM ACCESS OR FIFO MEMORY EP O415542 A2 3/1991 (75) Inventors: Craig S. Lytle, Mountain View; (List continued on next page.) Donald F. Faria, San Jose, both of CA (US) OTHER PUBLICATIONS Matsumoto, Rodney T., “Configurable On-Chip RAM (73) ASSignee: Altera Corporation, San Jose, CA Incorporated into Hign Speed Logic Array," IEEE Custom (US) Integrated Circuits Conference, Jun. 1985, CH2157–6/85/ (*) Notice: Subject to any disclaimer, the term of this 0000–0240, pp. 240–243. patent is extended or adjusted under 35 Landry, Steve, “Application-Specific ICs, Relying on RAM, U.S.C. 154(b) by 0 days. Implement Almost Any Logic Function,” Electronic Design, Oct. 31, 1985, pp. 123–130. This patent is Subject to a terminal dis Bursky, Dave, “Shrink Systems with One-Chip Decoder, claimer. EPROM, and RAM,” Electronic Design, Jul. 28, 1988, pp. 91-94. (21) Appl. No.: 09/481,781 Kawana, Keiichi et al., “An Efficient Logic Block Intercon nect Architecture for User-Reprogrammable Gate Array,” (22) Filed: Jan. 11, 2000 IEEE 1990 Custom Integrated Circuits Conference, May Related U.S. Application Data 1990, CH2860–5/90/0000–0164, pp. 31.3.1-4 (List continued on next page.) (63) Continuation of application No. 08/707,705, filed on Jul. 24, 1996, now Pat. No. 6,049,223, which is a continuation-in Primary Examiner Michael Tokar part of application No. -
LABORATORY for COMPUTER SCIENCE'progress REPORT Ig JULY 1/3 1986-JUNE 1981(U) MASSACHUSETTS INST of TECH CAMBRIDGE LAB for COMPUTER SCIENCE
-R127 586 LABORATORY FOR COMPUTER SCIENCE'PROGRESS REPORT ig JULY 1/3 1986-JUNE 1981(U) MASSACHUSETTS INST OF TECH CAMBRIDGE LAB FOR COMPUTER SCIENCE. M L DERTOUZOS 01 APR 82 UNCLASSIFIEDEhE0 LCS-PR-i8 00 N9014-75-C-8661 0 0 0 1iEF/G 9/2 N EhhhhhhhhhhhhE EhhhhhhhhhhhhE EhhhhhhhmhhhhE EhhhhhhhhhhhhI EhhhhhhohmhhhE ".2 111.0 t IL8125 IL .2 j'Ill-'liii 111.25 111. ~lI MICROCOPY RESOLUTION TEST CHART NATIONAL BUREAU OF SIANDARDS-1963-A a-, MASSACHUSETTS LABORATORY FOR INSTITUTE OF COMPUTER SCIENCE TECHNOLOGY PROGRESS REPORT 18 July 1980- June 1981 1i MAY 2 1.83 CL- Prepared for the Defense Advanced Research Projects Agency 545 TECHNOLOGY SQUARE. CAMBRIDGE, MASSACHUSETTS 02139 83 04 29 018 ,' -.^. %. '" * ' 4. .-,. -i .- - k 7 . - . -. _. - .. .. .. - • . ... ..• . Unclassified "ECUtITY CLASSIFICATION OF THIS PAGE (When Data Entered) REPOT DCUMETATONPGE READ INSTRUCTIONS REPEN RTATIN OCU P GEBEFORE COMPLETING FORM 1. REPORT NUMBER 2. G 3. RECIPIENT'S CATALOG NUMBER LCS Progress Report 18 8'k, 4. TITLE (and Subtitle) S. TYPE OF REPORT & PERIOD COVERED Laboratory for Computer Science DARPA/DOD, Progress Progress Report 18 Report 7/80 - 6/81 . July 1980 - June 1981 6. PERFORMING ORG. REPORT NUMBER LCS-PR 18 7. AUTHOR(s) 8. CONTRACT OR GRANT NUMBER(*) *Laboratory for Computer Science - Michael L. Dertouzos N00014-75-0661 9. PERFORMING ORGANIZATION NAME AND ADDRESS 10. PROGRAM ELEMENT. PROJECT, TASK - Laboratory for Computer Science AREA & WORK UNIT NUMBERS Massachusetts Institute of Technology .. 545 Tech. Sq. Cambridge, MA 02139 1i. CONTROLLING OFFICE NAME AND ADDRESS 12. REPORT DATE -Defense Advanced Research Projects Agency April 1, 1983 * Information Processing Techniques Office 13. -
Software Product Description
Software Product Description PRODUCT NAME: Uniplex™ Business Software for ULTRIX SPD 32.83.01 on RISC, Version 7.00c DESCRIPTION • On-screen print effects Uniplex Business Software is a product of Uniplex Lim- • Paragraph and page numbering ited and distributed under Digital Equipment Corpora- • Decimal tab and column align tion’s Terms and Conditions. • Headers, footers, footnotes and endnotes Uniplex Business Software is a suite of UNIX™-based • Line and box drawing, sketch mode office applications designed to handle routine office ac- tivities. Uniplex II Plus, the base program for all Uniplex • Auto backup and auto save Business Software, provides word processing, spread- • Document boilerplate merge sheet, database and business graphics. In addition to Uniplex II Plus, several optional applications can be • Flexible search and replace added to expand overall office functionality. • Automatic index and table of contents generation Uniplex Advanced Office System (AOS) adds electronic • Spelling dictionary and thesaurus mail, time manager, personal organizer, card index and report writer. Uniplex Advanced Graphics System • Flexible printer formatting on Digital printers (AGS) provides charting, graphing and freehand draw Spreadsheet capabilities. Uniplex Additional Dictionary Pack (ADP) provides support for multiple dictionaries which enables The Uniplex spreadsheet provides the user with a users to spellcheck documents in various languages. choice of using either the Uniplex interface or an in- dustry standard interface (ISSI) similar to that used by Uniplex Business Software uses consistent commands, other leading spreadsheet products. Data can imported menus and softkeys throughout all applications. Users from Lotus® 1-2-3, DIF or ASCII files into a matrix as may "hot-key" between several applications or between large as 1024 rows x 256 columns. -
Mi!!Lxlosalamos SCIENTIFIC LABORATORY
LA=8902-MS C3b ClC-l 4 REPORT COLLECTION REPRODUCTION COPY VAXNMS Benchmarking 1-’ > .— u) 9 g .— mi!!lxLOS ALAMOS SCIENTIFIC LABORATORY Post Office Box 1663 Los Alamos. New Mexico 87545 — wAifiimative Action/Equal Opportunity Employer b . l)lS(”L,\l\ll K “Thisreport wm prcpmd J, an xcttunt ,,1”wurk ,pmwrd by an dgmcy d the tlnitwl SIdtcs (kvcm. mm:. Ncit her t hc llniml SIJIL.. ( Lwcrnmcm nor any .gcncy tlhmd. nor my 08”Ihcif cmployccs. makci my wur,nly. mprcss w mphd. or JwImL.s m> lcg.d Iululity ur rcspmuhdily ltw Ilw w.cur- acy. .vmplctcncs. w uscftthtc>. ttt”any ml’ormdt ml. dpprdl us. prudu.i. w proccw didowd. or rep. resent%Ihd IIS us wuukl not mfrm$e priwtcly mvnd rqdtts. Itcl”crmcti herein 10 my sp.xi!l tom. mrcial ptotlucr. prtxcm. or S.rvskc hy tdc mmw. Irdcnmrl.. nmu(a.lurm. or dwrwi~.. does nut mmwsuily mnstitutc or reply its mdursmwnt. rccummcnddton. or favorin: by the llniwd States (“mvcmment ormy qxncy thctcd. rhc V!C$VSmd opinmm d .mthor% qmxd herein do nut net’. UMrily r;~lt or died lhow. ol”the llnttcd SIJIL.S( ;ovwnnwnt or my ugcncy lhure of. UNITED STATES .. DEPARTMENT OF ENERGY CONTRACT W-7405 -ENG. 36 . ... LA-8902-MS UC-32 Issued: July 1981 G- . VAX/VMS Benchmarking Larry Creel —. I . .._- -- ----- ,. .- .-. .: .- ,.. .. ., ..,..: , .. .., . ... ..... - .-, ..:. .. *._–: - . VAX/VMS BENCHMARKING by Larry Creel ABSTRACT Primary emphasis in this report is on the perform- ance of three Digital Equipment Corporation VAX-11/780 computers at the Los Alamos National Laboratory. Programs used in the study are part of the Laboratory’s set of benchmark programs. -
VAX 4000 V96-2.3—10 Feb 1997
TM VAX 4000 V96-2.3—10 Feb 1997 DIGITAL Systems and Options Catalog Product Description VAX 4000 systems provide commercial systems performance, high availability, and a compact footprint. They support a wide range of applications and options, including FDDI networks and Q-bus peripherals. System enclosure supports internal storage and Q-bus expansion through a B400X expansion cabinet. VAX 4000 systems come in three packages: Desktop Model 106A, Desktop/Deskside Model 108, and Pedestal/Deskside Model 505A/705A DSSI and Ethernet adapter chips—each driven by a 10-MIP on-chip RISC processor—are tightly integrated on the CPU module with direct access to memory. Digital's DSSI to SCSI HSD10 storage solutions replace DSSI RF36 disk technology in all VAX 4000 systems. Digital’s HSD10 DSSI-to-SCSI controller. mounted internally in system cabinet, supports standard RZxx SCSI storage on VAX 4000 systems while still supporting DSSI clustering. External StorageWorks HSD10 controllers are supported. VAX 4000 Model 106A offers performance of 10-ns NVAX chip. Systems achieve 215 transactions per second (TPS). With internal support for the HSD10, DSSI-to-SCSI controller, VAX 4000 customers can take advantage of low-cost, more flexible and open StorageWorks solutions. VAX 4000 Model 108 offers identical performance, is compatible with Model 106A, but is housed in a new Desktop/Deskside minitower enclosure. In addition, these systems offer enchancements in the memory and storage capacity, supporting up to 512 MB of standard SIMM memory and six storage devices in the system enclosure. VAX 4000 Model 505A and 705A offer 12 ns and 9 ns performance, respectively in a Q-bus Pedestal package.