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(12) United States Patent (10) Patent No.: US 6,340,897 B1 Lytle Et Al

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(12) United States Patent (10) Patent No.: US 6,340,897 B1 Lytle Et Al USOO6340897B1 (12) United States Patent (10) Patent No.: US 6,340,897 B1 Lytle et al. (45) Date of Patent: *Jan. 22, 2002 (54) PROGRAMMABLE LOGICARRAY FOREIGN PATENT DOCUMENTS INTEGRATED CIRCUIT WITH GENERAL EP OO81917 8/1983 PURPOSE MEMORY CONFIGURABLE ASA EP O410759 A2 1/1991 RANDOM ACCESS OR FIFO MEMORY EP O415542 A2 3/1991 (75) Inventors: Craig S. Lytle, Mountain View; (List continued on next page.) Donald F. Faria, San Jose, both of CA (US) OTHER PUBLICATIONS Matsumoto, Rodney T., “Configurable On-Chip RAM (73) ASSignee: Altera Corporation, San Jose, CA Incorporated into Hign Speed Logic Array," IEEE Custom (US) Integrated Circuits Conference, Jun. 1985, CH2157–6/85/ (*) Notice: Subject to any disclaimer, the term of this 0000–0240, pp. 240–243. patent is extended or adjusted under 35 Landry, Steve, “Application-Specific ICs, Relying on RAM, U.S.C. 154(b) by 0 days. Implement Almost Any Logic Function,” Electronic Design, Oct. 31, 1985, pp. 123–130. This patent is Subject to a terminal dis Bursky, Dave, “Shrink Systems with One-Chip Decoder, claimer. EPROM, and RAM,” Electronic Design, Jul. 28, 1988, pp. 91-94. (21) Appl. No.: 09/481,781 Kawana, Keiichi et al., “An Efficient Logic Block Intercon nect Architecture for User-Reprogrammable Gate Array,” (22) Filed: Jan. 11, 2000 IEEE 1990 Custom Integrated Circuits Conference, May Related U.S. Application Data 1990, CH2860–5/90/0000–0164, pp. 31.3.1-4 (List continued on next page.) (63) Continuation of application No. 08/707,705, filed on Jul. 24, 1996, now Pat. No. 6,049,223, which is a continuation-in Primary Examiner Michael Tokar part of application No. 08/408.510, filed on Mar. 22, 1995, ASSistant Examiner Steven S. Paik now Pat. No. 5,572,148. (74) Attorney, Agent, or Firm Townsend and Townsend (51) Int. Cl............................................... H03K 19/177 and Crew LLP (52) U.S. Cl. .............................. 326/40; 326/39; 326/41 (57) ABSTRACT (58) Field of Search .............................. 326/38, 39, 40, 326/41; 36.5/221 A programmable logic device integrated circuit incorporat ing a memory block. The memory block (250) is a general (56) References Cited purpose memory configurable as a random access memory U.S. PATENT DOCUMENTS (RAM) or a first-in first-out (FIFO) memory. In one 4,198,744 4/1980 embodiment, the organization of memory block (250) may 4.293.783 10/1981 Nilay - - - - - - - - - - - - - - - - - - - - - - - C. have variable word size and depth size. Memory block (250) 4,441,167 4/1984 Principi. ... 36.5/94 is coupled to a programmable interconnect array (213). 4,617.479 10/1986 Hartmann et al. .......... 307/465 Signals from the programmable interconnect array (213) 4,670,749 6/1987 Freeman ................ 340/825.85 may be programmably coupled to the data, address, and 4,706,216 11/1987 Carter . 365/94 control inputs of the memory block. Data output and Status 4,780,846 10/1988 Tanabe et al. ................ 365/63 flag Signals from the memory block are programmably 4,825.414 4/1989 Kawata ...................... 365/189 coupled to the programmable interconnect array (213). 4,831,591 5/1989 ImaZeki et al. ........ 365/189.08 (List continued on next page.) 52 Claims, 13 Drawing Sheets g fiel agg 5. 205 Eas 209s 2012iy 2f; s H LAB gig 203 as LAB s 220-223-27 23-217-220 S. 'Isis 2:23 SIas - AE Le - s PA ECH HKS g s - LAS LAB -- s s 650 683- 803 572 2. T -8:3 --- NE is lossit i? 2?? i605 2. r 68? is 67,e st-1 685 is i. 619-1 - - - - - - - - - - - - - -------------------- US 6,340,897 B1 Page 2 U.S. PATENT DOCUMENTS Bursky, D. “Combination RAM/PLD Opens New Applica tion Options” (1991) Electronic Design, May 23, 1991, pp. 4,855,958 A 8/1989 Ikeda .................... 365/230.08 138-140. 4,891,788 A 1/1990 Kreifels ....................... 365/49 4,940,909 A 7/1990 Mulder et al. ... 307/468 Plus Logic, “FPSL5110 Intelligent Data Buffer” Data Sheet, 4963,770 A 10/1990 Keida ........... ... 307/465 pp. 1-3. 4,975,601 A 12/1990 Steele ......................... 326/39 Xilinx XC4000, “The Programmable Logic Data Book”, 5,042,004 A 8/1991 Agrawal et al. ............ 364/900 1994, pp. 2-7 through 2–46. 5,122,685 A 6/1992 Chan et al. ............ 307/465.01 MAX 5000, Altera Data Book, Aug. 1993, pp. 149–160. RE34,363 E 8/1993 Freeman ..................... 307/465 “Implementing FIFO Buffers in FLEX 10K Devices”, Altera RE34,444 E 11/1993 Kaplinsky ..... 340/825.8 Corporation, Jan. 1996, Ver. 1, Application Note 66, pp. 5,260.610 A * 11/1993 Pedersen et al. .............. 326/41 1-12. 5,260,727 A 11/1993 Oksman et al. ............. 351/162 5,274,600 A * 12/1993 Ward et al. ................. 365/221 “Configuring FLEX 10K Devices”, Altera Corporation, Dec. 5,313,119 A 5/1994 Cooke et al. ................. 326/41 1995, Ver. 1, Application NOte 59, pp. 1-24. 5,315,178 A 5/1994 Snider .............. ... 307/465 “Flex 10K Embedded Programmable Logic Family”, Altera 5,329,460 A 7/1994 Agrawal et al. .. ... 364/489 Corporation, Jul. 1995, Ver. 1, Data Sheet, pp. 1-56. 5,343,406 A 8/1994 Freeman et al. ..... ... 364/490 “Implementing RAM Functions in FLEX 10K Devices”, 5,352,940 A 10/1994 Watson ....................... 307/468 Altera Corporation, Nov. 1995, Ver. 1, Application Note 52, 5,406.525 A 4/1995 Nicholes .... ... 365/230.02 pp. 1-8. 5,408,434 A 4/1995 Stansfield .. ... 365/189.08 Lattice Semiconductor Corporation Product News Release, 5,414,377 A 5/1995 Freidin ........................ 326/41 5,426,378 A 6/1995 Ong ............................ 326/39 Mar. 4, 1996. 5,432,719 A 7/1995 Freeman et al. ... 364/579 Lattice Semiconductor Corporation Data Sheet, Jan., 1996. 5,469,003 A 11/1995 Kean ........................... 326/39 Bursky, D. “CPLDs. Add Dedicated Memory, Counters To 5,530,378 A * 6/1996 Kucharewski, Jr. et al. ... 326/41 Up Performance,”, Mar. 4, 1996. 5,550,782 A * 8/1996 Cliff et al. ............. 365/230.03 Nelson, “Embedded Memory Enhances Programmable 5,566,123 A 10/1996 Freidin et al. ... 365/230.08 Logic for Complex, Compact Designs, EDN Magazine, 5,570,040 A * 10/1996 Lytle et al. ................... 326/41 Nov. 7, 1996, pp. 91-106. 5,572,148 A * 11/1996 Lytle et al. ................... 326/41 Kautz, “Cellular Logic in Memory Arrays.” IEEE Trans. On 5,668,771 A 9/1997 Cliff et al. ..... ... 365/230.03 Computers, vol. C-18, No. 8, Aug. 1969, pp. 719–727. 5,809,281 A 9/1998 Steele et al. ... 395/497.01 Stone, “A Logic in Memory Computer.” IEEE Trans. On 5.835,405. A 11/1998 Tsui et al. ..... ... 365/182 Computers, Jan. 1970, pp. 73-78. 6,049.223 A * 4/2000 Lytle et al. ................... 326/40 Manning, "An Approach to Highly Integrated Computer FOREIGN PATENT DOCUMENTS Maintained Cellular Arrays.” IEEE Trans. on Computers, vol. C-26, No. 6, Jun. 1977, pp. 536–552. EP O420389 A1 4/1991 Patil et al., “A Programmable Logic Approach for VLSI,” EP O507507 A2 10/1992 EP O530985 A2 3/1993 IEEE Trans. on Computers, vol. C-28, No. 9, Sep. 1979, pp. EP O569137 A2 11/1993 594-601. JP O1091525 A 4/1989 Seitz, “Concurrent VLSI Architectures.” IEEE Trans. on JP O1091526 A 4/1989 Computers, vol. C-33, No. 12, Dec. 1984, pp. 1247-1265. WO WO 94/10754 5/1994 Hsieh et al., “Third Generation Architecture Boosts Speed WO WO95/16993 6/1995 and Density of Filed Programmable Gate Arrays.” Proc. of IEEE CICC Conf., May 1990, pp. 31.2.1 to 31.2.7. OTHER PUBLICATIONS Bursky, “Combination RAM/PLD Opens New Application Options,” Electronic Design, May 23, 1991, pp. 138-140. Plus Logic “FPSL5110 Intelligent Data Buffer” Product Ling et al., “WASMII: A Data Driven Computer on a Virtual Brief, Plus Logic, Inc., San Jose, California, Oct. 1990, pp. Hardware,” Proc. of IEEE Field Prog. Custom Computing 1-6. Machines Conf., Napa, California, Apr. 1993, pp. 33–42. Shubat, Alexander et al., “A Family of User-Programmable Casselman, “Virtual Computing and The Virtual Computer,” Peripherals with a Functional Unit Architecture," IEEE Jor. IEEE, Jul 1993, p. 43. of Solid-State Circuits, vol. 27, No. 4, Apr. 1992, Quenot et al., “A Reconfigurable Compute Engine for Real 0018–9200/92SO3.00, pp. 515–529. -Time Vision Automata Prototyping.” Proc. of IEEE FCCM “AT&T's Orthogonal ORCA Targets the FPGA Future,” Conf., Napan, California, Feb. 1994, pp. 91-100. 8029 Electronic Engineering, 64, No. 786, Jun. 1992, Wool Larsson, T, “Programmable Logic Circuits: The Luxury wich, London, GB, pp. 9-10. Alternatives are Coming Soon,” Elteknik-med-Aktuell Bursky, Dave, “FPGA Advances Cut Delays, Add Flexibil Electronik, No. 4, Feb. 25-Mar. 9, 1988, pp. 37–38, (with ity,” 2328 Electronic Design, 40, No. 20, Oct. 1, 1992, English abstract). Cleveland, OH, pp. 35-43. Intel Prelininary Datasheet, “iFX780: 10ns FLEXlogic Smith, Daniel, “Intel's FLEXlogic FPGA Architecture,” FPGA with SRAM Option,” Nov. 1993, pp. 2–24 to 2–46. IEEE 1063–6390/93, Wilton 29, 1993 pp. 378-384. Quinnell, Richard A., “FPGA Family Offers Speed, Density, Bursky, Dave, “Denser, Faster FPGAs Vie for Gate-Array On-Chip RAM, and Wide-Decode Logic, EDN Dec. 6, Applications,” 2328 Electronic Design, 41, No. 11, May 27, 1990, pp. 62–63. 1993, Cleveland, OH, pp. 55-75. Satoh, Hisayasu et al., “A 209K-Transistor ECL Gate Array Ngai, Kai-Kit Tony, “An SRAM-Programmable Field with RAM, IEEE Jor.
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