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Automating Layout of Reconfigurable Subsystems for Systems-On-A-Chip

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Automating Layout of Reconfigurable Subsystems for Systems-On-A-Chip ©Copyright 2004 Shawn A. Phillips Automating Layout of Reconfigurable Subsystems for Systems-on-a-Chip Shawn A. Phillips A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy University of Washington 2004 Program Authorized to Offer Degree: Electrical Engineering University of Washington Graduate School This is to certify that I have examined this copy of a doctoral dissertation by Shawn A. Phillips and have found that it is complete and satisfactory in all respects, and that any and all revisions required by the final examining committee have been made. Chair of the Supervisory Committee: ____________________________________________________________ Scott Hauck Reading Committee: ____________________________________________________________ Scott Hauck ____________________________________________________________ Carl Ebeling ____________________________________________________________ Larry McMurchie Date: _______________________________ In presenting this dissertation in partial fulfillment of the requirements for the doctoral degree at the University of Washington, I agree that the Library shall make its copies freely available for inspection. I further agree that extensive copying of this dissertation is allowable only for scholarly purposes, consistent with “fair use” as prescribed in the U.S. Copyright Law. Requests for copying or reproduction of this dissertation may be referred to Bell and Howell Information and Learning, 300 North Zeeb Road, Ann Arbor, MI 48106-1346, to whom the author has granted “the right to reproduce and sell (a) copies of the manuscript in microform and/or (b) printed copies of the manuscript made from microform.” Signature _____________________________ Date _________________________________ University of Washington Abstract Automating Layout of Reconfigurable Subsystems for Systems-on-a-Chip by Shawn A. Phillips Chair of the Supervisory Committee: Professor Scott Hauck Electrical Engineering As technology scales, engineers are presented with the ability to integrate many devices onto a single chip, creating entire systems-on-a-chip. When designing SOCs, a unique opportunity exists to add custom reconfigurable fabric, which will provide an efficient compromise between the flexibility of software and the performance of hardware, while at the same time allowing for post-fabrication modification of circuits. Unfortunately, manually generating a custom reconfigurable fabric would make it impossible to meet any reasonable design cycle, while adding considerably to design costs. The goal of the Totem Project is to reduce the design time and effort in the creation of a custom reconfigurable architecture. This thesis is focused on automating the layout generation of custom reconfigurable devices for systems-on-a-chip. Towards this end, we present three methods, namely the Template Reduction, Circuit Generator, and Standard Cell Methods. The Template Reduction Method begins with a full-custom layout as a template that is a superset of the required resources, and removes those resources that are not needed by a given application domain. The Circuit Generator Method takes advantage of the regularity that exists in FPGAs using circuit generators to create the custom reconfigurable devices. Finally, the Standard Cell Method automates the creation of circuits by using a standard cell library that has been optimized for reconfigurable devices. Table of Contents List of Figures iv List of Graphs ix List of Tables xi Chapter 1 Introduction 1 Chapter 2 Reconfigurable Hardware 7 2.1 Architectural Overview............................................................................................. 7 2.2 Field Programmable Gate Array (FPGA)................................................................. 9 2.3 Case Study: The Altera Cyclone II FPGA.............................................................. 11 2.4 Case Study: Reconfigurable-Pipelined Datapath (RaPiD) ..................................... 21 2.5 Developing for Reconfigurable Devices................................................................. 24 Chapter 3 Reconfiguable Hardware in SOCs 27 3.1 Reconfigurable Subsystems.................................................................................... 28 3.2 Systems-on-a-Programmable-Chip (SOPCs) ......................................................... 30 Chapter 4 Totem 33 4.1 Architecture Generation.......................................................................................... 34 4.2 VLSI Layout Generation ........................................................................................ 43 4.3 Place-and-Route Tool Generation .......................................................................... 44 Chapter 5 Research Framework 47 i 5.1 Testing Framework................................................................................................. 48 Chapter 6 Template Reduction 61 6.1 Feature Rich Template............................................................................................ 64 6.2 Reduction List Generation...................................................................................... 65 6.3 Reduction and Compaction..................................................................................... 67 6.4 Results..................................................................................................................... 70 6.5 Summary................................................................................................................. 79 Chapter 7 Circuit Generators 80 7.1 Approach................................................................................................................. 82 7.2 Generators............................................................................................................... 89 7.3 Results..................................................................................................................... 97 7.4 Summary............................................................................................................... 106 Chapter 8 Standard Cell Method 108 8.1 Experimental Setup and Procedure....................................................................... 110 8.2 Results................................................................................................................... 114 8.3 Summary............................................................................................................... 124 Chapter 9 Comparison and Contrast of the Methods 126 9.1 Area Comparison: FC, TR, SC, and CG............................................................... 127 9.2 Performance Comparison: FC, TR, SC, and CG .................................................. 131 Chapter 10 Conclusions and Future Work 134 10.1 Contributions ...................................................................................................... 134 ii 10.2 Conclusions and Future Work ............................................................................ 136 Bibliography 141 iii List of Figures Figure 2-1: Xilinx style FPGA architecture. It contains an array of CLBs, switchboxes, and vertical and horizontal routing channels. ............................................................. 9 Figure 2-2: A basic configurable logic block (CLB) containing a three input LUT and a D-type flip-flop with bypass. .................................................................................... 10 Figure 2-3: A block diagram of the Cyclone II EP2C20 Device [46]. ............................. 12 Figure 2-4: Block Diagram of the Cyclone II logic element (LE) [46]. The LE is the smallest functional unit on the Cyclone II device. Each LE contains the following: a four-input LUT, a programmable register, a carry chain connection, and a register chain connection. ...................................................................................................... 13 Figure 2-5: LAB Structure [46], which provides local interconnect for LEs in the same LAB as well as direct connections between adjacent LE’s within an LAB. ............ 15 Figure 2-6: An embedded multiplier and its corresponding LAB row interface [46]. .... 16 Figure 2-7: An embedded four Kb memory block (M4K), and its corresponding LAB row interface [46]............................................................................................................. 17 Figure 2-8: R4 row interconnect connections. R4 interconnects span four LABs, three LABs and one M4K memory block, or three LABs and one embedded multiplier to the right or left of a source LAB [46]. ...................................................................... 18 Figure 2-9: C4 interconnect, which traverses four blocks in the vertical direction [46]. 20 Figure 2-10: A block diagram of a basic RaPiD-I cell. The functional units in this cell are located at the top of the diagram, with the routing resources located at the bottom. The black boxes represent bus connectors, which are bidirectional switches that enable the creation of long lines. Multiple cells are tiled along a one- dimensional horizontal axis. ..................................................................................... 23 Figure 2-11: High-level view of a possible FPGA design flow. The steps in the process are: design entry, physical synthesis from RTL to gate level, and physical design. Place and route of the design is done using the FPGA vendor proprietary tools, which take into account the devices architecture and logic
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