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A Partitioning-Based Approach to the Fitting Problem in Special Architecture Eplds

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A Partitioning-Based Approach to the Fitting Problem in Special Architecture Eplds Portland State University PDXScholar Dissertations and Theses Dissertations and Theses 1992 A partitioning-based approach to the fitting problem in special architecture EPLDs Steffan Goller Portland State University Follow this and additional works at: https://pdxscholar.library.pdx.edu/open_access_etds Part of the Electrical and Computer Engineering Commons Let us know how access to this document benefits ou.y Recommended Citation Goller, Steffan, "A partitioning-based approach to the fitting problem in special architecture EPLDs" (1992). Dissertations and Theses. Paper 4218. https://doi.org/10.15760/etd.6102 This Thesis is brought to you for free and open access. It has been accepted for inclusion in Dissertations and Theses by an authorized administrator of PDXScholar. Please contact us if we can make this document more accessible: [email protected]. AN ABSTRACT OF THE THESIS OF Steffen Goller for the Master of Science in Electrical Engineering presented July 9, 1992. Title: A Partitioning-Based Approach to the Fitting Problem in Special Architecture EPLDs APPROVED BY THE MEMBERS OF THE THESIS COMMITTEE: Maria E. Balogh In this thesis, we describe an architecture-driven fitting algorithm for an Application-Specific EPLD, the CY7C361, from Cypress Semiconductor. Tradi- tional placement and routing tools for PLDs perform placement and routing sepa- rately. Several placement possibilities are created and the router tries to realize the connections between the physical locations of the cells on the chip. The Cypress CY7C361 has a very unique chip architecture with a highly limited connectivity be­ tween the physical cells. Therefore, it is necessary to consider the mutability when the placement of cells is performed. The combination of the two stages is called fit- ting. The specific architecture-dependent constraints, imposed on the connectivity 2 of the CY7C361 chip were used to develop a hierarchical partitioning structure of the algorithm. This approach limits very effectively the solution space in the early stage of the search for a solution of the fitting problem. The partitioning approach for the fitting algorithm is not limited on the Cypress CY7C361. It can be applied to other architectures with similar connectivity restrictions, too. A PARTITIONING-BASED APPROACH TO THE FITTING PROBLEM IN SPECIAL ARCHITECTURE EPLDS by STEFFEN GOLLER A thesis submitted in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE lil ELECTRICAL ENGINEERIG Portland State University 1992 TO THE OFFICE OF GRADUATE STUDIES: The members of the committee approve the thesis of Steffen Goller presented July 9, 1992. .zanowska-Jeske, Chair Marek A. Maria E. Balogh APPROVED: Rolf Schaumann, air, Department of Electrical Engineering och, Vice Provost for Graduate Studies and Research TABLE OF CONTENTS PAGE LIST OF TABLES v LIST OF FIGURES . v1 GLOSSARY Vlll CHAPTER I INTRODUCTION 1 II PLACEMENT AND ROUTING TECHNIQUES FOREPLDS/FPGAS 8 11.1 FPGAs from Xilinx and Actel . 9 11.2 The Tryptich FPGA . 11 11.3 The Cypress EPLD . 13 11.4 The Concurrent Logic FPGA . 14 III THE STATE MACHINE CY7C361 EPLD ...... 16 111.1 The Architecture of the CY7C361 ....... 16 111.2 Development System for the CY7C361 . 22 IV ARCHITECTURE CONSTRAINTS FOR THE FITTING ALGO- RITHM .................................. 23 V DEFINITIONS AND PROBLEM FORMULATION . 34 V .1 Representation of the Chip Resources . ...... 34 V.2 Representation of the Netlist ......... 41 V.3 Formulation of the Fitting Problem ..... 43 VI DESCRIPTION OF THE FITTING ALGORITHM . 44 IV VI.I P3 Assignment . 48 VI.2 First Partition ......... ................. 51 VI.3 P13 and P23 Assignment ..................... 59 VI.4 Second Partition ......................... 63 VI.5 Physical Placement . 69 VI.5.1 Placement Matrix VI.5.2 Verification of Local Reset Output Restrictions VI.5.3 Final Physical Placement VII RESULTS OF THE FITTER ........... 81 VIII HEURISTICS FOR THE FIRST PARTITION .. 89 IX COMPLEXITY ANALYSIS 93 x CONCLUSION 97 REFERENCES . 99 LIST OF TABLES TABLE PAGE I Result of First and Second Partition 70 II Columns of the Placement Matrix and Partitions 72 III Industrial Examples . 83 IV Examples where PABFIT is Better than Cyperss Fitter . 84 V Additional Local Resets . 87 VI Examples where PABFIT Uses Heuristics. 92 LIST OF FIGURES FIGURE PAGE 1 Split Plane Architecture of the CY7C361. 18 2 Architecture of the CY7C361. 19 3 Array of Local Reset Groups of the CY7C361. 21 4 Interconnection Matrix of the CY7C361. 24 5 First-Level Partitioning of the Interconnection Matrix. 26 6 Second-Level Partitioning of the Interconnection Matrix. 28 7 First- and Lecond-Level Partitioning of the Interconnection Matrix. 29 8 Output Availability of State Macrocells to Local Resets. 32 9 First-Level Partitioning of Gp. 38 10 Second-Level Partitioning of Gp1 U Gp31 and Gp2 U Gp32. 40 11 Additional Normal Edge due to Input Restrictions of Local Resets. 42 12 Flowchart of the PABFIT Algorithm. 45 13 Chains in the P3 Assignment. 50 14 Example of a First Partition. 54 15 Example of a First Partition with a chain_cut_l. 57 16 Chains in the P13 Assignment. 61 17 Example of a Second Partition. 65 18 Example of a Second Partition with chain_cuL2. 67 19 Placement Matrix. 71 20 Examples of Local Reset Output Violations. 74 Vll 21 State Cell Feasible Mapping. .. 77 22 Local Resets and the Symbolic Graph. ... 78 23 Local Reset Connectivity Matrix. .................... 80 24 Degree Vector. 91 GLOSSARY Pa partition of physical macrocells Gp physical connectivity graph Vp vertex set of Gp Vpi element of Vp ENp normal edge set of Gp en pi element of ENp ECp chain-edge set of Gp ecpi element of ECp Gpa subgraph of Gp representing Pa Vpa vertex set of G Pa ENPa normal edge set of G Pa ECpa chain-edge set of G Pa Gr super graph with G Pa as vertices Vr vertex set of Gr ENr normal edge set of Gr ECT chain-edge set of Gr Gs symbolic graph representing the netlist Vs vertex set of Gs VSi element of Vs ENs normal edge set of Gs ensi element of ENs IX ECs chain-edge set of Gs ecsi element of ECs Pi physical macrocell of the CY7C361 plri physical local reset LRGi physical local reset group lri symbolic local reset CHi symbolic chain i CHAPTER I INTRODUCTION At the beginning of circuit integration, the design of a circuit on a piece of silicon was done completely manually by the designer. The design started with an empty piece of silicon at the transistor-level. The designer had to place the transistors, interconnect them to gates or memory blocks, and realize the connections between the different blocks by hand. Therefore, design process was very time consuming, especially as the integration of the circuit was increasing. Within the last years, more and more CAD tools have been developed for the design automation of integrated circuits. Today, tools for all different design methodologies are available. The approach to circuit realization can be classified in two distinct design methodologies [1 ], both covering a variety of different design styles. One method­ ology is the Full Custom Design [1] style that offers a maximum flexibility for ap­ plications of the technology in terms of the transistor sizing, the placement of the transistor on the silicon, and the interconnections. A development system for a Full Custom Design usually includes large libraries with predefined blocks (gates or modules), that can be included in the design. However, the designer still has the possibility of customizing the design at the transistor-level. After the design of the modules and the specification of the connections between them, the designer can use CAD tools that perform the placement and routing of the modules on the chip. Several tools are available for floorplanning [2] [3), placement [4), global routing, and detailed routing [5) [6) {7). 2 Contrary to the Full Custom Design, the Semi Custom Design [1] starts with a chip with regular pre-patterned silicon arrays that are customized at the interconnect-level in order to realize a given circuit. This design style offers less flexibility than a Full Custom Design, but the regularity of the predefined silicon arrays made it possible to develop CAD tools that automize the complete design pro­ cess. The circuit can be described in an abstract High-Level Description Language (HDL) (8], rather than on the transistor /gate-level. Thus, the design becomes inde­ pendent from the available device and the manufacturing cycle and manufacturing cost of the circuit design is strongly reduced. The Semi Custom Design style is very important for many Application Spe­ cific Integrated Circuits (ASICs) (1]. These are special purpose integrated circuits where a Full Custom Design is too time consuming and too expensive. The devices used for ASICs are Gate Arrays, Standard Cells, Sea of Gates, and Programmable Logic Devices (PLDs ). They differ in the logic and routing resources available on the chip and the programmability of these resources. Gate Arrays and Standard Cells are devices with pre-fabricated arrays of logic blocks, consisting of transistors, gates (AND, OR etc.), or memory cells. Gate Arrays consist of blocks that have all the same size (length and height). Standard Cells contain blocks where the height is predefined but the length is variable. The locations of the blocks on the chip are fixed. They are surrounded by horizontal and vertical routing channels that allow the realization of connections between the blocks. Each connection requires a routing track, that is routed directly on the silicon, where the routing track is located in the routing channels. The circuit design starts with empty routing channels and then routes sequentially all connections. Several placement and routing tools (9] are available that show good results for these 3 kind of devices. Devices where the routing channels are pre-fabricated are called Mask Programmable Gate Arrays (MPGAs).
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