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Contrpl Data Nos Version 2 Administration Handbook
60459840 CONTRPL DATA NOS VERSION 2 ADMINISTRATION HANDBOOK /fP^v CDC® OPERATING SYSTEMS: CYBER 180 CYBER 170 CYBER 70 MODELS 71, 72, 73, 74 6000 REVISION RECORD T-gSZBZaSESEl jiito wminan REVISION DESCRIPTION Manual released; reflects NOS 2.3 at PSR level 617. Features include default charge restriction, (10-05-84) terminal input and output count at logoff, password randomization, a new CHARGE directive for the SUBMIT command, and support of the Mass Storage Archival Subsystem. Supports CYBER 180 computer systems. B Revision B reflects NOS 2.4.2 at PSR level 642. It incorporates new features such as support of (09-26-85) CYBER 180 Models 840, 850, 860, and 990, Printer Support Utility, and NAM Application Switching. Revision C reflects NOS 2.5.1 at PSR level 664. It documents the personal identification (09-30-86) v a l i d a t i o n , t h e s i n g l e t e r m i n a l s e s s i o n r e s t r i c t i o n , a n d o t h e r m i s c e l l a n e o u s t e c h n i c a l c h a n g e s . Revision D reflects NOS 2.6.1 at PSR level 700. It includes miscellaneous corrections and minor (04-14-88) additions. Publication No, 60459840 REVISION LETTERS I. O. Q. S. X AND Z ARE NOT USED. Address comments concerning this manual to: Control Data Technical Publications 4201 N. -
Final Report and Recommendation on New
CERN LIBRARIES, GENEVA CERN/FC/661 Original: English 5 December, 1963 CM-P00085196 ORGANISATION EUROPĒENNE POUR LA RECHERCHE NUCLĒAIRE CERN EUROPEAN ORGANIZATION FOR NUCLEAR RESEARCH FINANCE COMMITTEE Fifty-sixth Meeting Geneva - 16 December, 1963 FINAL REPORT AND RECOMMENDATION ON NEW COMPUTERS FOR CERN This paper contains the results of the enquiries and studies unfinished at the time of the meeting of the Finance Committee, on 13 November, together with the Director-General's conclusions and request to the Finance Committee to authorize CERN to purchase a CDC 6600 computer for delivery early in 1965. 7752/e CERN/FC/661 FINAL REPORT AND RECOMMENDATION ON NEW COMPUTERS FOR CERN 1. Introduction The Finance Committee, at its meeting, on 13 November, discussed an interim report on CERN's computing needs (CERN/FC/653), which accompanied the Report of the European Committee on the Future Computing Needs of CERN, CERN/516 (hereinafter referred to as "the Report"). Since then, the final offers from manufacturers have been received and evaluated, and the outstanding technical studies referred to in the conclusion of the Interim Report (section 5) have been carried out. This paper contains: - a short report on the results of these technical studies, - the evaluation of the final offers, technically and financially, - a proposal for financing the purchase of the new computer, - the implications on the CERN budget and programme of a new computer, - the conclusion, with a request that the Finance Committee authorize CERN to purchase a CDC 6600 computer and to raise a loan for the necessary amount, - an annex containing prices and other material from the offers. -
A Characterization of Processor Performance in the VAX-1 L/780
A Characterization of Processor Performance in the VAX-1 l/780 Joel S. Emer Douglas W. Clark Digital Equipment Corp. Digital Equipment Corp. 77 Reed Road 295 Foster Street Hudson, MA 01749 Littleton, MA 01460 ABSTRACT effect of many architectural and implementation features. This paper reports the results of a study of VAX- llR80 processor performance using a novel hardware Prior related work includes studies of opcode monitoring technique. A micro-PC histogram frequency and other features of instruction- monitor was buiit for these measurements. It kee s a processing [lo. 11,15,161; some studies report timing count of the number of microcode cycles execute z( at Information as well [l, 4,121. each microcode location. Measurement ex eriments were performed on live timesharing wor i loads as After describing our methods and workloads in well as on synthetic workloads of several types. The Section 2, we will re ort the frequencies of various histogram counts allow the calculation of the processor events in 5 ections 3 and 4. Section 5 frequency of various architectural events, such as the resents the complete, detailed timing results, and frequency of different types of opcodes and operand !!Iection 6 concludes the paper. specifiers, as well as the frequency of some im lementation-s ecific events, such as translation bu h er misses. ?phe measurement technique also yields the amount of processing time spent, in various 2. DEFINITIONS AND METHODS activities, such as ordinary microcode computation, memory management, and processor stalls of 2.1 VAX-l l/780 Structure different kinds. This paper reports in detail the amount of time the “average’ VAX instruction The llf780 processor is composed of two major spends in these activities. -
Lecture 14 Data Level Parallelism (2) EEC 171 Parallel Architectures John Owens UC Davis Credits • © John Owens / UC Davis 2007–9
Lecture 14 Data Level Parallelism (2) EEC 171 Parallel Architectures John Owens UC Davis Credits • © John Owens / UC Davis 2007–9. • Thanks to many sources for slide material: Computer Organization and Design (Patterson & Hennessy) © 2005, Computer Architecture (Hennessy & Patterson) © 2007, Inside the Machine (Jon Stokes) © 2007, © Dan Connors / University of Colorado 2007, © Kathy Yelick / UCB 2007, © Wen-Mei Hwu/David Kirk, University of Illinois 2007, © David Patterson / UCB 2003–7, © John Lazzaro / UCB 2006, © Mary Jane Irwin / Penn State 2005, © John Kubiatowicz / UCB 2002, © Krste Asinovic/Arvind / MIT 2002, © Morgan Kaufmann Publishers 1998. Outline • Vector machines (Cray 1) • Vector complexities • Massively parallel machines (Thinking Machines CM-2) • Parallel algorithms Vector Processing • Appendix F & slides by Krste Asanovic, MIT Supercomputers • Definition of a supercomputer: • Fastest machine in world at given task • A device to turn a compute-bound problem into an I/O bound problem • Any machine costing $30M+ • Any machine designed by Seymour Cray • CDC 6600 (Cray, 1964) regarded as first supercomputer Seymour Cray • “Anyone can build a fast CPU. The trick is to build a fast system.” • When asked what kind of CAD tools he used for the Cray-1, Cray said that he liked “#3 pencils with quadrille pads”. Cray recommended using the backs of the pages so that the lines were not so dominant. • When he was told that Apple Computer had just bought a Cray to help design the next Apple Macintosh, Cray commented that he had just bought -
Conversion of the COBRA-IV-I Code from CDC CYBER to HP 9000/700 Version
KAERI/TR-803/97 Conversion of the COBRA-IV-I Code from CDC CYBER to HP 9000/700 Version CDC CYBER Version COBRA-IV-I ^H HP 9000/700 Version ° 1997. 1 Korea Atomic Energy Research Institute £- JiJL>Hl- "CDC CYBER Version COBRA-IV-I 3.B.4) HP 9000/700 Version ±£-2\ ^^" o\] 1997 tf 71 «V Abstract COBRA-IV-I is a multichannel analysis code for the thermal-hydraulic analysis of rod bundle nuclear fuel elements and cores based on the subchannel approach. The existing COBRA-IV-I code is the Control Data Corporation (CDC) CYBER version, which has limitations on the computer core storage and gives some inconvenience to the user interface. To solve these problems, we have converted the COBRA-IV-I code from the CDC CYBER mainframe to an Hewlett Packard (HP) 9000/700-series workstation version, and have verified the converted code. As a result, we have found almost no difference between the two versions in their calculation results. Therefore we expect the HP 9000/700 version of the COBRA-IV-I code to be the basis for the future development of an improved multichannel analysis code under the more convenient user environment. COBRA-IV-I fe COBRA-IV-I £• CDC CYBER-§- SE CDC CYBER oflSlH COBRA-IV-I SHf HP 9000/700 HP 9000/700 -§--^- COBRA-IV-I 3-E.t: ^± Table of Contents Abstract 2 Abstract (in Korean) 3 Table of Contents 4 List of Tables 6 List of Figures 7 1. Introduction 8 2. Conversion of COBRA-IV-1 9 2.1 Precision 9 2.2 Convenience 12 2.3 Emulation 12 2.4 Syntax 13 2.5 Equivalence 17 3. -
CHAPTER 1 Introduction
CHAPTER 1 Introduction 1.1 Overview 1 1.2 The Main Components of a Computer 3 1.3 An Example System: Wading through the Jargon 4 1.4 Standards Organizations 15 1.5 Historical Development 16 1.5.1 Generation Zero: Mechanical Calculating Machines (1642–1945) 17 1.5.2 The First Generation: Vacuum Tube Computers (1945–1953) 19 1.5.3 The Second Generation: Transistorized Computers (1954–1965) 23 1.5.4 The Third Generation: Integrated Circuit Computers (1965–1980) 26 1.5.5 The Fourth Generation: VLSI Computers (1980–????) 26 1.5.6 Moore’s Law 30 1.6 The Computer Level Hierarchy 31 1.7 The von Neumann Model 34 1.8 Non-von Neumann Models 37 Chapter Summary 40 CMPS375 Class Notes (Chap01) Page 1 / 11 by Kuo-pao Yang 1.1 Overview 1 • Computer Organization o We must become familiar with how various circuits and components fit together to create working computer system. o How does a computer work? • Computer Architecture: o It focuses on the structure and behavior of the computer and refers to the logical aspects of system implementation as seen by the programmer. o Computer architecture includes many elements such as instruction sets and formats, operation code, data types, the number and types of registers, addressing modes, main memory access methods, and various I/O mechanisms. o How do I design a computer? • The computer architecture for a given machine is the combination of its hardware components plus its instruction set architecture (ISA). • The ISA is the agreed-upon interface between all the software that runs on the machine and the hardware that executes it. -
The Implementation of Prolog Via VAX 8600 Microcode ABSTRACT
The Implementation of Prolog via VAX 8600 Microcode Jeff Gee,Stephen W. Melvin, Yale N. Patt Computer Science Division University of California Berkeley, CA 94720 ABSTRACT VAX 8600 is a 32 bit computer designed with ECL macrocell arrays. Figure 1 shows a simplified block diagram of the 8600. We have implemented a high performance Prolog engine by The cycle time of the 8600 is 80 nanoseconds. directly executing in microcode the constructs of Warren’s Abstract Machine. The imulemention vehicle is the VAX 8600 computer. The VAX 8600 is a general purpose processor Vimal Address containing 8K words of writable control store. In our system, I each of the Warren Abstract Machine instructions is implemented as a VAX 8600 machine level instruction. Other Prolog built-ins are either implemented directly in microcode or executed by the general VAX instruction set. Initial results indicate that. our system is the fastest implementation of Prolog on a commercrally available general purpose processor. 1. Introduction Various models of execution have been investigated to attain the high performance execution of Prolog programs. Usually, Figure 1. Simplified Block Diagram of the VAX 8600 this involves compiling the Prolog program first into an intermediate form referred to as the Warren Abstract Machine (WAM) instruction set [l]. Execution of WAM instructions often follow one of two methods: they are executed directly by a The 8600 consists of six subprocessors: the EBOX. IBOX, special purpose processor, or they are software emulated via the FBOX. MBOX, Console. and UO adamer. Each of the seuarate machine language of a general purpose computer. -
ABSTRACT CO-RESIDENT OPERATING SYSTEMS TASK TEAM REPORT April 181 1973
ABSTRACT CO-RESIDENT OPERATING SYSTEMS TASK TEAM REPORT THIS DOCUI-lENT CONTAINS INFORl-lATiON PROPRIETARY TO THE NATIONAL CASH REGISTER COfoIPAflY AND CONTROL DATA CORPORATION. ITS CONTENTS SHALL NOT BE DIVULGED OUTSIDE OF EITHER CO~lPANY NOR REPROD~CED mTHOUT EXPLICIT PERloJISSION OF THE DIRECTOR AND GENERAL r-lANAGER. NCRICDC ADVANCED SYSTEfolS LABORATORY. April 18 1 1973 · 1 The mission of the co-resident oper.al"ing system task group was: "To define a cost effective mechamism within the new operating system to allow selected 01 d operating syst'ems to operate in their entirety permitting simultaneous execution with no modifications to the old operating system". Four people were assigned to this task, I:wo from NCR wifh ,expBrience on/he NCi\/Century and two from CDC experienced with CYI3ER 70 computer systems. The scope of the probl em was narrowed to a point where productive OLltput could be obtained in the allotted time frame. It was decided the' time could be spent most profitably in a detailad study of emulating the .NCR Century computer systems ,on the IPL.·· This decision was heavily influen'ced by a desire to deal with specific problems , ' ral·her·than'philosophi'cal-cmd incondusive'mattcrs. It was also:f.;:;lt thut The productivity of the team would be greater if it were kept s.mall •. Having limited the problom in scope, vario~sassumptions h.od t:)bo made bdore furi-h.:,:,r progress could be accompl ished. Key in this area wes the assumption thar. ;h:; probkm wos soluble. As a result I Ihe team concentroted on how to effect Iheimp\ernentation, as opposed j'O if if' was possibl e. -
VAX VMS at 20
1977–1997... and beyond Nothing Stops It! Of all the winning attributes of the OpenVMS operating system, perhaps its key success factor is its evolutionary spirit. Some would say OpenVMS was revolutionary. But I would prefer to call it evolutionary because its transition has been peaceful and constructive. Over a 20-year period, OpenVMS has experienced evolution in five arenas. First, it evolved from a system running on some 20 printed circuit boards to a single chip. Second, it evolved from being proprietary to open. Third, it evolved from running on CISC-based VAX to RISC-based Alpha systems. Fourth, VMS evolved from being primarily a technical oper- ating system, to a commercial operat- ing system, to a high availability mission-critical commercial operating system. And fifth, VMS evolved from time-sharing to a workstation environment, to a client/server computing style environment. The hardware has experienced a similar evolution. Just as the 16-bit PDP systems laid the groundwork for the VAX platform, VAX laid the groundwork for Alpha—the industry’s leading 64-bit systems. While the platforms have grown and changed, the success continues. Today, OpenVMS is the most flexible and adaptable operating system on the planet. What start- ed out as the concept of ‘Starlet’ in 1975 is moving into ‘Galaxy’ for the 21st century. And like the universe, there is no end in sight. —Jesse Lipcon Vice President of UNIX and OpenVMS Systems Business Unit TABLE OF CONTENTS CHAPTER I Changing the Face of Computing 4 CHAPTER II Setting the Stage 6 CHAPTER -
A Look at Some Compilers MATERIALS from the DRAGON BOOK and WIKIPEDIA MICHAEL WOLLOWSKI
2/11/20 A Look at some Compilers MATERIALS FROM THE DRAGON BOOK AND WIKIPEDIA MICHAEL WOLLOWSKI EQN oTakes inputs like “E sub 1” and produces commands for text formatter TROFF to produce “E1” 1 2/11/20 EQN EQN oTreating EQN as a language and applying compiler technologies has several benefits: oEase of implementation. oLanguage evolution. In response to user needs 2 2/11/20 Pascal Developed by Nicolas Wirth. Generated machine code for the CDC 6000 series machines To increase portability, the Pascal-P compiler generates P-code for an abstract stack machine. One pass recursive-descent compiler Storage is organized into 4 areas: ◦ Code for procedures ◦ Constants ◦ Stack for activation records ◦ Heap for data allocated by the new operator. Procedures may be nested, hence, activation record for a procedure contains both access and control links. CDC 6000 series The first member of the CDC 6000 series Was the supercomputer CDC 6600, Designed by Seymour Cray and James E. Thornton Introduced in September 1964 Performed up to three million instructions per second, three times faster than the IBM Stretch, the speed champion for the previous couple of years. It remained the fastest machine for five years until the CDC 7600 Was launched. The machine Was Freon refrigerant cooled. Control Data manufactured about 100 machines of this type, selling for $6 to $10 million each. 3 2/11/20 CDC 6000 series By Steve Jurvetson from Menlo Park, USA - Flickr, CC BY 2.0, https://commons.Wikimedia.org/w/index.php?curid=1114605 CDC 205 CDC 205 DKRZ 4 2/11/20 CDC 205 CDC 205 Wiring, davdata.nl Pascal 5 2/11/20 Pascal One of the compiler Writers states about the use of a one-pass compiler: ◦ Easy to implement ◦ Imposes severe restrictions on the quality of the generated code and suffers from relatively high storage requirements. -
Vincent M. Weaver Sally A. Mckee
Optimizing for Size: Exploring the Limits of Code Density Sally A. McKee Vincent M. Weaver ASPLOS XIV Poster Session, 8 March 2009 Cornell University Chalmers University of Technology Abstract Hand-Optimized Assembly Results Architectural Size Correlations 0.9020 Minimum possible instruction size Reductions in instruction count can improve cache and bandwidth utiliza- 0.8652 Number of integer registers tion, lower power consumption, and increase overall performance. Nonethe- Total Size of Executable VLIW 2560 RISC less, code density is often overlooked when studying processor architectures. 2048 CISC 0.6623 Architecture has a zero register embedded 1536 8/16-bit 0.5845 Bit-width bytes 1024 We hand-optimize an embedded benchmark for size in assembly language -0.4366 Hardware divide in ALU on 20 different instruction set architectures and investigate the architectural 512 features that contribute most heavily to code density. 0 0.4385 Number of operands in each instruction arm ppc vax sh3 z80 ia64 6502 mips s390 i386 alphaparisc sparc m88k m68k thumb avr32 -0.3356 Unaligned load/store available x86_64 crisv32pdp-11 0.2773 Year the architecture was introduced 256 Size of LZSS Decompression Code VLIW -0.2597 Auto-incrementing addressing scheme Background RISC CISC 192 embedded -0.2597 Hardware status flags (zero/overflow/etc.) 128 8/16-bit bytes -0.1252 Little or Big endian 64 The 20 architectures investigated can be broadly broken into 5 categories: -0.0487 Branch delay slot 0 -0.0079 Maximum possible instruction size Instr Length Opcode arm ppc vax z80 sh3 ia64 mips s390 6502 i386 Type Represented Architectures alpha parisc sparc m88k m68kthumb avr32 (bytes) Args pdp-11 x86_64crisv32 VLIW ia64 16/3 3 Size of String-Search Code VLIW Other Considerations alpha, arm, m88k, mips 256 RISC RISC 4 3 CISC pa-risc, ppc, sparc 192 embedded 128 8/16-bit System libraries and compiler overhead can overshadow the effects of size bytes CISC m68k, s390, vax, x86, x86 64 1-54 2 64 optimization, increasing memory footprint by several orders of magnitude. -
In Using the GNU Compiler Collection (GCC)
Using the GNU Compiler Collection For gcc version 6.1.0 (GCC) Richard M. Stallman and the GCC Developer Community Published by: GNU Press Website: http://www.gnupress.org a division of the General: [email protected] Free Software Foundation Orders: [email protected] 51 Franklin Street, Fifth Floor Tel 617-542-5942 Boston, MA 02110-1301 USA Fax 617-542-2652 Last printed October 2003 for GCC 3.3.1. Printed copies are available for $45 each. Copyright c 1988-2016 Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with the Invariant Sections being \Funding Free Software", the Front-Cover Texts being (a) (see below), and with the Back-Cover Texts being (b) (see below). A copy of the license is included in the section entitled \GNU Free Documentation License". (a) The FSF's Front-Cover Text is: A GNU Manual (b) The FSF's Back-Cover Text is: You have freedom to copy and modify this GNU Manual, like GNU software. Copies published by the Free Software Foundation raise funds for GNU development. i Short Contents Introduction ::::::::::::::::::::::::::::::::::::::::::::: 1 1 Programming Languages Supported by GCC ::::::::::::::: 3 2 Language Standards Supported by GCC :::::::::::::::::: 5 3 GCC Command Options ::::::::::::::::::::::::::::::: 9 4 C Implementation-Defined Behavior :::::::::::::::::::: 373 5 C++ Implementation-Defined Behavior ::::::::::::::::: 381 6 Extensions to