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Mi!!Lxlosalamos SCIENTIFIC LABORATORY
LA=8902-MS C3b ClC-l 4 REPORT COLLECTION REPRODUCTION COPY VAXNMS Benchmarking 1-’ > .— u) 9 g .— mi!!lxLOS ALAMOS SCIENTIFIC LABORATORY Post Office Box 1663 Los Alamos. New Mexico 87545 — wAifiimative Action/Equal Opportunity Employer b . l)lS(”L,\l\ll K “Thisreport wm prcpmd J, an xcttunt ,,1”wurk ,pmwrd by an dgmcy d the tlnitwl SIdtcs (kvcm. mm:. Ncit her t hc llniml SIJIL.. ( Lwcrnmcm nor any .gcncy tlhmd. nor my 08”Ihcif cmployccs. makci my wur,nly. mprcss w mphd. or JwImL.s m> lcg.d Iululity ur rcspmuhdily ltw Ilw w.cur- acy. .vmplctcncs. w uscftthtc>. ttt”any ml’ormdt ml. dpprdl us. prudu.i. w proccw didowd. or rep. resent%Ihd IIS us wuukl not mfrm$e priwtcly mvnd rqdtts. Itcl”crmcti herein 10 my sp.xi!l tom. mrcial ptotlucr. prtxcm. or S.rvskc hy tdc mmw. Irdcnmrl.. nmu(a.lurm. or dwrwi~.. does nut mmwsuily mnstitutc or reply its mdursmwnt. rccummcnddton. or favorin: by the llniwd States (“mvcmment ormy qxncy thctcd. rhc V!C$VSmd opinmm d .mthor% qmxd herein do nut net’. UMrily r;~lt or died lhow. ol”the llnttcd SIJIL.S( ;ovwnnwnt or my ugcncy lhure of. UNITED STATES .. DEPARTMENT OF ENERGY CONTRACT W-7405 -ENG. 36 . ... LA-8902-MS UC-32 Issued: July 1981 G- . VAX/VMS Benchmarking Larry Creel —. I . .._- -- ----- ,. .- .-. .: .- ,.. .. ., ..,..: , .. .., . ... ..... - .-, ..:. .. *._–: - . VAX/VMS BENCHMARKING by Larry Creel ABSTRACT Primary emphasis in this report is on the perform- ance of three Digital Equipment Corporation VAX-11/780 computers at the Los Alamos National Laboratory. Programs used in the study are part of the Laboratory’s set of benchmark programs. -
DX11-8 System 360/370 Channel to PDP-11 Unibus Interface Maintenance Manual
EK-DXIIB-MM-002 DX11-8 system 360/370 channel to PDP-11 unibus interface maintenance manual digital equipment corporation • maynard, massachusetts 1st Edition, August 1972 2nd Printing (Rev) March 1973 3rd Printing July 1973 4th Printing May 1974 5th Printing (Rev) January 1976 Copyright © 1972,1973,1974,1976 by Digital Equipment Corporation The material in this manual is for informational purposes and is subject to change without notice. Digital Equipment Corporation assumes no respon sibility for any errors which may appear in this manual. Printed in U.S.A. The following are trademarks of Digital Equipment Corporation, Maynard, Massachusetts: DEC PDP FLIP CHIP FOCAL DIGITAL COMPUTER LAB CONTENTS Page CHAPTER 1 GENERAL DESCRIPTION 1.1 Purpose of Manual 1-1 1.2 System Description 1-2 1.3 Mechanical Description 1-5 1.4 Specifications 1-5 1.4.1 Physical 1-6 1.4.2 Environmental 1-6 1.4:3 Electrical 1-6 1.4.4 Performance 1-6 1.5 Engineering Drawaing Drawings 1-7 CHAPTER 2 INSTALLATION AND ACCEPTANCE TEST 2.1 Summary of Installation Functions 2-1 2.2 Installation and Acceptance Test Requirements 2-2 2.2.1 Equipment Required 2-2 2.2.2 Diagnostics Required 2-2 2.2.3 Space Requirements 2-3 2.2.4 Power Requirements 2-3 2.2.5 Information Requirements 2-5 2.2.6 Test Schedule 2-6 2.3 Unpacking and Inspection 2-6 2.3.1 Unpacking 2-6 2.3.2 Inspection 2-7 2.4 Installation 2-7 2.4.1 PDP-II and DX11-B Cable Installation (within PDP-II System) 2-7 2.4.2 IBM Device Address Jumper Installation 2-8 2.4.3 Interrupt Vector Address Jumper Installation 2-12 -
PDP-11 Bus Handbook (1979)
The material in this document is for informational purposes only and is subject to change without notice. Digital Equipment Corpo ration assumes no liability or responsibility for any errors which appear in, this document or for any use made as a result thereof. By publication of this document, no licenses or other rights are granted by Digital Equipment Corporation by implication, estoppel or otherwise, under any patent, trademark or copyright. Copyright © 1979, Digital Equipment Corporation The following are trademarks of Digital Equipment Corporation: DIGITAL PDP UNIBUS DEC DECUS MASSBUS DECtape DDT FLIP CHIP DECdataway ii CONTENTS PART 1, UNIBUS SPECIFICATION INTRODUCTION ...................................... 1 Scope ............................................. 1 Content ............................................ 1 UNIBUS DESCRIPTION ................................................................ 1 Architecture ........................................ 2 Unibus Transmission Medium ........................ 2 Bus Terminator ..................................... 2 Bus Segment ....................................... 3 Bus Repeater ....................................... 3 Bus Master ........................................ 3 Bus Slave .......................................... 3 Bus Arbitrator ...................................... 3 Bus Request ....................................... 3 Bus Grant ......................................... 3 Processor .......................................... 4 Interrupt Fielding Processor ......................... -
A Characterization of Processor Performance in the VAX-1 L/780
A Characterization of Processor Performance in the VAX-1 l/780 Joel S. Emer Douglas W. Clark Digital Equipment Corp. Digital Equipment Corp. 77 Reed Road 295 Foster Street Hudson, MA 01749 Littleton, MA 01460 ABSTRACT effect of many architectural and implementation features. This paper reports the results of a study of VAX- llR80 processor performance using a novel hardware Prior related work includes studies of opcode monitoring technique. A micro-PC histogram frequency and other features of instruction- monitor was buiit for these measurements. It kee s a processing [lo. 11,15,161; some studies report timing count of the number of microcode cycles execute z( at Information as well [l, 4,121. each microcode location. Measurement ex eriments were performed on live timesharing wor i loads as After describing our methods and workloads in well as on synthetic workloads of several types. The Section 2, we will re ort the frequencies of various histogram counts allow the calculation of the processor events in 5 ections 3 and 4. Section 5 frequency of various architectural events, such as the resents the complete, detailed timing results, and frequency of different types of opcodes and operand !!Iection 6 concludes the paper. specifiers, as well as the frequency of some im lementation-s ecific events, such as translation bu h er misses. ?phe measurement technique also yields the amount of processing time spent, in various 2. DEFINITIONS AND METHODS activities, such as ordinary microcode computation, memory management, and processor stalls of 2.1 VAX-l l/780 Structure different kinds. This paper reports in detail the amount of time the “average’ VAX instruction The llf780 processor is composed of two major spends in these activities. -
What We Learned from the PDP-11
ABSTRACT Gordon Bell, William Il. Strecker November 8, 1975 COMPUTER STRUCTURES: WHAT HAVE WE LEARNED FROM THE PDP-ll? Over the FDP-11’S six year life behave in a particular way? about 20,000 specimens have been Where does it get inputs? HOW built based on 10 species (models). does it formulate and solve Al though range was a design goal, problems? it was unquantified; the actual range has exceeded expectations 3. The rest of the DEC (5OO:l in memory size and system organization--this includes price]. The range has stressed the applications groups assoc ia ted baa ic mini (mall computer with market groups # sales, architecture along all dimensions. service and manufacturing. The marn PM.5 structure, i.e. the UNIBUS, has been adopted as a de 4. The user, who receives the facto standard of interconnection final OUtQUt. for many micro and minicomputer systems. The architectural Note, that if we assume that a experience gained in the design and QrOduc t is done sequentially, and use of the PDP-11 will be described each stage has a gestation time of in terms Of its environment about two years, it takes roughly (initial goals and constraints, eight years for an idea from basic technology, and the organization research to finally appear at the that designs, builds and user’s site. Other organizations distributes the machine). ala0 affect the design : competitors (they establish a deaign level and determine the product life): and government IsI 1.0 TNTRODUCTTON and standards. There are an ever increasing number Although one might think that of groups who feel compel led to computer architecture is the sole control all products bringing them determinant of a machine, it is all common norm : the merely the focal point for a government (“5) , testing groups such specification. -
The Implementation of Prolog Via VAX 8600 Microcode ABSTRACT
The Implementation of Prolog via VAX 8600 Microcode Jeff Gee,Stephen W. Melvin, Yale N. Patt Computer Science Division University of California Berkeley, CA 94720 ABSTRACT VAX 8600 is a 32 bit computer designed with ECL macrocell arrays. Figure 1 shows a simplified block diagram of the 8600. We have implemented a high performance Prolog engine by The cycle time of the 8600 is 80 nanoseconds. directly executing in microcode the constructs of Warren’s Abstract Machine. The imulemention vehicle is the VAX 8600 computer. The VAX 8600 is a general purpose processor Vimal Address containing 8K words of writable control store. In our system, I each of the Warren Abstract Machine instructions is implemented as a VAX 8600 machine level instruction. Other Prolog built-ins are either implemented directly in microcode or executed by the general VAX instruction set. Initial results indicate that. our system is the fastest implementation of Prolog on a commercrally available general purpose processor. 1. Introduction Various models of execution have been investigated to attain the high performance execution of Prolog programs. Usually, Figure 1. Simplified Block Diagram of the VAX 8600 this involves compiling the Prolog program first into an intermediate form referred to as the Warren Abstract Machine (WAM) instruction set [l]. Execution of WAM instructions often follow one of two methods: they are executed directly by a The 8600 consists of six subprocessors: the EBOX. IBOX, special purpose processor, or they are software emulated via the FBOX. MBOX, Console. and UO adamer. Each of the seuarate machine language of a general purpose computer. -
DHQ11 User Guide
EK -DHQ 11-UG.002 DHQ11 User Guide Prepared by Educational Services of Digital Equipment Corporation Second Edition, July 1987 Copyright © 1987 by Digital Equipment Corporation All Rights Reserved Printed in U.S.A. The information in this document is subject to change without notice. Digital Equipment Corporation assumes no responsibility for any errors herein. The following are trademarks of Digital Equipment Corporation: mmDDmrM DEC MASSBUS RT-l1 DECmate PDP UNIBUS DECsystem-IO PIOS VAX DECSYSTEM-20 Professional VAXBI DECUS Rainbow VMS DECwriter RSTS VT DIBOL RSX Work Processor FALCON CONTENTS PREFACE CHAPTER 1 INTRODUCTION 1.1 SCOPE................................................................. 1-1 1.2 OVERVIEW ........................................................... 1-1 1.2.1 General Description ................................................ 1-1 1.2.1.1 Modem Control Facility ....................................... 1-2 1.2.1.2 Self-Test Facility .............................................. 1-2 1.2.1.3 Diagnostic Programs .......................................... 1-2 1.2.1.4 Preventing Data Loss ......................................... 1-2 1.2.2 Physical Description ............................................... 1-2 1.2.2.1 On-Board Switchpacks ........................................ 1-3 1.2.2.2 Communications Standard ..................................... 1-3 1.2.3 Versions Of The DHQl1 ........................................... 1-4 1.2.4 Configurations ...... Ie. • • •• •• • • • • • • • • • • • • • • • • • • • • • • -
VAX VMS at 20
1977–1997... and beyond Nothing Stops It! Of all the winning attributes of the OpenVMS operating system, perhaps its key success factor is its evolutionary spirit. Some would say OpenVMS was revolutionary. But I would prefer to call it evolutionary because its transition has been peaceful and constructive. Over a 20-year period, OpenVMS has experienced evolution in five arenas. First, it evolved from a system running on some 20 printed circuit boards to a single chip. Second, it evolved from being proprietary to open. Third, it evolved from running on CISC-based VAX to RISC-based Alpha systems. Fourth, VMS evolved from being primarily a technical oper- ating system, to a commercial operat- ing system, to a high availability mission-critical commercial operating system. And fifth, VMS evolved from time-sharing to a workstation environment, to a client/server computing style environment. The hardware has experienced a similar evolution. Just as the 16-bit PDP systems laid the groundwork for the VAX platform, VAX laid the groundwork for Alpha—the industry’s leading 64-bit systems. While the platforms have grown and changed, the success continues. Today, OpenVMS is the most flexible and adaptable operating system on the planet. What start- ed out as the concept of ‘Starlet’ in 1975 is moving into ‘Galaxy’ for the 21st century. And like the universe, there is no end in sight. —Jesse Lipcon Vice President of UNIX and OpenVMS Systems Business Unit TABLE OF CONTENTS CHAPTER I Changing the Face of Computing 4 CHAPTER II Setting the Stage 6 CHAPTER -
Integriti Access Controller (IAC)
Integriti Access Controller (IAC) An IP based master controller The Integriti Access Controller (IAC) is an IP based master controller for the Integriti modular hardware system. The Integriti Access Controller can be used to control and monitor up to 8 Doors or Lift cars on the Integriti RS-485 LAN). The IAC supports two doors/four wiegand and 16 RS485 SIFER readers and is expandable up to eight doors/ eight wiegand readers with the simple addition of 2 Door expander boards via the UniBus in-cabinet expansion interface. Equipped with an Ethernet Port, the IAC can be used both stand alone or expanded further via its UniBus and RS-485 Sub-LAN ports. The flexible, modular design of the IAC’s system parameters and Sub-LAN architecture allows a single standalone controller to be expanded to form a network of RS-485 expansion modules of up to 100,000 Users, 512 Zone Inputs, 250 Areas/ Zone Partitions and up to 80 card readers and 40 Doors. Integriti’s multi-controller architecture allows any number of IAC’s and or ISCs to be combined within the Integriti software package to form a globally managed small, medium or enterprise sized system where the entire network of controllers is managed as a whole. This architecture allows for an infinite number of Readers, Doors, Areas, Zone Inputs and Outputs. Doors Terminals Users LAN Modules Review Events No Smart Card 12 24 10,000 2 60,000 Expanded 40 80 100,000 16 100,000 Key Features Uni-Bus In-Cabinet Expansion ISC On board Features UniBus is an innovative in-cabinet bus which allows the • RJ45 - 10/100 Ethernet Port Ethernet Connected Services • RS-485 Sub-LAN • Connectivity to Integriti Software connection of Expansion devices, Communications devices and • USB Master & Slave Ports • SkyTunnel® Cloud Services & Door & Reader expansion devices on a common Plug & Play • UniBus In-Cabinet Expansion Interface Smart Phone connectivity • Multipath-IP / GSM STU Port (Port bus. -
Vincent M. Weaver Sally A. Mckee
Optimizing for Size: Exploring the Limits of Code Density Sally A. McKee Vincent M. Weaver ASPLOS XIV Poster Session, 8 March 2009 Cornell University Chalmers University of Technology Abstract Hand-Optimized Assembly Results Architectural Size Correlations 0.9020 Minimum possible instruction size Reductions in instruction count can improve cache and bandwidth utiliza- 0.8652 Number of integer registers tion, lower power consumption, and increase overall performance. Nonethe- Total Size of Executable VLIW 2560 RISC less, code density is often overlooked when studying processor architectures. 2048 CISC 0.6623 Architecture has a zero register embedded 1536 8/16-bit 0.5845 Bit-width bytes 1024 We hand-optimize an embedded benchmark for size in assembly language -0.4366 Hardware divide in ALU on 20 different instruction set architectures and investigate the architectural 512 features that contribute most heavily to code density. 0 0.4385 Number of operands in each instruction arm ppc vax sh3 z80 ia64 6502 mips s390 i386 alphaparisc sparc m88k m68k thumb avr32 -0.3356 Unaligned load/store available x86_64 crisv32pdp-11 0.2773 Year the architecture was introduced 256 Size of LZSS Decompression Code VLIW -0.2597 Auto-incrementing addressing scheme Background RISC CISC 192 embedded -0.2597 Hardware status flags (zero/overflow/etc.) 128 8/16-bit bytes -0.1252 Little or Big endian 64 The 20 architectures investigated can be broadly broken into 5 categories: -0.0487 Branch delay slot 0 -0.0079 Maximum possible instruction size Instr Length Opcode arm ppc vax z80 sh3 ia64 mips s390 6502 i386 Type Represented Architectures alpha parisc sparc m88k m68kthumb avr32 (bytes) Args pdp-11 x86_64crisv32 VLIW ia64 16/3 3 Size of String-Search Code VLIW Other Considerations alpha, arm, m88k, mips 256 RISC RISC 4 3 CISC pa-risc, ppc, sparc 192 embedded 128 8/16-bit System libraries and compiler overhead can overshadow the effects of size bytes CISC m68k, s390, vax, x86, x86 64 1-54 2 64 optimization, increasing memory footprint by several orders of magnitude. -
In Using the GNU Compiler Collection (GCC)
Using the GNU Compiler Collection For gcc version 6.1.0 (GCC) Richard M. Stallman and the GCC Developer Community Published by: GNU Press Website: http://www.gnupress.org a division of the General: [email protected] Free Software Foundation Orders: [email protected] 51 Franklin Street, Fifth Floor Tel 617-542-5942 Boston, MA 02110-1301 USA Fax 617-542-2652 Last printed October 2003 for GCC 3.3.1. Printed copies are available for $45 each. Copyright c 1988-2016 Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with the Invariant Sections being \Funding Free Software", the Front-Cover Texts being (a) (see below), and with the Back-Cover Texts being (b) (see below). A copy of the license is included in the section entitled \GNU Free Documentation License". (a) The FSF's Front-Cover Text is: A GNU Manual (b) The FSF's Back-Cover Text is: You have freedom to copy and modify this GNU Manual, like GNU software. Copies published by the Free Software Foundation raise funds for GNU development. i Short Contents Introduction ::::::::::::::::::::::::::::::::::::::::::::: 1 1 Programming Languages Supported by GCC ::::::::::::::: 3 2 Language Standards Supported by GCC :::::::::::::::::: 5 3 GCC Command Options ::::::::::::::::::::::::::::::: 9 4 C Implementation-Defined Behavior :::::::::::::::::::: 373 5 C++ Implementation-Defined Behavior ::::::::::::::::: 381 6 Extensions to -
Unibus: a Universal Hardware Architecture for Serial Bus Interfaces with Real-Time Support
UNIBUS: A UNIVERSAL HARDWARE ARCHITECTURE FOR SERIAL BUS INTERFACES WITH REAL-TIME SUPPORT A THESIS SUBMITTED TO THE GRADUATE SCHOOL OF NATURAL AND APPLIED SCIENCES OF MIDDLE EAST TECHNICAL UNIVERSITY BY MEHDI DUMAN IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE IN ELECTRICAL AND ELECTRONICS ENGINEERING JANUARY 2015 Approval of the thesis: UNIBUS: A UNIVERSAL HARDWARE ARCHITECTURE FOR SERIAL BUS INTERFACES WITH REAL-TIME SUPPORT submitted by MEHDI DUMAN in partial fulfillment of the requirements for the de- gree of Master of Science in Electrical and Electronics Engineering Department, Middle East Technical University by, Prof. Dr. Gülbin Dural Ünver Dean, Graduate School of Natural and Applied Sciences Prof. Dr. Gönül Turhan Sayan Head of Department, Electrical and Electronics Engineering Assoc. Prof. Dr. ¸SenanEce Güran Schmidt Supervisor, Electrical and Electronics Eng. Dept., METU Examining Committee Members: Prof. Dr. Gözde Bozdagı˘ Akar Electrical and Electronics Engineering Dept., METU Assoc. Prof. Dr. ¸SenanEce Güran Schmidt Electrical and Electronics Engineering Dept., METU Assoc. Prof. Dr. Cüneyt F. Bazlamaçcı Electrical and Electronics Engineering Dept., METU Dr. Nizam Ayyıldız ASELSAN,REHIS˙ Dr. Salih Zengin TÜBITAK˙ SAGE Date: I hereby declare that all information in this document has been obtained and presented in accordance with academic rules and ethical conduct. I also declare that, as required by these rules and conduct, I have fully cited and referenced all material and results that are not original to this work. Name, Last Name: MEHDI DUMAN Signature : iv ABSTRACT UNIBUS: A UNIVERSAL HARDWARE ARCHITECTURE FOR SERIAL BUS INTERFACES WITH REAL-TIME SUPPORT Duman, Mehdi M.S., Department of Electrical and Electronics Engineering Supervisor : Assoc.