ABSTRACT Gordon Bell, William Il. Strecker November 8, 1975 COMPUTER STRUCTURES: WHAT HAVE WE LEARNED FROM THE PDP-ll? Over the FDP-11’S six year life behave in a particular way? about 20,000 specimens have been Where does it get inputs? HOW built based on 10 species (models). does it formulate and solve Al though range was a design goal, problems? it was unquantified; the actual range has exceeded expectations 3. The rest of the DEC (5OO:l in memory size and system organization--this includes price]. The range has stressed the applications groups assoc ia ted baa ic mini (mall computer with market groups # sales, architecture along all dimensions. service and manufacturing. The marn PM.5 structure, i.e. the UNIBUS, has been adopted as a de 4. The user, who receives the facto standard of interconnection final OUtQUt. for many micro and minicomputer systems. The architectural Note, that if we assume that a experience gained in the design and QrOduc t is done sequentially, and use of the PDP-11 will be described each stage has a gestation time of in terms Of its environment about two years, it takes roughly (initial goals and constraints, eight years for an idea from basic technology, and the organization research to finally appear at the that designs, builds and user’s site. Other organizations distributes the machine). ala0 affect the design : competitors (they establish a deaign level and determine the product life): and government IsI 1.0 TNTRODUCTTON and standards. There are an ever increasing number Although one might think that of groups who feel compel led to computer architecture is the sole control all products bringing them determinant of a machine, it is all common norm : the merely the focal point for a government (“5) , testing groups such specification.
Integriti Access Controller (IAC) An IP based master controller The Integriti Access Controller (IAC) is an IP based master controller for the Integriti modular hardware system. The Integriti Access Controller can be used to control and monitor up to 8 Doors or Lift cars on the Integriti RS-485 LAN). The IAC supports two doors/four wiegand and 16 RS485 SIFER readers and is expandable up to eight doors/ eight wiegand readers with the simple addition of 2 Door expander boards via the UniBus in-cabinet expansion interface. Equipped with an Ethernet Port, the IAC can be used both stand alone or expanded further via its UniBus and RS-485 Sub-LAN ports. The flexible, modular design of the IAC’s system parameters and Sub-LAN architecture allows a single standalone controller to be expanded to form a network of RS-485 expansion modules of up to 100,000 Users, 512 Zone Inputs, 250 Areas/ Zone Partitions and up to 80 card readers and 40 Doors. Integriti’s multi-controller architecture allows any number of IAC’s and or ISCs to be combined within the Integriti software package to form a globally managed small, medium or enterprise sized system where the entire network of controllers is managed as a whole. This architecture allows for an infinite number of Readers, Doors, Areas, Zone Inputs and Outputs. Doors Terminals Users LAN Modules Review Events No Smart Card 12 24 10,000 2 60,000 Expanded 40 80 100,000 16 100,000 Key Features Uni-Bus In-Cabinet Expansion ISC On board Features UniBus is an innovative in-cabinet bus which allows the • RJ45 - 10/100 Ethernet Port Ethernet Connected Services • RS-485 Sub-LAN • Connectivity to Integriti Software connection of Expansion devices, Communications devices and • USB Master & Slave Ports • SkyTunnel® Cloud Services & Door & Reader expansion devices on a common Plug & Play • UniBus In-Cabinet Expansion Interface Smart Phone connectivity • Multipath-IP / GSM STU Port (Port bus.
Unibus: a Universal Hardware Architecture for Serial Bus Interfaces with Real-Time Support
UNIBUS: A UNIVERSAL HARDWARE ARCHITECTURE FOR SERIAL BUS INTERFACES WITH REAL-TIME SUPPORT A THESIS SUBMITTED TO THE GRADUATE SCHOOL OF NATURAL AND APPLIED SCIENCES OF MIDDLE EAST TECHNICAL UNIVERSITY BY MEHDI DUMAN IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE IN ELECTRICAL AND ELECTRONICS ENGINEERING JANUARY 2015 Approval of the thesis: UNIBUS: A UNIVERSAL HARDWARE ARCHITECTURE FOR SERIAL BUS INTERFACES WITH REAL-TIME SUPPORT submitted by MEHDI DUMAN in partial fulfillment of the requirements for the de- gree of Master of Science in Electrical and Electronics Engineering Department, Middle East Technical University by, Prof. Dr. Gülbin Dural Ünver Dean, Graduate School of Natural and Applied Sciences Prof. Dr. Gönül Turhan Sayan Head of Department, Electrical and Electronics Engineering Assoc. Prof. Dr. ¸SenanEce Güran Schmidt Supervisor, Electrical and Electronics Eng. Dept., METU Examining Committee Members: Prof. Dr. Gözde Bozdagı˘ Akar Electrical and Electronics Engineering Dept., METU Assoc. Prof. Dr. ¸SenanEce Güran Schmidt Electrical and Electronics Engineering Dept., METU Assoc. Prof. Dr. Cüneyt F. Bazlamaçcı Electrical and Electronics Engineering Dept., METU Dr. Nizam Ayyıldız ASELSAN,REHIS˙ Dr. Salih Zengin TÜBITAK˙ SAGE Date: I hereby declare that all information in this document has been obtained and presented in accordance with academic rules and ethical conduct. I also declare that, as required by these rules and conduct, I have fully cited and referenced all material and results that are not original to this work. Name, Last Name: MEHDI DUMAN Signature : iv ABSTRACT UNIBUS: A UNIVERSAL HARDWARE ARCHITECTURE FOR SERIAL BUS INTERFACES WITH REAL-TIME SUPPORT Duman, Mehdi M.S., Department of Electrical and Electronics Engineering Supervisor : Assoc.
PANNON EGYETEM, Veszprém Villamosmérnöki és Információs Rendszerek Tanszék Digitális Rendszerek és Számítógép Architektúrák 7. el őadás: I/O műveletek PCI, PCI Express, SCSI buszok El őadó: Dr. Vörösházi Zsolt voroshazi.zsolt@virt.uni-pannon.hu Jegyzetek, segédanyagok: Könyvfejezetek: http://www.virt.uni-pannon.hu Oktatás Tantárgyak Digitális Rendszerek és Számítógép Architektúrák (Nappali) (chapter06.pdf + további részek, amik a könyvben nem szerepelnek: PCI_bus.pdf, SCSI_bus.pdf ) Fóliák, óravázlatok .ppt (.pdf) Feltöltésük folyamatosan 2 I/O műveletek Aszinkron protokoll Szinkron protokoll Arbitráció (döntési mechanizmus) Megszakítás – kezelés (operációs rendszerek) Buszok – Buszrendszerek: PCI, PCI-Express, SCSI buszok 3 I/O egységek A számítógép a külvilággal, perifériákkal az I/O egységeken keresztül tartja a kapcsolatot. Az információ továbbítását az egységek között buszok végzik, amelyek interfészekkel kapcsolódnak egymáshoz. Interface: azon szabályok összessége, amelyek mind a fizikai megjelenést, kapcsolatot, mind pedig a kommunikációs folyamatokat leírják. Egy busz általában 3 fő kommunikációs vonalból állhat: vezérl őbusz, adatbusz, és címbusz . 4 I/O kommunikációs protokollok: Kommunikáció során megkülönböztetünk egy eszközpárt: a Master -t és Slave -t. A Master (pl. CPU) általában, mint kezdeményez ő, birtokolja és ellen őrzi a buszt, és átadja (ír / olvas) az adatokat a Slave-nek (pl. Memória). A kommunikációhoz el őredefiniált protokollokra (szabályok és konvenciók gy űjteménye) van szükség, amelyek meghatározzák az események sorrendjét és id őzítését. A kommunikáció feltétele a másik egység állapotának pontos ismerete. Lehetséges több M-S modul (pl. multi-master rendszer több kezdeményez ővel) is egy rendszerben. Két alapvet ő protokoll különböztethet ő meg: 1.) Aszinkron kommunikációs (pl. SCSI busz), és 2.) Szinkron kommunikációs (pl. PCI busz) protokoll. 5 Busz rendszer Master-Slave moduljainak szervezése Modul-szervezés Busz-Master (busz- vezérl ő) kommunikál Master Slave a Busz-Slave-el M M M S S (responder).
PDP-11 Unibus Replacement Systems PDP-11 Unibus Replacement System Model NuPDPU 4200 Eliminate Your PDP-11 has been a dependable workhorse for decades, but, Obsolete disks and tapes What do you do if it stops running? High maintenance costs Can you obtain spare parts? Aging, unreliable equipment Do you have knowledgeable staff to troubleshoot Preserve the old system? Existing applications Specialized Unibus I/O interfaces You want to get rid of the high maintenance overhead, but how do you connect a new system to your expensive, hard- Packaging and cables to-replace externally connected equipment? Improve You might be able to replace it all – Speeds 25 times faster than a PDP-11 system, software and external equipment – New equipment, new warranty for a significant capital investment; High performance disk Or, save time and money and choose NuPDP 4200: Unibus Support Retain your investment in software. Support for multiple Unibus devices Preserve your investment in external equipment. Follows all Unibus rules and specifications Migrate to a brand new system with a new Both Unibus PIO and DMA data transers are warranty. supported as well as all three Unibus interrupts Unibus PIO and DMA data transfers occur at NuPDP 4200 is a modern, industry-standard system that replaces the PDP-11 chassis, CPU, memory, and mass maximum Unibus speeds; throughput is limited only storage. Your current PDP-11 disk images can be by the Unibus device(s) transferred onto a NuPDP system running your existing operating system and applications. PDP-11 Compatibility Software compatible with existing applications You can select from a variety of new technology controllers such as the DR11-W, DR11-C, and DHU to replace popular Hardware compatible legacy Unibus interfaces.
Datadoc - DEC/VAX 7xx0/10xx0 This section by Dave Bazley..... Revision: Written July 1993, updated January 1994, August 1994, April 1995. 1 Introduction This section contains information on the following systems: DEC7xx0, DEC10xx0, VAX7xx0 and VAX10xx0. The basic 7000 and 10000 boxes, or platforms, can be configured to support either VAX architecture (the 32 bit, CISC based one, you know about, that made us great in the ’80s) or Alpha AXP architecture (the 64 bit, RISC based one, you’ve heard about, that’s going to make us great again!) The DECxxxx(x) systems are AXP based, the VAXxxxx(x) systems are VAX based. The 7000s are single cabinet systems and were designed as a replacement for VAX 6000s. For this reason they are described as "departmental" and sometimes termed "VAX 6000 style". However, read on to discover how different they actually are. The 10000s are multi-cabinet systems designed as a replacement for VAX 9000s. They are described as "datacentre" systems. The fact that all these systems can start off as VAXes and be simply upgraded to AXPs later, makes migrating from one architecture to the other easier for customers. As additional models and options appear, I expect this section to evolve and expand. Any suggestions for improvement would be welcome. 1.1 Codenames System Code name Architecture DEC 7xx0 Laser (Ruby) Alpha AXP DEC 10xx0 Blaser (Ruby) Alpha AXP VAX 7xx0 Laser (Neon) VAX/VMS VAX 10xx0 Blaser (Neon) VAX/VMS LASER: Light Amplified by Stimulated Emission of Radiation BLASER: Sounds like a jacket, first worn by sailors on HMS Blazer, but actually stands for Big laser.
03 Top Level View of Computer Function and Interconnection
William Stallings Computer Organization and Architecture 8th Edition Chapter 3 Elements of Bus Design What is a Bus? • A communication pathway connecting two or more devices • Usually broadcast • Often grouped —A number of channels in one bus —32 bit data bus is 32 separate single bit channels • What do buses look like? —Parallel lines on circuit boards —Ribbon cables —Strip connectors on mother boards (e.g. PCI) —Sets of wires Buses • There are a # of possible interconnection systems • Single and multiple BUS structures are most common • e.g. Control/Address/Data bus (PC) • e.g. Unibus (DEC-PDP) Connecting • All the units must be connected • Different type of connection for different type of units —Memory —Input/Output —CPU Bus Interconnection Scheme Definition of a Bus Bus lines - Digital interconnection mechanism • Transfer of data - A set of parallel wires with rules for putting • Address information and retrieving information on the wires. • Control of the bus - A digital communication mechanism that – Memory fetch or store allows two or more functional units to transfer – Ready control signals or data. – Bus Request and Bus Grant - The connection medium allowing the CPU, – Interrupt and Interrupt Acknowledge memory and I/O controllers to communicate – Clock Memory Connection • Receives and sends data • Receives addresses (of locations) • Receives control signals —Read —Write —Timing N words of = length. Each word is assigned a unique numerical address. A word can be read from or written into memory. The nature of operation is indicated by read and write control signals. The location for the operation is specified by an address Input/Output Connection • Output - Receive data from computer - Send data to peripheral • Input - Receive data from peripheral or send data to computer • Receive control signals from computer • Send control signals to peripherals (spin disk) • Receive addresses from computer —e.g.
Oo/OF - " - 7 SuLniiitted to tHe Third Biennial Conference on Real-Time Computer Applications in Nuclear & Particle Physics, Berkeley,:CA "" Kay 16-19, 1983 BROOKHAVEN FASTBUS/UNIBUS INTERFACE 3 NL 33165 G. Benenson, J. Bauecnfeind, R.C. Larsen, L.8. Lelpuner, and W.H.Morse* BNL--3 316 5 Brookhaven National laboratory Associated Universities, Inc. Upton, New York 11973 DB83 014434 R.K. Adair, J.K. Black, S.R. Campbell, H. Kasha, and H.P. Schmidt Tale University New Haven, Connecticut 06511 I. Summary CONTROL signals are needed to determine which of many A typical high energy physics experiment re- potential masters will actually assume mastership quires both a high speed data acquisiton and proces- during a particular time slot on the bus. ADDRESS sing system, for data collection and reduction; and a Information is used to select which of many potential general purpose computer to handle further reduction, slaves will actually respond io the current master. bookkeeping and mass storage. Broad differences in architecture, format or technology, will often exist between these two systems, and Interface design can become a formidable task. A. ONE-TO-ONE The PDP-11 series minicomputer is widely used in physics research, and the Brookhaven FASTBUS is the only standard high speed data acquisition system which Is fully Implemented in a current high energy physics experiment, this paper will describe the design and operation of an interface between these two-systems. The major issues are elucidated by a preliminary discussion on the basic principles of Bus Systems, and their application to Brookhaven FASTBUS and UMIBUS.