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Engineering Specification for the KA43 Processor Module Revision 1.0 1–May–1989 COMPANY CONFIDENTIAL RESTRICTED DISTRIBUTION
Engineering Specification for the KA43 Processor Module Revision 1.0 1–May–1989 COMPANY CONFIDENTIAL RESTRICTED DISTRIBUTION COPYRIGHT (c) 1989 by DIGITAL EQUIPMENT CORPORATION This information shall not be disclosed to non-Digital personnel or generally distributed within Digital. Distribution is restricted to persons authorized and designated by the responsible en- gineer or manager. This document shall not be left unattended, and when not in use shall be stored in a locked storage container. The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may occur in this document. The information in this document does not describe any program or product currently available from Digital Equipment Corporation. Nor does Digital Equipment Corporation commit to imple- ment this specification in any program or product. Digital Equipment Corporation makes no commitment that this document accurately describes any product which it might ever make. Digital Equipment Corporation CONTENTS Preface . ........................................................... v Chapter 1 INTRODUCTION .............................................. 1 1.1 Scope of Document ................................................... 1 1.2 General Description .................................................. 1 1.3 Applicable Documents ................................................. 2 Chapter 2 KA43 ROM MEMORY ........................................ -
Pdp11-40.Pdf
processor handbook digital equipment corporation Copyright© 1972, by Digital Equipment Corporation DEC, PDP, UNIBUS are registered trademarks of Digital Equipment Corporation. ii TABLE OF CONTENTS CHAPTER 1 INTRODUCTION 1·1 1.1 GENERAL ............................................. 1·1 1.2 GENERAL CHARACTERISTICS . 1·2 1.2.1 The UNIBUS ..... 1·2 1.2.2 Central Processor 1·3 1.2.3 Memories ........... 1·5 1.2.4 Floating Point ... 1·5 1.2.5 Memory Management .............................. .. 1·5 1.3 PERIPHERALS/OPTIONS ......................................... 1·5 1.3.1 1/0 Devices .......... .................................. 1·6 1.3.2 Storage Devices ...................................... .. 1·6 1.3.3 Bus Options .............................................. 1·6 1.4 SOFTWARE ..... .... ........................................... ............. 1·6 1.4.1 Paper Tape Software .......................................... 1·7 1.4.2 Disk Operating System Software ........................ 1·7 1.4.3 Higher Level Languages ................................... .. 1·7 1.5 NUMBER SYSTEMS ..................................... 1-7 CHAPTER 2 SYSTEM ARCHITECTURE. 2-1 2.1 SYSTEM DEFINITION .............. 2·1 2.2 UNIBUS ......................................... 2-1 2.2.1 Bidirectional Lines ...... 2-1 2.2.2 Master-Slave Relation .. 2-2 2.2.3 Interlocked Communication 2-2 2.3 CENTRAL PROCESSOR .......... 2-2 2.3.1 General Registers ... 2-3 2.3.2 Processor Status Word ....... 2-4 2.3.3 Stack Limit Register 2-5 2.4 EXTENDED INSTRUCTION SET & FLOATING POINT .. 2-5 2.5 CORE MEMORY . .... 2-6 2.6 AUTOMATIC PRIORITY INTERRUPTS .... 2-7 2.6.1 Using the Interrupts . 2-9 2.6.2 Interrupt Procedure 2-9 2.6.3 Interrupt Servicing ............ .. 2-10 2.7 PROCESSOR TRAPS ............ 2-10 2.7.1 Power Failure .............. -
Validated Products List, 1995 No. 3: Programming Languages, Database
NISTIR 5693 (Supersedes NISTIR 5629) VALIDATED PRODUCTS LIST Volume 1 1995 No. 3 Programming Languages Database Language SQL Graphics POSIX Computer Security Judy B. Kailey Product Data - IGES Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 July 1995 QC 100 NIST .056 NO. 5693 1995 NISTIR 5693 (Supersedes NISTIR 5629) VALIDATED PRODUCTS LIST Volume 1 1995 No. 3 Programming Languages Database Language SQL Graphics POSIX Computer Security Judy B. Kailey Product Data - IGES Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 July 1995 (Supersedes April 1995 issue) U.S. DEPARTMENT OF COMMERCE Ronald H. Brown, Secretary TECHNOLOGY ADMINISTRATION Mary L. Good, Under Secretary for Technology NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY Arati Prabhakar, Director FOREWORD The Validated Products List (VPL) identifies information technology products that have been tested for conformance to Federal Information Processing Standards (FIPS) in accordance with Computer Systems Laboratory (CSL) conformance testing procedures, and have a current validation certificate or registered test report. The VPL also contains information about the organizations, test methods and procedures that support the validation programs for the FIPS identified in this document. The VPL includes computer language processors for programming languages COBOL, Fortran, Ada, Pascal, C, M[UMPS], and database language SQL; computer graphic implementations for GKS, COM, PHIGS, and Raster Graphics; operating system implementations for POSIX; Open Systems Interconnection implementations; and computer security implementations for DES, MAC and Key Management. -
Mobile Digital Computer Program. Mobidic D
UNCLASSIFIED AD 4 7_070 DEFENSE DOCUMEI'TATION CENTER FOR SCIENTIFIC AND TECHNIA!. INFO'UMATION CAMERON STATION, ALEXANDRW , VIFGINI, UNCLASSIFIED NOTICE: When government or other drawings, speci- fications or other data are used for any purpose other than in connection with a definitely related government procurement operation, the U. S. Government thereby incurs no responsibility, nor any obligation whatsoever; and the fact that the Govern- ment may have formulated, furnished, or in any way supplied the said drawings, specifications, or other data is not to be regarded by implication or other- wise as in any manner licensing the holder or any other person or corporation, or conveying any rights or permission to manufacture, use or sell any patented invention that may in any way be related thereto. FINAL REPORT 1 FEBRUARY 1963 J a I MOBILE DIGITAL COMPUTER PROGRAM MOBIDIC D FINAL REPORT 1 July 1958 to 1 February 1963 I Signal Corps Technical Requirements I SCL 1959 SCL 4328 Contract No. DA 3 6 -039-sc-781 6 4 I DA Project No. 3-28-02-201 I Submitted by: _, _ _ _ E. W. Jer'7is, Manage'r MOBIDIC Projects February 1963 S SYLVANIA ELECTRONIC SYSTEMS-EAST SYLVANIA ELECTRONIC SYSTEMS A Division of Sylvania Electric Products Inc. 189 B Street-Needham Heights 94, Massachusetts ~• I 3 TABLE OF CONTENTS I Section Page LIST OF ILLUSTRATIONS v ILIST OF TABLES vii I PURPOSE 1-1 1U1.1 MOBIDIC D General Purpose High-Speed Computer 1-1 1.2 MOBIDIC D Program 1-1 11.2. 1 Phase I -Preliminary Design 1-1 1.2.2 Phase II-Design 1-1 1.2.3 Phase III-Construction and Test 1-2 1.2.4 Phase IV-Update MOBIDIC D to MOBIDIC 7A 1-2 I 1.2.5 Phase V-Van Installation and Test 1,-2 II ABSTRACT 2-1 III PUBLICATIONS, LECTURES, CONFERENCES & TERMINOLOGY 3-1 3.1 Publications 3-1 T3.2 Lectures 3-1 3.3 Conferences 3-2 3.4 Terminology and Abbreviations 3-10 S3.4.1 Logical and Mechanization Designations: 3-13 Central Machine and Converter S3.4.2 Logical and Mechanization Designations: - 3-45 Card Reader and Punch Buffer 3.4. -
A Screen Oriented Simulator for a DEC PDP-8 Computer
University of Wollongong Research Online Department of Computing Science Working Faculty of Engineering and Information Paper Series Sciences 1983 A screen oriented simulator for a DEC PDP-8 computer Neil Gray University of Wollongong, [email protected] Follow this and additional works at: https://ro.uow.edu.au/compsciwp Recommended Citation Gray, Neil, A screen oriented simulator for a DEC PDP-8 computer, Department of Computing Science, University of Wollongong, Working Paper 83-2, 1983, 65p. https://ro.uow.edu.au/compsciwp/69 Research Online is the open access institutional repository for the University of Wollongong. For further information contact the UOW Library: [email protected] THE UNIVERSITY OF WOlLONGONG DEPARTMENT OF COMPUTING SCIENCE A SCREEN ORIENTED SIMULATOR FOR A DEC PDP-8 COMPUTER .". N.A.B. Gray Department of Computing Science University of Wollongong Preprlnt No 83-2 January 25. 1983 P.O. Box 1144. WOLLONGONG. N.S.W. AUSTRALIA telephone (042)-282-981 telex AA29022 A Screen Oriented Simulator for a DEC PDP-8 computer. N.A.B. Gray. Department of Computing Science. University of Wollongong. PO Box 1144. WOllongong NSW 2500. Austr"1lia. ABSTRACT This note describes a simulator for the DEC PDP-8 computer. The simulator is intended as an aid tor students starting to learn assemDly language programming. It utilises the simple graphIcs capaDilities of the terminals in the department's laboratories to present. on the termI nal screen. a view of the operations of the simulated computer. The complete system comprises two versions at me program tor simulating a PDP-8 computer and a simplified "assembler" tor prepar Ing students' programs for execution. -
The Design and Verification of the Alphastation 600 5-Series Workstation by John H
The Design and Verification of the AlphaStation 600 5-series Workstation by John H. Zurawski, John E. Murray, and Paul J. Lemmon ABSTRACT The AlphaStation 600 5-series workstation is a high-performance, uniprocessor design based on the Alpha 21164 microprocessor and on the PCI bus. Six CMOS ASICs provide high-bandwidth, low-latency interconnects between the CPU, the main memory, and the I/O subsystem. The verification effort used directed, pseudorandom testing on a VERILOG software model. A hardware-based verification technique provided a test throughput that resulted in a significant improvement over software tests. This technique currently involves the use of graphics cards to emulate generic DMA devices. A PCI hardware demon is under development to further enhance the capability of the hardware-based verification. INTRODUCTION The high-performance AlphaStation 600 5-series workstation is based on the fastest Alpha microprocessor to date -- the Alpha 21164.[1] The I/O subsystem uses the 64-bit version of the Peripheral Component Interconnect (PCI) and the Extended Industry Standard Architecture (EISA) bus. The AlphaStation 600 supports three operating systems: Digital UNIX (formerly DEC OSF/1), OpenVMS, and Microsoft's Windows NT. This workstation series uses the DECchip 21171 chip set designed and built by Digital. These chips provide high-bandwidth, low-latency interconnects between the CPU, the main memory, and the PCI bus. This paper describes the architecture and features of the AlphaStation 600 5-series workstation and the DECchip 21171 chip set. The system overview is first presented, followed by a detailed discussion of the chip set. The paper then describes the cache and memory designs, detailing how the memory design evolved from the workstation's requirements. -
PDP-8 Simulator Manual
PDP-8 Simulator Usage 30-Apr-2020 COPYRIGHT NOTICE The following copyright notice applies to the SIMH source, binary, and documentation: Original code published in 1993-2016, written by Robert M Supnik Copyright (c) 1993-2016, Robert M Supnik Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. Except as contained in this notice, the name of Robert M Supnik shall not be used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from Robert M Supnik. 1 Simulator Files.............................................................................................................................3 -
Go Forth with TTL !
Go Forth with TTL ! The Gigatron TTL Color Computer Forth for a Very Unusual Processor Ken Boak SV Fig. Forth Day 2019 . In September of 1975, MOS Technology launched the 6502 at the Wescon75 Computer Conference in San Francisco. Chuck Peddle and his team had created a very lean, stripped down, small die cpu. Costing just $25, the 6502 was a fraction of the cost of its nearest competitor. At that time the Intel 8080 was $360 and the Motorola 6800 was $175 . The 6502 was clearly a disruptive usurper. 25 year old, HP Engineer, Steve Wozniak, realised that this new microprocessor would be a game-changer and went on to incorporate it into the small computer he was developing. That machine went on to become the Apple I. In 1975 7400 TTL was the “Bread and Butter” of logic design: 7400 series TTL integrated circuits were developed in the early 1960’s. Initially quite expensive so mainly used in Military and Aerospace applications. By the early 1970’s TTL had become a versatile family of standardised, low cost,. easy to use logic. Typically about $1 per device. 7400 series logic was widely used in the design of minicomputers, including the PDP-11, the Data General Nova 1200 and later models of PDP-8. TTL was a viable, faster and cheaper processing solution than the emerging 8-bit microprocessors such as MOS 6502, Intel 8080 and the Motorola 6800. Essential Reading 16-bit TTL CPU board from Data General Nova 1200 The Gigatron TTL Computer – What is it? Started as a Hackaday.io project in Spring 2017 by Marcel van Kervinck of The Hague, Netherlands. -
Procurement and Retrieval - Meeting the Challenge"
UNCLASSIFIED AD NUMBER AD493137 NEW LIMITATION CHANGE TO Approved for public release, distribution unlimited FROM Distribution authorized to U.S. Gov't. agencies and their contractors; Administrative/Operational Use; 10 JUN 1964. Other requests shall be referred to Bureau of Naval Weapons, Washington, DC. AUTHORITY USNOL ltr, 26 Nov 1969 THIS PAGE IS UNCLASSIFIED NOLTR 64-98 PkOCEEDINGS OF THE 7th MILITARY LIBRARIANS' WORKSHOP "Procurement and Retrieval - Meeting the Challenge" - 0 40 :- =7 - r cOm 1963 No2,3,4 UNITED STATES ,,:,,NAVAL ORDNANCE LABORATORY, WHITE OAK, MARYLAND co I- 0 NOLTR 64-98- PROCEEDINGS OF THE SEVENTH MILITARY LIBRARIANS' WORKSHOP "Procurement and Retrieval - Meeting the Challenge" ABSTRACT: Papers presented at the Workshop on library operation make up the Proceedings. A panel on the Army STINFO program and one on procurement were important contributions to the Work- shop. Two sessions were devoted to library operation - one using computer, the other using automated equipment. Questions and answers at the end of the talks are included. U. S. NAVAL ORDNANCE LABORATORY WHITE OAK, MARYLAND V77 7. NOLTR\64-98 NOLTR 64-98 10 June 1964 PROCEEDINGS OF THE SEVENTH MILITARY LIBRARIANS' WORKSHOP "Procurement and Retrieval - Meeting the Challenge" The Naval Ordnance Laboratory was host to the Seventh Military Librarians' Workshop on 2 - 4 October 1963. These Proceedings are the record of the meeting, including papers presented, and recordings of discussion which followed the talks. The business meeting of the Group, which was held on 4 October, is included in the Proceedings. R. E. 0DENING LAN BECK By directio ii A# NOLTR 64-98 I CONTENTS Page INTRODUCTION ................. -
Computer Organization EECC 550 • Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Week 1 Notation (RTN)
Computer Organization EECC 550 • Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Week 1 Notation (RTN). [Chapters 1, 2] • Instruction Set Architecture (ISA) Characteristics and Classifications: CISC Vs. RISC. [Chapter 2] Week 2 • MIPS: An Example RISC ISA. Syntax, Instruction Formats, Addressing Modes, Encoding & Examples. [Chapter 2] • Central Processor Unit (CPU) & Computer System Performance Measures. [Chapter 4] Week 3 • CPU Organization: Datapath & Control Unit Design. [Chapter 5] Week 4 – MIPS Single Cycle Datapath & Control Unit Design. – MIPS Multicycle Datapath and Finite State Machine Control Unit Design. Week 5 • Microprogrammed Control Unit Design. [Chapter 5] – Microprogramming Project Week 6 • Midterm Review and Midterm Exam Week 7 • CPU Pipelining. [Chapter 6] • The Memory Hierarchy: Cache Design & Performance. [Chapter 7] Week 8 • The Memory Hierarchy: Main & Virtual Memory. [Chapter 7] Week 9 • Input/Output Organization & System Performance Evaluation. [Chapter 8] Week 10 • Computer Arithmetic & ALU Design. [Chapter 3] If time permits. Week 11 • Final Exam. EECC550 - Shaaban #1 Lec # 1 Winter 2005 11-29-2005 Computing System History/Trends + Instruction Set Architecture (ISA) Fundamentals • Computing Element Choices: – Computing Element Programmability – Spatial vs. Temporal Computing – Main Processor Types/Applications • General Purpose Processor Generations • The Von Neumann Computer Model • CPU Organization (Design) • Recent Trends in Computer Design/performance • Hierarchy -
Cpu Identification Program. P?S Pal V08s Sat 11-Mar-17 Page 1
/ CPU IDENTIFICATION PROGRAM. P?S PAL V08S SAT 11-MAR-17 PAGE 1 1 1 / CPU IDENTIFICATION PROGRAM. 1 2 2 2 3 3 / LAST EDIT: 03-OCT-2016 CJL 3 4 4 4 5 5 / MUST BE ASSEMBLED WITH THE '/J' COMMAND-LINE SWITCH OFF IN P?S/8 PAL OR THE 5 6 6 / '/F' COMMAND-LINE SWITCH OFF IN OS/8 PAL8. 6 7 7 7 8 8 / THIS PROGRAM IDENTIFIES THE PARTICULAR MODEL OF PDP-8 THE PROGRAM IS RUNNING 8 9 9 / ON. THIS IS ACCOMPLISHED USING A SERIES OF TESTS FOR QUIRKS THAT APPLY TO THE 9 10 10 / VARIOUS MODELS. 10 11 11 11 12 12 / NOTE: MUCH OF THE CODE IN THIS PROGRAM WAS OBTAINED FROM THE KERMIT-12 SOURCE 12 13 13 / FILES; SOME MODIFICATIONS HAVE BEEN MADE THAT WILL EVENTUALLY BE APPLIED TO 13 14 14 / KERMIT-12 TO BETTER IDENTIFY THE COMPUTER. NOTE: KERMIT-12 USES A 14 15 15 / MODEL-DEPENDENT COMMAND PROMPT TO HELP ASSIST IN DETERMINING WHICH KERMIT IS 15 16 16 / CURRENTLY BEING ADDRESSED; IN CERTAIN CIRCUMSTANCES, TWO DIFFERENT SYSTEMS ARE 16 17 17 / IN USE. IT CAN SOMETIMES BE CONFUSING WHICH COMPUTER IS CURRENTLY IN EFFECT, 17 18 18 / THUS, USING MODEL-SPECIFIC PROMPTS CAN AID IN PREVENTING CONFUSION. AS 18 19 19 / CURRENTLY IMPLEMENTED AS OF THIS WRITING, KERMIT-12 CANNOT QUITE DISTINGUISH 19 20 20 / BETWEEN DECMATE SYSTEMS AND OTHER SYSTEMS BASED ON THE 6120 CHIP SUCH AS THE 20 21 21 / CPU-8 OR GIZMO. WHILE THIS ASPECT OF THE PROBLEM IS PURELY COSMETIC, 21 22 22 / KERMIT-12 HAS CONFIGURATION ISSUES WHEN RUN ON THESE PARTICULAR SYSTEMS. -
The Origins of Word Processing and Office Automation
Remembering the Office of the Future: The Origins of Word Processing and Office Automation Thomas Haigh University of Wisconsin Word processing entered the American office in 1970 as an idea about reorganizing typists, but its meaning soon shifted to describe computerized text editing. The designers of word processing systems combined existing technologies to exploit the falling costs of interactive computing, creating a new business quite separate from the emerging world of the personal computer. Most people first experienced word processing using a word processor, we think of a software as an application of the personal computer. package, such as Microsoft Word. However, in During the 1980s, word processing rivaled and the early 1970s, when the idea of word process- eventually overtook spreadsheet creation as the ing first gained prominence, it referred to a new most widespread business application for per- way of organizing work: an ideal of centralizing sonal computers.1 By the end of that decade, the typing and transcription in the hands of spe- typewriter had been banished to the corner of cialists equipped with technologies such as auto- most offices, used only to fill out forms and matic typewriters. The word processing concept address envelopes. By the early 1990s, high-qual- was promoted by IBM to present its typewriter ity printers and powerful personal computers and dictating machine division as a comple- were a fixture in middle-class American house- ment to its “data processing” business. Within holds. Email, which emerged as another key the word processing center, automatic typewriters application for personal computers with the and dictating machines were rechristened word spread of the Internet in the mid-1990s, essen- processing machines, to be operated by word tially extended word processing technology to processing operators rather than secretaries or electronic message transmission.