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Pdp11-40.Pdf processor handbook digital equipment corporation Copyright© 1972, by Digital Equipment Corporation DEC, PDP, UNIBUS are registered trademarks of Digital Equipment Corporation. ii TABLE OF CONTENTS CHAPTER 1 INTRODUCTION 1·1 1.1 GENERAL ............................................. 1·1 1.2 GENERAL CHARACTERISTICS . 1·2 1.2.1 The UNIBUS ..... 1·2 1.2.2 Central Processor 1·3 1.2.3 Memories ........... 1·5 1.2.4 Floating Point ... 1·5 1.2.5 Memory Management .............................. .. 1·5 1.3 PERIPHERALS/OPTIONS ......................................... 1·5 1.3.1 1/0 Devices .......... .................................. 1·6 1.3.2 Storage Devices ...................................... .. 1·6 1.3.3 Bus Options .............................................. 1·6 1.4 SOFTWARE ..... .... ........................................... ............. 1·6 1.4.1 Paper Tape Software .......................................... 1·7 1.4.2 Disk Operating System Software ........................ 1·7 1.4.3 Higher Level Languages ................................... .. 1·7 1.5 NUMBER SYSTEMS ..................................... 1-7 CHAPTER 2 SYSTEM ARCHITECTURE. 2-1 2.1 SYSTEM DEFINITION .............. 2·1 2.2 UNIBUS ......................................... 2-1 2.2.1 Bidirectional Lines ...... 2-1 2.2.2 Master-Slave Relation .. 2-2 2.2.3 Interlocked Communication 2-2 2.3 CENTRAL PROCESSOR .......... 2-2 2.3.1 General Registers ... 2-3 2.3.2 Processor Status Word ....... 2-4 2.3.3 Stack Limit Register 2-5 2.4 EXTENDED INSTRUCTION SET & FLOATING POINT .. 2-5 2.5 CORE MEMORY . .... 2-6 2.6 AUTOMATIC PRIORITY INTERRUPTS .... 2-7 2.6.1 Using the Interrupts . 2-9 2.6.2 Interrupt Procedure 2-9 2.6.3 Interrupt Servicing ............ .. 2-10 2.7 PROCESSOR TRAPS ............ 2-10 2.7.1 Power Failure ............... 2-10 2.7.2 Odd Addressing Errors ... ......... 2-10 2.7.3 Time-out Errors ...... 2·11 2.7.4 Reserved Instructions 2-11 2.7.5 Trap Handling ........... 2-11 iii CHAPTER 3 ADDRESSING MODES .............................................. 3·1 3.1 SINGLE OPERAND ADDRESSING ...................... ......... 3·2 3.2 DOUBLE OPERAND ADDRESSING ................................ ~-2 3.3 DIRECT ADDRESSING .. .. .. .. .. .. .. ... .. .. .. .. ... .. ... ... ... 3-4 3.3.1 Register Mode .................................................. 3·4 3.3.2 Auto-increment Mode . .. .. .. .. .. .. .. .. 3·5 3.3.3 Auto-decrement Mode ...................................... 3·7 3.3.4 Index Mode . .. .. .. .. .. .. .. 3·8 3.4 DEFERRED (INDIRECT) ADDRESSING ......................... 3·10 3.5 USE OF THE PC AS A GENERAL REGISTER ................ 3·12 3.5.1 Immediate Mode................................................ 3·13 3.5.2 Absolute Addressing .. ......... ............................... 3·13 3.5.3 Relative Addressing ....... .................................. 3·14 3.5.4 Relative Deferred Addressing .. .. .. .. .. .. .. 3·15 3.6 USE OF STACK POINTER AS GENERAL REGISTER ...... 3·16 3.7 SUMMARY OF ADDRESSING MODES .......................... 3·16 3.7.1 General· Register Addressing ............................ 3·16 3.7.2 Program Counter Addressing ............................ 3·18 CHAPTER 4 INSTRUCTION SET . .. .. .. 4·1 4.1 INTRODUCTION ............................................................ 4·1 4.2 INSTRUCTION FORMATS .. .. ...... ... ................................ 4·2 4.3 LIST OF INSTRUCTIONS . .. ... .. .. .. .. .. .. 4·4 4.4 SINGLE OPERAND INSTRUCTIONS . .. .. .. .. .. .. .4·6 4.5 .DOUBLE OPERAND INSTRUCTIONS ............... .. ....... .... 4·22 4.6· PROGRAM CONTROL INSTRUCTIONS ..... ............ ......... 4·36 4.7 MISCELLANEOUS ..... ..................................................... 4·74 CHAPTER 5 PROGRAMMING TECHNIQUES ................................ 5·1 5.1 THE STACK .................................................................. 5·1 5.2 SUBROUTINE LINKAGE ................................. ............... 5·5 5.2.1 Subroutine Calls .... ........................................... 5·5 5.2.2 Argument Transmission . .. .. .. .. .. .. .. .. ... .. 5·6 5.2.3 Subroutine Return . .. .. .. .. 5·9 5.2.4 PDP·ll Subroutine Advantage .......................... 5·9 5.3 INTERRUPTS . ... ... .... .. .. .. ... .. .. .. .. .. ... .. .. ....... .. ... 5·9 5.3.1 General Principles ............................................ 5·9 5.3.2 Nesting ..... .................. ....................................... 5·10 5.4 REENTRANCY ................................................................ 5·13 5.5 POSITION INDEPENDENT CODE .................................. 5·15 5.6 CO· ROUTINES ........... .......... ........... ................................ 5·16 5.7 MULTI-PROGRAMMING ................................................ 5·17 5.7.1 Control Information .......................................... 5·17 5.7.2 Data .................................................................. 5·17 5.7.3 Processor Status Word ...................................... 5·17 iv CHAPTER 6 MEMORY MANAGEMENT 6.1 PDP-11 FAMILY BASIC ADDRESSING LOGIC ............... 6-1 6.2 VIRTUAL ADDRESSING .... ...................... 6-2 6.3 INTERRUPT CONDITIONS UNDER MANAGEMENT CONTROL....................................................................... 6-2 6.4 CONSTRUCTION OF A PHYSICAL ADDRESS ............... 6-3 6.5 MANAGEMENT REGISTERS ........................................... 6-4 6.5.1 Page Address Register...................................... 6-5 6.5.2 Page Descriptor Register ........ ........................... 6-5 6.6 FAULT REGISTERS .. ............................. ...................... 6-7 6.6.1 Status Register #0 ........................................... 6-7 6.6.2 Status Register #2 ........................................... 6-8 CHAPTER 7 INTERNAL PROCESSOR OPTIONS 7.1 GENERAL ....................................................................... 7-1 7.2 EIS OPTION ................................................................... 7-1 7.3 FLOATING POINT OPTION ............................................. 7-3 7.4 STACK LIMIT OPTION ....... ........................................... 7-5 CHAPTER 8 CONSOLE OPERATION 8.1 CONSOLE ELEMENTS ................. ................................. 8-1 8.2 STATUS INDICATORS ................................................... 8·2 8.3 CONSOLE SWITCHES.................................................... 8-3 8.4 DISPLAYS....................................................................... 8-4 CHAPTER 9 SPECIFICATIONS 9.1 PACKAGING ................................................................... 9-1 9.2 CPU OPERATING SPECIFICATIONS ............................... 9-1 9.3 OTHER EQUIPMENT ..................................................... 9-1 9.4 PDP-11 FAMILY OF COMPUTERS ................................. 9-4 Appendix A Instruction Set Processor ........................................ A-1 Appendix B Memory Map ............................................................ 8·1 Appendix C PDP-11/40 Instruction Timing .................................. C-1 Appendix D Instruction Index and Numerical Op Code List ........ D-1 Appendix E Summary of PDP11 Instructions .............................. E-1 v vi CHAPTER 1 INTRODUCTION 1.1 GENERAL The PDP-11 family includes several central processors, a large number of peripheral devices and options, and extensive software. PDP-11 com· puters have similar architecture and are hardware and software upwards compatible, although each machine has some of its own characteristics. New systems will be compatible with existing family members. The user can choose the system which is most suitable for his application, but as needs change or grow he can easi!y add or change hardware. This Handbook describes the PDP-11/40, one of the latest computers in the PDP-11 family from Digital Equipment Corporation (DEC). This powerful, low-priced machine is packaged in a 21·'' front panel slide chassis, allowing convenient access and expansion when mounted in a standard rack. The PDP-11/40 was designed to fit a broad range of applications, from small stand alone situations where the computer con­ sists of only 8K of memory and a processor, to large multi-user, multi­ task applications requiring up to 124K of addressable memory space. Among its major features are a fast central processor with a choice of floating point and sophisticated memory management, both of which are hardware options. Some of the PDP-11/40 features are: • 16-bit word (two 8-bit bytes) direct addressing of 32K 16-bit words or 64K 8-bit bytes (K = 1024) • Word or byte processing very efficient handling of 8-bit characters • Asynchronous operation systems run at their highest possible speed, replacement with faster devices means faster operation with no other hardware or software changes • Modular component design extreme ease and flexibility in configuring systems • Stack Processing hardware sequential memory manipulation makes it easy to handle structured data, subroutines, and interrupts 1·1 • 8 fast general-purpose registers very fast integrated circuits used in tera:tively for instruction processing • Automatic priority processing four-line, multi-level system is dynamically alterable • Vectored interrupts fast interrupt response without device polling • Single & double operand instructions powerful and convenient set of micro-programmed instructions DEC References The following publications contain supplementary and useful information: Title PDP-11 Peripherals and Interfacing Handbook PDP-11 UNIBUS Interface Manual Introduction to Programming Small Computer
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