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CS61C : Machine Structures •Remember: “Load from Memory”

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CS61C : Machine Structures •Remember: “Load from Memory” inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Review Lecture 9 – Introduction to MIPS • In MIPS Assembly Language: Data Transfer & Decisions I • Registers replace C variables • One Instruction (simple operation) per line • Simpler is Better, Smaller is Faster Lecturer PSOE Dan Garcia • New Instructions: www.cs.berkeley.edu/~ddgarcia add, addi, sub Future HVD 1 TB disks! ⇒ The future of digital storage • New Registers: (past the DVD, Blu-Ray and HD DVD) C Variables: $s0 - $s7 may be the Holographic Versatile Disc. Temporary Variables: $t0 - $t7 A massive 1 TB on each (200 DVDs)! 1TB www.zdnet.com.au/news/hardware/0,2000061702,39180148,00.htm Zero: $zero CS61C L09 Introduction to MIPS: Data Transfer & Decisions I (1) Garcia © UCB CS61C L09 Introduction to MIPS: Data Transfer & Decisions I (2) Garcia © UCB Assembly Operands: Memory Anatomy: 5 components of any Computer Registers are in the datapath of the • C variables map onto registers; what processor; if operands are in memory, about large data structures like arrays? Personal Computer we must transfer them to the processor to operate on them, and • 1 of 5 components of a computer: then transfer back to memory when done. memory contains such data structures Computer Processor Memory Devices • But MIPS arithmetic instructions only operate on registers, never directly on Control Input (“brain”) memory. Store (to) Datapath • Data transfer instructions transfer data Registers Output between registers and memory: Load (from) • Memory to register • Register to memory These are “data transfer” instructions… CS61C L09 Introduction to MIPS: Data Transfer & Decisions I (3) Garcia © UCB CS61C L09 Introduction to MIPS: Data Transfer & Decisions I (4) Garcia © UCB Data Transfer: Memory to Reg (1/4) Data Transfer: Memory to Reg (2/4) • To transfer a word of data, we need to • To specify a memory address to copy specify two things: from, specify two things: • Register: specify this by # ($0 - $31) or • A register containing a pointer to memory symbolic name ($s0,…, $t0, …) • A numerical offset (in bytes) • Memory address: more difficult - Think of memory as a single one- • The desired memory address is the dimensional array, so we can address sum of these two values. it simply by supplying a pointer to a Example: memory address. • 8($t0) • specifies the memory address pointed to - Other times, we want to be able to by the value in $t0, plus 8 bytes offset from this pointer. •Remember: “Load FROM memory” CS61C L09 Introduction to MIPS: Data Transfer & Decisions I (5) Garcia © UCB CS61C L09 Introduction to MIPS: Data Transfer & Decisions I (6) Garcia © UCB Data Transfer: Memory to Reg (3/4) Data Transfer: Memory to Reg (4/4) • Load Instruction Syntax: Data flow 1 2,3(4) Example:lw $t0,12($s0) • where This instruction will take the pointer in $s0, add 1) operation name 12 bytes to it, and then load the value from the memory pointed to by this calculated sum into 2) register that will receive value register $t0 3) numerical offset in bytes • Notes: 4) register containing pointer to memory •$s0 is called the base register • MIPS Instruction Name: • 12 is called the offset • offset is generally used in accessing elements •lw (meaning Load Word, so 32 bits of array or structure: base reg points to or one word are loaded at a time) beginning of array or structure CS61C L09 Introduction to MIPS: Data Transfer & Decisions I (7) Garcia © UCB CS61C L09 Introduction to MIPS: Data Transfer & Decisions I (8) Garcia © UCB Data Transfer: Reg to Memory Pointers v. Values • Also want to store from register into memory • Key Concept: A register can hold any • Store instruction syntax is identical to Load’s 32-bit value. That value can be a (signed) int, an unsigned int, a • MIPS Instruction Name: pointer (memory address), and so on sw (meaning Store Word, so 32 bits or one word are loaded at a time) • If you write add $t2,$t1,$t0 then $t0 and $t1 Data flow better contain values • Example:sw $t0,12($s0) • If you write lw $t2,0($t0) This instruction will take the pointer in $s0, add then $t0 better contain a pointer 12 bytes to it, and then store the value from register $t0 into that memory address • Don’t mix these up! • Remember: “Store INTO memory” CS61C L09 Introduction to MIPS: Data Transfer & Decisions I (9) Garcia © UCB CS61C L09 Introduction to MIPS: Data Transfer & Decisions I (10) Garcia © UCB Addressing: Byte vs. word Compilation with Memory • What offset in lw to select A[5] in C? • Every word in memory has an address, similar to an index in an array • 4x5=20 to select A[5]: byte v. word • Early computers numbered words like • Compile by hand using registers: C numbers elements of an array: g = h + A[5]; •Memory[0], Memory[1], Memory[2], … • g: $s1, h: $s2, $s3:base address of A Called the “address” of a word • Computers needed to access 8-bit • 1st transfer from memory to register: bytes as well as words (4 bytes/word) lw $t0,20($s3) # $t0 gets A[5] • Today machines address memory as • Add 20 to $s3 to select A[5], put into $t0 bytes, (i.e.,“Byte Addressed”) hence 32- bit (4 byte) word addresses differ by 4 • Next add it to h and place in g •Memory[0], Memory[4], Memory[8], … add $s1,$s2,$t0 # $s1 = h+A[5] CS61C L09 Introduction to MIPS: Data Transfer & Decisions I (11) Garcia © UCB CS61C L09 Introduction to MIPS: Data Transfer & Decisions I (12) Garcia © UCB Notes about Memory More Notes about Memory: Alignment • Pitfall: Forgetting that sequential • MIPS requires that all words start at byte word addresses in machines with addresses that are multiples of 4 bytes byte addressing do not differ by 1. Last hex digit 0 1 2 3 • Many an assembly language of address is: programmer has toiled over errors made Aligned 0, 4, 8, or C by assuming that the address of the next hex word can be found by incrementing the Not 1, 5, 9, or Dhex address in a register by 1 instead of by Aligned 2, 6, A, or Ehex the word size in bytes. 3, 7, B, or Fhex • So remember that for both lw and sw, the sum of the base address and the offset must be a multiple of 4 (to be word • Called Alignment: objects must fall on aligned) address that is multiple of their size. CS61C L09 Introduction to MIPS: Data Transfer & Decisions I (13) Garcia © UCB CS61C L09 Introduction to MIPS: Data Transfer & Decisions I (14) Garcia © UCB Role of Registers vs. Memory Administrivia • What if more variables than registers? • HW3 due Wed @ 23:59 • Compiler tries to keep most frequently used variable in registers • Project 1 up soon, due in 10 days • Less common in memory: spilling • Hope you remember your Scheme! • Why not keep all variables in memory? • gcc -o foo foo.c • Smaller is faster: • We shouldn’t see any a.out files registers are faster than memory anymore now that you’ve learned this! • Registers more versatile: - MIPS arithmetic instructions can read 2, operate on them, and write 1 per instruction - MIPS data transfer only read or write 1 operand per instruction, and no operation CS61C L09 Introduction to MIPS: Data Transfer & Decisions I (15) Garcia © UCB CS61C L09 Introduction to MIPS: Data Transfer & Decisions I (16) Garcia © UCB So Far... C Decisions: if Statements • All instructions so far only manipulate • 2 kinds of if statements in C data…we’ve built a calculator. •if (condition) clause • In order to build a computer, we need •if (condition) clause1 else clause2 ability to make decisions… • Rearrange 2nd if into following: • C (and MIPS) provide labels to if (condition) goto L1; support “goto” jumps to places in clause2; code. goto L2; • C: Horrible style; MIPS: Necessary! L1: clause1; L2: • Heads up: pull out some papers and pens, you’ll do an in-class exercise! • Not as elegant as if-else, but same meaning CS61C L09 Introduction to MIPS: Data Transfer & Decisions I (17) Garcia © UCB CS61C L09 Introduction to MIPS: Data Transfer & Decisions I (18) Garcia © UCB MIPS Decision Instructions MIPS Goto Instruction • Decision instruction in MIPS: • In addition to conditional branches, MIPS has an unconditional branch: •beq register1, register2, L1 •beq is “Branch if (registers are) equal” j label Same meaning as (using C): • Called a Jump Instruction: jump (or if (register1==register2) goto L1 branch) directly to the given label • Complementary MIPS decision instruction without needing to satisfy any condition •bne register1, register2, L1 • Same meaning as (using C): •bne is “Branch if (registers are) not equal” goto label Same meaning as (using C): • Technically, it’s the same as: if (register1!=register2) goto L1 beq $0,$0,label • Called conditional branches since it always satisfies the condition. CS61C L09 Introduction to MIPS: Data Transfer & Decisions I (19) Garcia © UCB CS61C L09 Introduction to MIPS: Data Transfer & Decisions I (20) Garcia © UCB Compiling C if into MIPS (1/2) Compiling C if into MIPS (2/2) •Compile by hand (true) (false) •Compile by hand (true) (false) i == j? i == j? if (i == j) f=g+h; i == j i != j if (i == j) f=g+h; i == j i != j else f=g-h; else f=g-h; f=g+h f=g-h f=g+h f=g-h •Final compiled MIPS code: •Use this mapping: Exit Exit beq $s3,$s4,True # branch i==j f: $s0 sub $s0,$s1,$s2 # f=g-h(false) j Fin # goto Fin g: $s1 True: add $s0,$s1,$s2 # f=g+h (true) h: $s2 Fin: i: $s3 j: $s4 Note: Compiler automatically creates labels to handle decisions (branches).
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