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Computer Architecture 3 Addresses and Address Spaces Binary Data Outline 1 Introduction 2 Processing binary data Computer Architecture 3 Addresses and address spaces Binary data S. Coudert R. Pacalet Telecom Paris 2021-09-23 1 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data 2 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Section 1 Digital world is binary From voltage to bits Introduction Wires/memory elements carry/store voltages Electric potential difference with reference Two main voltage levels: ground, power supply • Ground (reference, zero volt): 0 / false • Power supply (e.g. ≈ one volt): 1 / true o Intermediate or unstable voltages also exists From bits to numbers Buses: sets of wires Memory data: sets of memory cells Ordered bit sets represent numbers in binary form 3 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data 4 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Digital world is binary Unsigned numbers Goals of this lecture From strings to numbers Discover low level and more abstract binary representations Base N: N symbols α, β... associated to values zero, one. Become familiar with them Usually 0, . , 9 for first ten symbols, then A, B. if needed Widely used in computer science Let D0, ..., Dk−1 be k symbols in base N Pi=k−1 i ⇒ Dk−1...D1D0 denotes number i=0 Di × N o Non-ambiguous interpretation requires knowledge of base 5 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data 6 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Unsigned numbers Signed numbers Example Two main representations Base ten (digits 0, 1. , 9) Dk−1 Pi=k−2 i Sign and magnitude: (−1) × i=0 Di × 2 342 = 3 × 102 + 4 × 101 + 2 × 100 = 3 × 100 + 4 × 10 + 2 10 Negate ultra-simple: flip sign bit Base eleven (symbols 0, 1. , 9, A) Addition/subtraction not simple (tests, need of both) 2 1 0 34211 = 3 × 1011 + 4 × 1011 + 2 × 1011 Multiplication simple 2 1 k Pi=k−2 i = 3 × 1110 + 4 × 1110 + 2 Two’s complement: −2 × Dk−1 + i=0 Di × 2 = 3 × 12110 + 4 × 1110 + 2 = 40910 Negate not simple: flip all bits (one’s complement), add 1 Addition and subtraction simple (no tests) Base two (bits 0, 1) 02 = 010, 12 = 110, 102 = 210, 112 = Multiplication a bit more complicated 310, 1002 = 410, 1012 = 510... ɳ Decimal value of 3426? 7 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data 8 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Exercise: Two’s complement Notations Check your understanding of two’s complement Human readable or close to hardware (binary)? ɳ Prove the two’s complement negate ɳ Simply use base ten and avoid headache? ɳ Imagine the ten’s complement Translating to/from base 2 difficult ɳ What is the set of representable 4-bits integers? 9: 1001, 14: 1110, 237: 11101101 ɳ 4th bit (from right) in 8 bit memory cell containing 97 ? ɳ −310 and 910 on 4 bits 10 ɳ −3 and 9 on 8 bits ɳ Use base two? 10 10 ɳ ɳ How to extend from n bits to n+k bits? 4th bit (from right) in 8 bit memory cell containing 9710? Ë ɳ 01100001 Explain addition and subtraction Not really human-readable 2134: 100001010110, 69497: 10000111101111001 Frequent trade-offs • Hexadecimal, 16 symbols: 0, . , 9, A, B, C, D, E, F (A16 = 1010, ..., F16 = 1510) • Frequent notation (C language): 0xA3F690D • Octal, 8 symbols: 0, . , 7. Notation: 042075 9 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data 10 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Hexadecimal and octal Vocabulary MSB/LSB Hexadecimal Octal Most/Least Significant Bit (MSB/LSB) Compact: one symbol = 4 bits Relevant for 3-bits groups, Coefficients of greatest/smallest power of two 8 × 4 = 32 e.g. Unix-like permissions By convention binary numbers usually: Octal 7 5 1 D 8 F 3 7 B 0 9 • Written MSB left, down to LSB right (as humans expect) • 0 1 1 1 Binary 1 1 1 1 0 1 0 0 1 Indexed k-1 (MSB) down to 0 (LSB) Text r w x r - x - - x o This is just a convention, other notations possible 17th bit from left owner group user Examples 7 0 Summary 0 0 1 1 1 1 0 1 Octal 1 7 2 4 high half low half 0 7 Binary 0 0 1 1 1 1 0 1 0 1 0 0 1 0 1 1 1 1 0 0 low half high half Hexadecimal 3 D 4 11 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data 12 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Vocabulary Exercise: Number representations Endianness Check your understanding of number representations Memory data at several consecutive addresses ɳ 3010 in base three Big endian: MSB first (at lowest address) ɳ 8710 in bases two, eight, sixteen Little endian: LSB first (at lowest address) ɳ F 30616 in base two Example: 0xEB2EF18A in 8-bits memory ɳ F 30816 in base eight 31 24 23 16 15 8 7 0 bits (LSB: 0) ɳ 01100010101011102 in bases eight, sixteen big EB 2E F1 8A ɳ bit #5 in 8-bits memory cell containing 12310? a a + 1 a + 2 a + 3 addresses 7 0 15 8 23 16 31 24 bits (LSB: 0) little 8A F1 2E EB a a + 1 a + 2 a + 3 addresses 13 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data 14 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Section 2 Bitwise boolean operations Instruction sets usually contain bitwise operations Processing binary data x 10111010 y 01011101 not x 01000101 x and y 00011000 x or y 11111111 x xor y 11100111 x shl 2 (shift x left by two positions) 11101000 x shr 2 (shift x right by two positions) 00101110 15 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data 16 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Bitwise boolean operations Bitwise boolean operations, example of use Straightforward hardware implementation 8-bits CPU with 8 registers R0...R7 Load <R> <Addr> R ← Mem[Addr] Store <R> <Addr> Mem[Addr] ← R And <Ri> <Rj> <Rk> Ri ← Rj and Rk Andi <Ri> <Rj> <Value> Ri ← Rj and V Or, Ori, Xor, Xori, Not similar to And/Andi 8-pin Input/Output port 8-bit configuration register at address 0xFA01 If bit #i set pin #i output, else input 216 − 1 output pins 0 4 1 5 0xFA01 MSB 0 1 0 0 1 0 1 1 LSB 2 6 3 7 address space input pins 0 17 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data 18 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Exercise: Bitwise operations Section 3 Configure pin #5 as output, other pins unmodified Load R1 0xFA01 Addresses and address spaces Ori R2 R1 b00100000 // (0x20) Store R2 0xFA01 Check your understanding of bitwise operations ɳ Configure pin #7 as input ɳ Configure: • pins #2 and #7 as inputs • pin #4 as output • using only one load and one store ɳ Invert all pin states without not instruction? 19 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data 20 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Memory mapping Memory mapping 2n − 1 2n − 1 n-bits addresses CPU Read-write effect vary ROM (RO memory) Address space: address from ROM (RO memory) RAM: read and write (RW) 0 to 2n − 1 ROM: read only (RO) RAM 2 (RW memory) CPU communication: RAM 2 (RW memory) Devices interface registers addressed read/write (data • Can be RO, RW or timer (RW registers) timer (RW registers) write-only USB (RW registers) or instructions) USB (RW registers) Memory mapping: hardware • Can store commands, unmapped unmapped map addresses to devices data, status,. • • Can have side-effects RAM 1 (RW memory) Memories RAM 1 (RW memory) • Device registers ⇒ Different programming uses keyboard (RO registers) • ... keyboard (RO registers) 0 Addresses can be unmapped 0 21 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data 21 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Example: Leon’s memory mapping Example: Leon’s memory mapping (AHB) Typical Leon-based architecture AHB bus 22 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data 23 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Example: Leon’s memory mapping (APB) Remarks on Mapping Components have dedicated subspaces Power of two addresses and sizes Addresses breakdown on AHB bus: • Bits 31. 28: select AHB Slave • Bits 27. 0: offset in subspace Addresses breakdown on APB bus: • Bits 27. 6 or 27. 4: select APB Slave • Bits 5. 0 or 3. 0: offset in subspace Components not always use complete subspace Component address bus can be narrower than system bus APB bus memory mapping 24 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data 25 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Addresses and subspaces Addresses and subspaces Address space can split into subspaces Addresses viewed as subspace identifier + offset in subspace Powers of 2 allow simple addresses decoding • MSB: subspace identifier • LSB: offset in subspace Example: 64 addresses (n = 6 address bits) • One subspace: k = 0, 64 cells per subspace • Two subspaces: k = 1, 32 cells per subspace • ... • 64 subspaces: k = 6, single cell per subspace k bits, 2k subspaces n − k bits, 2n−k cells per subspace subspace offset 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 n-bits addresses, 2n cells One layout, several views Subspaces are more logical concepts than physical ones 26 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data 27 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Exercise: Simple implementation example Addresses refinement Check your understanding of address subspaces Example: 4-byte ɳ Modify diagram such that device 2 has 64-addresses subspace words addressing device 3 Add LSBs to addresses for device 2 3 wires only, device 1 uses 8 (or less) finer addressing addresses, some addresses are unmapped granularity device 1 Two extra LSBs allow device 0 Chip select wires byte addressing address bus decoder up to 8 targets 011011 011011 0 1 28 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data 29 / 35 2021-09-23 Telecom Paris Computer Architecture — Binary data Address fields Address fields Memory Memory byte subspace offset ..
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