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PA-RISC 1.1 Architecture and Instruction Set Reference Manual

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PA-RISC 1.1 Architecture and Instruction Set Reference Manual PA-RISC 1.1 Architecture and Instruction Set Reference Manual HP Part Number: 09740-90039 Printed in U.S.A. February 1994 Third Edition Notice The information contained in this document is subject to change without notice. HEWLETT-PACKARD MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Hewlett-Packard shall not be liable for errors contained herein or for incidental or consequential damages in connection with furnishing, performance, or use of this material. Hewlett-Packard assumes no responsibility for the use or reliability of its software on equipment that is not furnished by Hewlett-Packard. This document contains proprietary information which is protected by copyright. All rights are reserved. No part of this document may be photocopied, reproduced, or translated to another language without the prior written consent of Hewlett-Packard Company. Copyright © 1986 – 1994 by HEWLETT-PACKARD COMPANY Printing History The printing date will change when a new edition is printed. The manual part number will change when extensive changes are made. First Edition . November 1990 Second Edition. September 1992 Third Edition . February 1994 Contents Contents . iii Preface. ix 1 Overview . 1-1 Introduction. 1-1 System Features . 1-2 PA-RISC 1.1 Enhancements . 1-2 System Organization . 1-4 2 System Organization . 2-1 Introduction. 2-1 Memory and I/O Addressing . 2-2 Byte Ordering (Big Endian/Little Endian) . 2-3 Levels of PA-RISC. 2-5 Data Types . 2-5 Processing Resources. 2-7 3 Addressing and Access Control. 3-1 Introduction. 3-1 Pointers and Address Specification . 3-2 Address Resolution and the TLB. 3-3 Access Control . .3-10 Page Table Structure . .3-14 Caches . .3-15 The Synchronization Primitive. .3-16 Cache Coherence with I/O . .3-17 Cache Coherence in Multiprocessor Systems . .3-17 TLB Coherence in Multiprocessor Systems . .3-18 TLB Operation Requirements . .3-18 Data Cache Move-In . .3-21 Instruction Cache Move-In. .3-22 4 Flow Control and Interruptions . 4-1 Introduction. 4-1 Instruction Execution. 4-1 Atomicity of Storage Accesses. 4-3 Ordering of Accesses. 4-3 Completion of Accesses . 4-5 Instruction Pipelining. 4-6 Nullification . 4-7 Branching. 4-7 Interruptions . .4-13 5 Instruction Set . 5-1 Introduction. 5-1 Undefined and Illegal Instructions . 5-1 Reserved Instruction Fields . 5-2 Reserved Values of an Instruction Field . 5-2 PA-RISC 1.1 Architecture Contents iii Null Instructions. 5-2 Conditions and Control Flow . 5-2 Instruction Notations . 5-7 Instruction Descriptions. 5-14 Memory Reference Instructions. 5-15 Immediate Instructions . 5-54 Branch Instructions . 5-58 Computation Instructions . 5-81 System Control Instructions. 5-136 Assist Instructions. 5-176 6 Floating-point Coprocessor . 6-1 Introduction . 6-1 Data Registers . 6-5 Data Formats . 6-6 Status Register . 6-9 Instruction Set . 6-12 Exception Registers . 6-23 Interruptions and Exceptions . 6-26 Saving and Restoring State . 6-35 Instruction Set Description . 6-36 7 Performance Monitor Coprocessor . 7-1 Introduction . 7-1 The Instruction Set . 7-1 Interruptions. 7-1 Monitor Units . 7-2 Instruction Set Description . 7-2 8 Debug Special Function Unit . 8-1 Introduction . 8-1 Debug Registers. 8-1 The Instruction Set . 8-3 Interruptions. 8-4 Instruction Set Description . 8-5 A Glossary . A-1 B Instruction Index . .B-1 C Instruction Formats . .C-1 D Operation Codes . D-1 Major Opcode Assignments. D-1 Opcode Extension Assignments . D-3 E Level 0 Summary . .E-1 I Index . I-1 iv Contents PA-RISC 1.1 Architecture.
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