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CSE 141 Introduction to Computer Architecture Summer Session I, 2005 CSE 141 Introduction to Computer Architecture Summer Session I, 2005 Lecture 1 Introduction Pramod V. Argade June 27, 2005 CSE141: Introduction to Computer Architecture Instructor: Pramod V. Argade ([email protected]) Office Hour: Mon. 4:30 - 5:30 PM (AP&M 4218) TAs: Chengmo Yang: [email protected] Wenjing Rao: [email protected] Lecture: Mon/Wed. 6:00 - 8:50 PM, HSS 1330 Textbook: Computer Organization & Design The Hardware Software Interface, 3nd Edition. Authors: Patterson and Hennessy Web-page: http://www.cse.ucsd.edu/classes/su05/cse141 Pramod Argade CSE 141, Summer Session I, 2005 1-2 What is a Computer? z Components: – Input (mouse, keyboard) – Output (display, printer) – Memory (disk drives, DRAM, SRAM, CD) –Network z Our primary focus: the processor (datapath and control) – Implemented using millions of transistors – Impossible to understand by looking at each transistor z Rapidly changing field: – Vacuum tube Î Transistor Î IC Î VLSI Î SoC z Interesting history: – http://www.islandnet.com/~kpolsson/comphist/ Pramod Argade CSE 141, Summer Session I, 2005 1-3 Architecture: Dictionary Definition z The art and science of designing and erecting buildings. z A style and method of design and construction. z Orderly arrangement of parts; structure. z ... Pramod Argade CSE 141, Summer Session I, 2005 1-4 What is Computer Architecture? z Hardware Designer z Computer Architect – Thinks about circuits, – Thinks about high-level components, timing, functionality, components, how they fit ease of debugging together, how they work together to deliver performance. “construction engineer” “building architect” Pramod Argade CSE 141, Summer Session I, 2005 1-5 The Challenge of Computer Architecture z The industry changes faster than any other. – design assuming processor technology trends z The ground rules change every year. – new problems – new opportunities – different tradeoffs z It’s all about making programs run faster than the current generation of processors Pramod Argade CSE 141, Summer Session I, 2005 1-6 Forces on Computer Architecture Hardware Programming Technology Languages Applications Compiler Computer Technology Architecture Operating Systems Compatibility Pramod Argade CSE 141, Summer Session I, 2005 1-7 Evolution of Intel Processors* Year of # Processor Introduction Transistors 4004 1971 2,250 8008 1972 2,500 8080 1974 5,000 8086 1978 29,000 286 1982 120,000 Intel I386 1985 275,000 Intel I486 1989 1,180,000 Intel Pentium 1993 3,100,000 Intel Pentium II 1997 7,500,000 Intel Pentium III 1999 24,000,000 Intel Pentium 4 2000 42,000,000 Intel Itanium 2002 220,000,000 Intel Itanium 2 2003 410,000,000 *http://www.intel.com/research/silicon/mooreslaw.htm Pramod Argade CSE 141, Summer Session I, 2005 1-8 Pentium 2 Photomicrograph* *http://microscope.fsu.edu/chipshots/pentium/pent2large.html Pramod Argade CSE 141, Summer Session I, 2005 1-9 Moore’s Law* • Gordon Moore made the observation in 1965, four years after planar integrated circuit was discovered. • The “law” states that transistor density doubles every ~18 months *http://www.intel.com/research/silicon/mooreslaw.htm Pramod Argade CSE 141, Summer Session I, 2005 1-10 Processor Performance 1200 DEC Alpha 21264/600 1000 800 600 DEC Alpha 5/500 Performance 400 DEC DEC Alpha 5/300 IBM HP AXP/ Sun MIPS MIPS 200 RS/ 9000/ 500 -4/ M M/ DEC Alpha 4/266 6000 750 260 2000 120 IBM POWER 100 0 87 88 89 90 91 92 93 94 95 96 97 Year Pramod Argade CSE 141, Summer Session I, 2005 1-11 Computer Architecture’s Changing Definition z 1950s to 1960s Computer Architecture – Computer Arithmetic z 1970s to mid 1980s Computer Architecture – Instruction Set Design, especially ISA appropriate for compilers z 1990s Computer Architecture – Design of CPU, memory system, I/O system, Multiprocessors – Instruction level Parallelism z 2000s Computer Architecture – System-on-a-chip (SoC) Pramod Argade CSE 141, Summer Session I, 2005 1-12 Processors are everywhere! z PC, Workstation z Cell Phone z DVD Player z Digital Camera z Car z Watch z Pacemaker z “Pill Camera” z ... Pramod Argade CSE 141, Summer Session I, 2005 1-13 Commercial Processor Architectures z Embedded Processors – ARM, MIPS, PowerPC, ARC, … z PC/Workstation Processors – Intel x86, Sun SPARC, IBM/Motorola PowerPC, … z Super Computer – IBM PowerPC, Intel Itanium, NEC, Pramod Argade CSE 141, Summer Session I, 2005 1-14 Why do you care about architecture? z If you become a SW designer – Understand architecture to better utilize it – What are performance bottlenecks & who will fix them? z If you become a HW designer – You may implement a processor architecture in your career z If you become a System designer – You may make HW and SW partition decision z You may have to make purchasing decisions – Buy from vendor A or B? Why? z Everything amounts to cost/benefit tradeoff! – What are the techniques for making such tradeoffs? Pramod Argade CSE 141, Summer Session I, 2005 1-15 Which is faster? for (i=0; i<N; i=i+1) for (jj=0; jj<N; jj=jj+B) for (j=0; j<N; j=j+1) { for (kk=0; kk<N; kk=kk+B) r = 0; for (i=0; i<N; i=i+1) { for (k=0; k<N; k=k+1) for (j=jj; j<min(jj+B-1,N); j=j+1) r = r + y[i][k] * z[k][j]; r = 0; x[i][j] = r; for (k=kk; k<min(kk+B-1,N); k=k+1) } r = r + y[i][k] * z[k][j]; x[i][j] = x[i][j] + r; } Pramod Argade CSE 141, Summer Session I, 2005 1-16 Which is faster? load R1, addr1 load R1, addr1 store R1, addr2 add R0, R2 -> R3 add R0, R2 -> R3 add R0, R6 -> R7 subtract R4, R3 -> R5 store R1, addr2 add R0, R6 ->R7 subtract R4, R3 -> R5 store R7, addr3 store R7, addr3 Pramod Argade CSE 141, Summer Session I, 2005 1-17 Levels of Abstraction z Delving into the depths reveals more information z An abstraction omits unneeded detail, helps us cope with complexity High Level Language temp = v[k]; Program v[k] = v[k+1]; v[k+1] = temp; Compiler SW $15, 0($2) Assembly Language LW $16, 4($2) Program SW $16, 0($2) SW $15, 4($2) Assembler 1000110001100010000000000000000 Machine Language 1000110011110010000000000000100 Program 1010110011110010000000000000000 1010110001100010000000000000100 Machine Interpretation Control Signal Spec ALUOP[0:3] <= InstReg[9:11] & MASK Pramod Argade CSE 141, Summer Session I, 2005 1-18 The five classic components of computers Computer Control Input Memory Datapath Output Pramod Argade CSE 141, Summer Session I, 2005 1-19 Computer Architecture Topics Input/Output and Storage Disks, WORM, Tape RAID Emerging Technologies DRAM Interleaving Bus protocols Coherence, Memory L2 Cache Bandwidth, Hierarchy Latency L1 Cache Addressing, VLSI Protection, Instruction Set Architecture Exception Handling Pipelining, Hazard Resolution, Pipelining and Instruction Superscalar, Reordering, Level Parallelism Prediction, Speculation, Vector, DSP Pramod Argade CSE 141, Summer Session I, 2005 1-20 MIPS R10000 CPU What you can expect to get out of this class z Understand fundamental concepts in computer architecture z Understand impact on application performance z Evaluate architectural descriptions of processors z Gain experience designing a working CPU completely from scratch z Learn techniques used to evaluate advanced architecture design Pramod Argade CSE 141, Summer Session I, 2005 1-22 Course Outline z Instruction Set Architecture z Computer System Performance and Performance Metrics z Computer Arithmetic and Number System z CPU Architecture z Pipelining z Memory Hierarchy and Caches z Virtual Memory Pramod Argade CSE 141, Summer Session I, 2005 1-23 Summer Session I, 2005 CSE141 Course Schedule Homework Lecture # Date Time Room Topic Quiz topic Due Introduction, Ch. 1 1 Mon. 6/27 6 - 8:50 PM HSS 1330 -- ISA, Ch. 2 ISA 2 Wed. 6/29 6 - 8:50 PM HSS 1330 Arithmetic, Ch. 3 #1 Ch. 2 - Mon. 7/4No Class July 4th Holiday - - Performance, Ch. 4 Arithmetic 3 Wed. 7/6 6 - 8:50 PM HSS 1330 #2 Single-cycle CPU Ch. 5 Ch. 3 Single-cycle CPU Ch. 5 Cont. Performance 4 Mon. 7/11 6 - 8:50 PM HSS 1330 #3 Multi-cycle CPU Ch. 5 Ch. 4 Multi-cycle CPU Ch. 5 Cont. 5 Tue. 7/12 7:30 - 8:50 PM HSS 1330 -- (July 4th make up class) Single and Multicycle CPU Examples and Single-cycle CPU 6 Wed. 7/13 6 - 8:50 PM HSS 1330 - Review for Midterm Ch. 5 Mid-term Exam 7 Mon. 7/18 6 - 8:50 PM HSS 1330 -#4 Exceptions Pipelining Ch. 6 8 Tue. 7/19 7:30 - 8:50 PM HSS 1330 -- (July 4th make up class) 9 Wed. 7/20 6 - 8:50 PM HSS 1330 Hazards, Ch. 6 - - Hazards 10 Mon. 7/25 6 - 8:50 PM HSS 1330 Memory Hierarchy & Caches Ch. 7 #5 Ch. 6 Virtual Memory, Ch. 7 Cache 11 Wed. 7/27 6 - 8:50 PM HSS 1330 #6 Course Review Ch. 7 12 Sat. 7/30 TBD TBD Final Exam - - Pramod Argade CSE 141, Summer Session I, 2005 1-24 Course Work and Grading z Course Work – Weekly homework assignments ¾ No late assignments accepted ¾ No re-grading of homework or quizzes z Grading – 10% homework ¾ Lowest homework score will be dropped – 25% weekly quizzes (10 minutes, every Monday) ¾ Lowest quiz score will be dropped – 25% midterm – 40% final (which will cover the whole quarter) – Tests & Quizzes ¾ Closed books and no notes Pramod Argade CSE 141, Summer Session I, 2005 1-25 Quiz, Tests: What to expect? z Material covered during lectures z Material covered by homework assignments Pramod Argade CSE 141, Summer Session I, 2005 1-26 CSE 141 – Computer Architecture Spring 2005 Lecture 2 Instruction Set Architecute Pramod V.
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