CSE 141 Introduction to Computer Architecture Summer Session I, 2005

Lecture 1 Introduction Pramod V. Argade June 27, 2005 CSE141: Introduction to Computer Architecture

Instructor: Pramod V. Argade ([email protected]) Office Hour: Mon. 4:30 - 5:30 PM (AP&M 4218)

TAs: Chengmo Yang: [email protected] Wenjing Rao: [email protected]

Lecture: Mon/Wed. 6:00 - 8:50 PM, HSS 1330

Textbook: Computer Organization & Design The Hardware Software Interface, 3nd Edition. Authors: Patterson and Hennessy

Web-page: http://www.cse.ucsd.edu/classes/su05/cse141

Pramod Argade CSE 141, Summer Session I, 2005 1-2 What is a Computer? z Components: – Input (mouse, keyboard) – Output (display, printer) – Memory (disk drives, DRAM, SRAM, CD) –Network z Our primary focus: the processor (datapath and control) – Implemented using millions of transistors – Impossible to understand by looking at each transistor z Rapidly changing field: – Vacuum tube Î Transistor Î IC Î VLSI Î SoC z Interesting history: – http://www.islandnet.com/~kpolsson/comphist/

Pramod Argade CSE 141, Summer Session I, 2005 1-3 Architecture: Dictionary Definition z The art and science of designing and erecting buildings. z A style and method of design and construction. z Orderly arrangement of parts; structure. z ...

Pramod Argade CSE 141, Summer Session I, 2005 1-4 What is Computer Architecture?

z Hardware Designer z Computer Architect – Thinks about circuits, – Thinks about high-level components, timing, functionality, components, how they fit ease of debugging together, how they work together to deliver performance. “construction engineer” “building architect”

Pramod Argade CSE 141, Summer Session I, 2005 1-5 The Challenge of Computer Architecture z The industry changes faster than any other. – design assuming processor technology trends z The ground rules change every year. – new problems – new opportunities – different tradeoffs z It’s all about making programs run faster than the current generation of processors

Pramod Argade CSE 141, Summer Session I, 2005 1-6 Forces on Computer Architecture

Hardware Programming Technology Languages

Applications Compiler Computer Technology Architecture

Operating Systems Compatibility

Pramod Argade CSE 141, Summer Session I, 2005 1-7 Evolution of Intel Processors*

Year of # Processor Introduction Transistors 4004 1971 2,250 8008 1972 2,500 8080 1974 5,000 8086 1978 29,000 286 1982 120,000 Intel I386 1985 275,000 Intel I486 1989 1,180,000 Intel Pentium 1993 3,100,000 Intel Pentium II 1997 7,500,000 Intel Pentium III 1999 24,000,000 Intel Pentium 4 2000 42,000,000 Intel Itanium 2002 220,000,000 Intel Itanium 2 2003 410,000,000

*http://www.intel.com/research/silicon/mooreslaw.htm

Pramod Argade CSE 141, Summer Session I, 2005 1-8 Pentium 2 Photomicrograph*

*http://microscope.fsu.edu/chipshots/pentium/pent2large.html Pramod Argade CSE 141, Summer Session I, 2005 1-9 Moore’s Law*

• Gordon Moore made the observation in 1965, four years after planar integrated circuit was discovered. • The “law” states that transistor density doubles every ~18 months

*http://www.intel.com/research/silicon/mooreslaw.htm

Pramod Argade CSE 141, Summer Session I, 2005 1-10 Processor Performance

1200 DEC Alpha 21264/600

1000

800

600

Performance DEC Alpha 5/500

400 DEC DEC Alpha 5/300 IBM HP AXP/ Sun MIPS MIPS 200 RS/ 9000/ 500 -4/ M M/ DEC Alpha 4/266 6000 750 260 2000 120 IBM POWER 100 0 87 88 89 90 91 92 93 94 95 96 97 Year Pramod Argade CSE 141, Summer Session I, 2005 1-11 Computer Architecture’s Changing Definition

z 1950s to 1960s Computer Architecture – Computer Arithmetic

z 1970s to mid 1980s Computer Architecture – Instruction Set Design, especially ISA appropriate for compilers

z 1990s Computer Architecture – Design of CPU, memory system, I/O system, Multiprocessors – Instruction level Parallelism

z 2000s Computer Architecture – System-on-a-chip (SoC)

Pramod Argade CSE 141, Summer Session I, 2005 1-12 Processors are everywhere! z PC, Workstation z Cell Phone z DVD Player z Digital Camera z Car z Watch z Pacemaker z “Pill Camera” z ...

Pramod Argade CSE 141, Summer Session I, 2005 1-13 Commercial Processor Architectures z Embedded Processors – ARM, MIPS, PowerPC, ARC, … z PC/Workstation Processors – Intel x86, Sun SPARC, IBM/Motorola PowerPC, … z Super Computer – IBM PowerPC, Intel Itanium, NEC,

Pramod Argade CSE 141, Summer Session I, 2005 1-14 Why do you care about architecture? z If you become a SW designer – Understand architecture to better utilize it – What are performance bottlenecks & who will fix them? z If you become a HW designer – You may implement a processor architecture in your career z If you become a System designer – You may make HW and SW partition decision z You may have to make purchasing decisions – Buy from vendor A or B? Why? z Everything amounts to cost/benefit tradeoff! – What are the techniques for making such tradeoffs?

Pramod Argade CSE 141, Summer Session I, 2005 1-15 Which is faster?

for (i=0; i

Pramod Argade CSE 141, Summer Session I, 2005 1-16 Which is faster?

load R1, addr1 load R1, addr1 store R1, addr2 add R0, R2 -> R3 add R0, R2 -> R3 add R0, R6 -> R7 subtract R4, R3 -> R5 store R1, addr2 add R0, R6 ->R7 subtract R4, R3 -> R5 store R7, addr3 store R7, addr3

Pramod Argade CSE 141, Summer Session I, 2005 1-17 Levels of Abstraction z Delving into the depths reveals more information z An abstraction omits unneeded detail, helps us cope with complexity High Level Language temp = v[k]; Program v[k] = v[k+1]; v[k+1] = temp; Compiler SW $15, 0($2) Assembly Language LW $16, 4($2) Program SW $16, 0($2) SW $15, 4($2) Assembler 1000110001100010000000000000000 Machine Language 1000110011110010000000000000100 Program 1010110011110010000000000000000 1010110001100010000000000000100 Machine Interpretation

Control Signal Spec ALUOP[0:3] <= InstReg[9:11] & MASK

Pramod Argade CSE 141, Summer Session I, 2005 1-18 The five classic components of computers

Computer

Control Input

Memory

Datapath Output

Pramod Argade CSE 141, Summer Session I, 2005 1-19 Computer Architecture Topics

Input/Output and Storage

Disks, WORM, Tape RAID

Emerging Technologies DRAM Interleaving Bus protocols

Coherence, Memory L2 Cache Bandwidth, Hierarchy Latency

L1 Cache Addressing, VLSI Protection, Instruction Set Architecture Exception Handling Pipelining, Hazard Resolution, Pipelining and Instruction Superscalar, Reordering, Level Parallelism Prediction, Speculation, Vector, DSP Pramod Argade CSE 141, Summer Session I, 2005 1-20 MIPS R10000 CPU What you can expect to get out of this class

z Understand fundamental concepts in computer architecture

z Understand impact on application performance

z Evaluate architectural descriptions of processors

z Gain experience designing a working CPU completely from scratch

z Learn techniques used to evaluate advanced architecture design

Pramod Argade CSE 141, Summer Session I, 2005 1-22 Course Outline

z Instruction Set Architecture z Computer System Performance and Performance Metrics z Computer Arithmetic and Number System z CPU Architecture z Pipelining z Memory Hierarchy and Caches z Virtual Memory

Pramod Argade CSE 141, Summer Session I, 2005 1-23 Summer Session I, 2005 CSE141 Course Schedule

Homework Lecture # Date Time Room Topic Quiz topic Due Introduction, Ch. 1 1 Mon. 6/27 6 - 8:50 PM HSS 1330 -- ISA, Ch. 2 ISA 2 Wed. 6/29 6 - 8:50 PM HSS 1330 Arithmetic, Ch. 3 #1 Ch. 2 - Mon. 7/4No Class July 4th Holiday - - Performance, Ch. 4 Arithmetic 3 Wed. 7/6 6 - 8:50 PM HSS 1330 #2 Single-cycle CPU Ch. 5 Ch. 3 Single-cycle CPU Ch. 5 Cont. Performance 4 Mon. 7/11 6 - 8:50 PM HSS 1330 #3 Multi-cycle CPU Ch. 5 Ch. 4 Multi-cycle CPU Ch. 5 Cont. 5 Tue. 7/12 7:30 - 8:50 PM HSS 1330 -- (July 4th make up class) Single and Multicycle CPU Examples and Single-cycle CPU 6 Wed. 7/13 6 - 8:50 PM HSS 1330 - Review for Midterm Ch. 5 Mid-term Exam 7 Mon. 7/18 6 - 8:50 PM HSS 1330 -#4 Exceptions Pipelining Ch. 6 8 Tue. 7/19 7:30 - 8:50 PM HSS 1330 -- (July 4th make up class) 9 Wed. 7/20 6 - 8:50 PM HSS 1330 Hazards, Ch. 6 - - Hazards 10 Mon. 7/25 6 - 8:50 PM HSS 1330 Memory Hierarchy & Caches Ch. 7 #5 Ch. 6 Virtual Memory, Ch. 7 Cache 11 Wed. 7/27 6 - 8:50 PM HSS 1330 #6 Course Review Ch. 7 12 Sat. 7/30 TBD TBD Final Exam - -

Pramod Argade CSE 141, Summer Session I, 2005 1-24 Course Work and Grading z Course Work – Weekly homework assignments ¾ No late assignments accepted ¾ No re-grading of homework or quizzes z Grading – 10% homework ¾ Lowest homework score will be dropped – 25% weekly quizzes (10 minutes, every Monday) ¾ Lowest quiz score will be dropped – 25% midterm – 40% final (which will cover the whole quarter) – Tests & Quizzes ¾ Closed books and no notes

Pramod Argade CSE 141, Summer Session I, 2005 1-25 Quiz, Tests: What to expect?

z Material covered during lectures z Material covered by homework assignments

Pramod Argade CSE 141, Summer Session I, 2005 1-26 CSE 141 – Computer Architecture Spring 2005

Lecture 2 Instruction Set Architecute

Pramod V. Argade June 27, 2005 Instruction Set Architecture (ISA) General Considerations

Pramod Argade CSE 141, Summer Session I, 2005 1-28 Stored Program Concept

Control Memory Input for Program Datapath & Output Data

z Instructions are bits z Programs are stored in memory — to be read or written just like data z Fetch & Execute Cycle – Instructions are fetched and put into a special register – Bits in the register "control" the subsequent actions – Fetch the “next” instruction and continue

Pramod Argade CSE 141, Summer Session I, 2005 1-29 Memory Organization z Viewed as a large, single-dimension array, with an address. z A memory address is an index into the array z "Byte addressing" means that the index points to a byte of memory.

0 8 bits of data 1 8 bits of data 2 8 bits of data 3 8 bits of data 4 8 bits of data 5 8 bits of data 6 8 bits of data ...

Pramod Argade CSE 141, Summer Session I, 2005 1-30 Memory Organization z Bytes are nice, but most data items use larger "words" z For MIPS, a word is 32 bits or 4 bytes.

0 32 bits of data 4 32 bits of data 8 32 bits of data 12 32 bits of data ... z Words are aligned on 4-byte boundary i.e., what are the least 2 significant bits of a word address? z 32 bits address –232 bytes with byte addresses from 0 to 232-1 –230 words with byte addresses 0, 4, 8, ... 232-4

Pramod Argade CSE 141, Summer Session I, 2005 1-31 Endian-ness: How to address bytes within words?

z Big Endian: address of most significant byte = word address – IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA z Little Endian: address of least significant byte = word address – Intel 80x86, DEC Vax, DEC Alpha (Windows NT) 3 2 1 0 little endian byte # msb lsb

0 1 2 3 bigendianbyte # 0 0x00 0 0x33 1 0x11 0 0x00112233 1 0x22 2 0x22 4 0x44556677 2 0x11 3 0x33 8 0x8899aabb 3 0x00 4 0x44 12 0xccddeeff 4 0x77 5 0x55 ... 5 0x66 0x66 0x55 6 Word Data 6 ...... Big-endian Little-endian

Pramod Argade CSE 141, Summer Session I, 2005 1-32 Addressing: Alignment

0 1 2 3 Aligned

Not Aligned

• Alignment: require that objects fall on address that is multiple of their size.

• MIPS requires address alignment • Word addresses must be multiple of 4 • Half word addresses must be multiple of 2

Pramod Argade CSE 141, Summer Session I, 2005 1-33 The Instruction Execution Cycle Instruction Obtain instruction from program storage Fetch

Instruction Determine required actions and instruction size Decode

Operand Locate and obtain operand data Fetch

Execute Compute result value or status

Result Deposit results in storage for later use Store

Next Determine successor instruction Instruction The Instruction Set Architecture

• Is the interface between all the software that runs on the machine and the hardware that executes it.

Application

Operating Compiler System Instruction Set Architecture Micro-code I/O system Digital Design Circuit Design

• Provides a “level of abstraction” in both directions • Modern instruction set architectures: 80x86/Pentium, MIPS, SPARC, PowerPC, ARM, Tensilica, ...

Pramod Argade CSE 141, Summer Session I, 2005 1-35 Instruction Set Architecture (ISA) z Instructions: Words of a machine’s language z Instruction Set: Machine’s vocabulary z ISA: A very important abstraction – Interface between hardware and low-level software – Standardizes instructions, machine language bit patterns, etc. – Advantage: different implementations of the same architecture – Disadvantage: sometimes prevents using new innovations True or False? Binary compatibility is extraordinarily important. z Part of the architecture that is visible to the programmer – opcodes (available instructions) – number and types of registers – instruction formats – storage access, addressing modes – exceptional conditions Pramod Argade CSE 141, Summer Session I, 2005 1-36 Key ISA Decisions z Instruction length – Fixed length – Variable length z Registers – How many? z Operand access –Register –Memory z Instruction format – Meaning of group of bits within machine instruction z Operands – How many per instruction, size (byte, word,..) z Operations – ADD, SUB, MUL, ... Pramod Argade CSE 141, Summer Session I, 2005 1-37 Accessing the Operands z Operands are generally in one of two places: – Registers: fast on-chip storage (how many, how wide?) – Memory (how many locations?) z Registers are – Easy to specify – Close to the processor – Provide fast access – Can read two operands and write one result per clock cycle z The idea that we want to access registers whenever possible led to load-store architectures. – Normal arithmetic instructions only access registers – Only access memory with explicit loads and stores

Pramod Argade CSE 141, Summer Session I, 2005 1-38 Basic ISA Classes Comparing the Number of Instructions

Code sequence for C = A + B for four classes of instruction sets: Stack Accumulator Register Register (register-memory) (load-store) Push A Load A Load R1,A Load R1,A Push B Add B Add R1,B Load R2,B Add Store C Store C, R1 Add R3,R1,R2 Pop C Store C,R3

Pramod Argade CSE 141, Summer Session I, 2005 1-39 MIPS Instruction Set Architecture

Pramod Argade CSE 141, Summer Session I, 2005 1-40 MIPS Instruction Set Architecture z Typical “RISC” Instruction Set designed in 1980’s z MIPS is found in products from: – Silicon Graphics –NEC –Cisco – Broadcom – Nintendo – Sony –Ti – Toshiba z We will study various implementations of MIPS instruction set – Later part of the course!

Pramod Argade CSE 141, Summer Session I, 2005 1-41 MIPS ISA: Key Points z MIPS is a general-purpose register, load-store, fixed- instruction-length architecture. z MIPS is optimized for fast pipelined performance, not for low instruction count z Four principles of ISA – Simplicity favors regularity: regular instruction set – Smaller is faster: small number of formats, registers – Good design demands good compromises: e.g. fixed length instructions – Make the common case fast: encode constant within the instruction

Pramod Argade CSE 141, Summer Session I, 2005 1-42 Overview of MIPS ISA

z Fixed 32-bit instructions z 3-operand, load-store architecture z 32 general-purpose registers – Registers are 32-bits wide (word) – R0 always equals zero. z Addressing modes – Register, immediate, base+displacement, PC-relative and pseudo- direct addressing modes z 3 instruction formats will be covered in the class

Pramod Argade CSE 141, Summer Session I, 2005 1-43 Notes on MIPS Assembly z Comments start with “#” z Destination first (except for “store” instructions) – ADD $t0, $s1, $s2 # $t0 = $s1 + $s2 z Register access $n: register n (e.g. $1 is register 1) z Register naming convention

Name Register number Usage $zero 0 the constant value 0 $v0-$v1 2-3 values for results and expression evaluation $a0-$a3 4-7 arguments $t0-$t7 8-15 temporaries $s0-$s7 16-23 saved $t8-$t9 24-25 more temporaries $gp 28 global pointer $sp 29 stack pointer $fp 30 frame pointer $ra 31 return address

Pramod Argade CSE 141, Summer Session I, 2005 1-44 MIPS Instructions (Covered in this course)

z Arithmetic – add, sub, addi z Logical – sll, srl, and, andi, or, ori, nor z Data transfer – lw, sw, lb, sb, lui z Conditional branch – beq, bne, slt, slti z Unconditional jump –j, jr z Jump and link –jal

Pramod Argade CSE 141, Summer Session I, 2005 1-45 MIPS Arithmetic Instructions z All instructions have 3 operands z Operand order is fixed (destination first) Example: C code: A = B + C MIPS code: add $s0, $s1, $s2 (associated with variables by compiler) z Operands must be registers, only 32 registers provided z Instruction format: 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits R op rs rt rd shamt funct z Design Principle: simplicity favors regularity. Why? z Design Principle: smaller is faster. Why?

Pramod Argade CSE 141, Summer Session I, 2005 1-46 How to specify constants? z Small constants are used quite frequently (50% of operands) e.g., A = A + 5; B = B + 1; C = C - 18; z Solutions – Put 'typical constants' in memory and load them. – create hard-wired registers (like $zero) for constants like one. – Specify constant in the instruction: this commonly used z MIPS Instructions: addi $s3, $t0, 4 slti $s0, $t1, 10 z Instruction Format 6 bits 5 bits 5 bits I op rs rt 16 bit address

Pramod Argade CSE 141, Summer Session I, 2005 1-47 How about larger constants? z We'd like to be able to load a 32 bit constant into a register z Must use two instructions, new "load upper immediate" instruction lui $t0, 1010101010101010 filled with zeros

1010101010101010 0000000000000000 z Then must get the lower order bits right, i.e., ori $t0, $t0, 1010101010101010

1010101010101010 0000000000000000

0000000000000000 1010101010101010 ori

1010101010101010 1010101010101010

Pramod Argade CSE 141, Summer Session I, 2005 1-48 Memory Access Instructions z Load and store instructions z Example: C code: A[8] = h + A[8];

MIPS code: lw $t0, 32($s3) add $t0, $s2, $t0 sw $t0, 32($s3) z Store word has destination last z Remember arithmetic operands are registers, not memory! z Instruction format: 6 bits 5 bits 5 bits I op rs rt 16 bit address

Pramod Argade CSE 141, Summer Session I, 2005 1-49 Control Transfer Instructions z Decision making instructions – Alter the control flow, – i.e., change the "next" instruction to be executed z MIPS conditional branch instructions: bne $t0, $t1, Label beq $t0, $t1, Label z Example: if (i==j) h = i + j; bne $s0, $s1, Label add $s3, $s0, $s1 Label: .... z Instruction format: 6 bits 5 bits 5 bits I op rs rt 16 bit address

Pramod Argade CSE 141, Summer Session I, 2005 1-50 MIPS Conditional Branches z MIPS branches use PC-relative addressing z BEQ, BNE – BEQ $1, $2, addr => if( r1 == r2 ) goto addr z MIPS has no Branch-If-Lless-Than – It is in timing critical path z Set-Less-Than, SLT – SLT $1, $2, $3 => if( $2 < $3) $1 = 1; else 1 = 0 z BEQ, BNE, SLT combined with $0 can implement all branch conditions: – always, never, !=, ==, <=, >=, <, >, >(unsigned), <=(unsigned), ...

Pramod Argade CSE 141, Summer Session I, 2005 1-51 MIPS Jump Instructions z Need to transfer control – Jump to an absolute address – Jump to an address in a register – Jump-And-Link to do procedure call and return z Jump example: – j 0x20000 => PC = 0x20000 z Jump and Link example – jal 0x40000 => $31 = PC+4, PC = 0x40000 z Jump register example: – jr $31 => PC = $31 (This is return instruction!)

Pramod Argade CSE 141, Summer Session I, 2005 1-52 Unconditional Jumps z MIPS unconditional branch instructions: j label z Instruction format: 6 bits J op 26 bit address z Jump uses pseudo-direct addressing mode Program Counter Instruction 426 626

426 00 Jump Destination Address

Pramod Argade CSE 141, Summer Session I, 2005 1-53 MIPS Instruction Format & Machine code z Instruction format 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits R op rs rt rd shamt funct I op rs rt 16 bit address J op 26 bit address z The opcode tells the machine which format z Machine instruction add r1, r2, r3 has – opcode=0, funct=32, rs=2, rt=3, rd=1, sa=0 – Machine code: 000000 00010 00011 00001 00000 100000 0000 0000 0100 0011 0000 1000 0010 0000 0x00430820 z Expected to assemble and disassemble machine code

Pramod Argade CSE 141, Summer Session I, 2005 1-54 Summary of MIPS Instructions MIPS operands Name Example Comments $s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform 32 registers $a0-$a3, $v0-$v1, $gp, arithmetic. MIPS register $zero always equals 0. Register $at is $fp, $sp, $ra, $at reserved for the assembler to handle large constants. Memory[0], Accessed only by data transfer instructions. MIPS uses byte addresses, so 30 2 memory Memory[4], ..., sequential words differ by 4. Memory holds data structures, such as arrays, words Memory[4294967292] and spilled registers, such as those saved on procedure calls. MIPS assembly language Category Instruction Example Meaning Comments add add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; data in registers

Arithmetic subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; data in registers

add immediate addi $s1, $s2, 100 $s1 = $s2 + 100 Used to add constants load word lw $s1, 100($s2) $s1 = Memory[$s2 + 100] Word from memory to register store word sw $s1, 100($s2) Memory[$s2 + 100] = $s1 Word from register to memory Data transfer load byte lb $s1, 100($s2) $s1 = Memory[$s2 + 100] Byte from memory to register store byte sb $s1, 100($s2) Memory[$s2 + 100] = $s1 Byte from register to memory load upper immediate lui $s1, 100 $s1 = 100 * 216 Loads constant in upper 16 bits

branch on equal beq $s1, $s2, 25 if ($s1 == $s2) go to Equal test; PC-relative branch PC + 4 + 100

branch on not equal bne $s1, $s2, 25 if ($s1 != $s2) go to Not equal test; PC-relative PC + 4 + 100 Conditional branch set on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1; Compare less than; for beq, bne else $s1 = 0

set less than slti $s1, $s2, 100 if ($s2 < 100) $s1 = 1; Compare less than constant immediate else $s1 = 0

jump j 2500 go to 10000 Jump to target address Uncondi- jump register jr $ra go to $ra For switch, procedure return tional jump jump and link jal 2500 $ra = PC + 4; go to 10000 For procedure call

Pramod Argade CSE 141, Summer Session I, 2005 1-55 MIPS Addressing Modes

1. Immediate addressing e.g. addi $t0, $t1, 4 op rs rt Immediate Note: Parts 3 and 4 in Figure 2.24 (page 101) Edition 3 are incorrect!

2. Register addressing e.g. sub $t0, $t1, $t2 op rs rt rd . . . funct Registers Register

3. Base addressing e.g. lw $t0, 4( $t2) op rs rt Address Memory

Register + Byte Halfword Word

4. PC-relative addressing e.g. beq $t1, $t2, 32 op rs rt Address Memory

PC + Word

5. Pseudodirect addressing e.g. j 0x1000 op Address Memory

PC Word

Pramod Argade CSE 141, Summer Session I, 2005 1-56 Assembly Language vs. Machine Language

z Assembly provides convenient symbolic representation – Much easier than writing down numbers – e.g., destination first z Machine language is the underlying reality – Used by the processor at run time z Assembly can provide 'pseudo-instructions' – e.g., “move $t0, $t1” exists only in Assembly – would be implemented using “add $t0,$t1,$zero” z When considering performance you should count real instructions

Pramod Argade CSE 141, Summer Session I, 2005 1-57 Other Issues z Things we are not going to cover support for procedures linkers, loaders, memory layout stacks, frames, recursion manipulating strings and pointers interrupts and exceptions system calls and conventions z We've focused on architectural issues – Basics of MIPS assembly language and machine code – We’ll build a processor to execute these instructions.

Pramod Argade CSE 141, Summer Session I, 2005 1-58 Alternative Architectures z Design alternative: – Provide more powerful operations – Goal is to reduce number of instructions executed – Danger is a slower cycle time and/or a higher CPI z Sometimes referred to as “RISC vs. CISC” – Virtually all new instruction sets since 1982 have been RISC – VAX: minimize code size, make assembly language easy instructions from 1 to 54 bytes long!

Pramod Argade CSE 141, Summer Session I, 2005 1-59 Intel IA-32 Architecture z 1978: The Intel 8086 is announced (16 bit architecture) z 1980: The 8087 floating point coprocessor is added z 1982: The 80286 increases address space to 24 bits, +instructions z 1985: The 80386 extends to 32 bits, new addressing modes z 1989-1995: The 80486, Pentium, Pentium Pro add a few instructions (mostly designed for higher performance) z 1997: MMX is added z 1999 Pentium II (same architecture) z 2000 Pentium 4 (144 new multimedia instructions z 2001 Itanium (new ISA which executes x86 code)

Pramod Argade CSE 141, Summer Session I, 2005 1-60 A dominant architecture: 80x86 z See Section 2-16 for a more detailed description z Complexity: – Instructions from 1 to 17 bytes long – One operand must act as both a source and destination – One operand can come from memory – Complex addressing modes e.g., “base or scaled index with 8 or 32 bit displacement” z Saving grace: – The most frequently used instructions are not too difficult to build – Compilers avoid the portions of the architecture that are slow

Pramod Argade CSE 141, Summer Session I, 2005 1-61 Summary z Instruction complexity is only one variable – Lower instruction count vs. higher CPI / lower clock rate z Four principles of ISA – Simplicity favors regularity: regular instruction set – Smaller is faster: small number of formats, small number of registers – Good design demands good compromises: fixed length instructions – Make the common case fast: encode constant within the instruction z Instruction set architecture – A very important abstraction indeed! z In subsequent lectures we will show how to implement a subset of this ISA

Pramod Argade CSE 141, Summer Session I, 2005 1-62