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Pentium ® Pro Family Developer's Manual Pentium Pro Family Developer’s Manual Volume 3: Operating System Writer’s Guide NOTE: The Pentium Pro Family Developer’s Manual consists of three books: Pentium Pro Family Developer’s Manual, Volume 1: Specifications (Order Number 242690); Pentium Pro Family Developer’s Manual, Volume 2: Programmer’s Reference Manual (Order Number 242691); and the Pentium Pro Family Developer’s Manual, Volume 3: Operating System Writer’s Guide (Order Number 242692). Please refer to all three volumes when evaluating your design needs. December 1995 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The Pentium® Pro processor may contain design defects or errors known as errata. Current characterized errata are available on request. *Third-party brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 COPYRIGHT © INTEL CORPORATION 1996 TABLE OF CONTENTS CHAPTER 1 ABOUT THIS MANUAL 1.1. OVERVIEW OF THE PENTIUM PRO FAMILY DEVELOPER’S MANUAL, VOLUME 3 . 1-1 1.2. OVERVIEW OF THE PENTIUM PRO PROGRAMMER’S REFERENCE MANUAL 1-3 1.3. NOTATIONAL CONVENTIONS. 1-4 1.3.1. Bit and Byte Order . .1-4 1.3.2. Reserved Bits and Software Compatibility . .1-5 1.3.3. Instruction Operands . .1-5 1.3.4. Hexadecimal and Binary Numbers . .1-6 1.3.5. Segmented Addressing . .1-6 1.3.6. Exceptions . .1-6 1.4. RELATED LITERATURE . 1-7 CHAPTER 2 SYSTEM ARCHITECTURE OVERVIEW 2.1. OVERVIEW OF THE SYSTEM-LEVEL ARCHITECTURE . 2-1 2.1.1. Global and Local Descriptor Tables . .2-3 2.1.2. System Segments, Segment Descriptors, and Gates . .2-3 2.1.3. Task State Segments and Task Gates . .2-4 2.1.4. Interrupt and Exception Handling . .2-4 2.1.5. Memory Management . .2-4 2.1.6. System Registers . .2-5 2.1.7. Other System Resources . .2-6 2.2. MODES OF OPERATION . 2-6 2.3. SYSTEM FLAGS AND FIELDS IN THE EFLAGS REGISTER . 2-7 2.4. MEMORY-MANAGEMENT REGISTERS . 2-10 2.4.1. Global Descriptor Table Register (GDTR). .2-10 2.4.2. Local Descriptor Table Register (LDTR) . .2-11 2.4.3. IDTR Interrupt Descriptor Table Register . .2-11 2.4.4. Task Register (TR) . .2-11 2.5. CONTROL REGISTERS . 2-12 2.5.1. CPUID Qualification of Control Register Flags . .2-17 2.6. SYSTEM INSTRUCTION SUMMARY . 2-17 2.6.1. Loading and Storing System Registers . .2-19 2.6.2. Verifying of Access Privileges . .2-19 2.6.3. Loading and Storing Debug Registers. .2-20 2.6.4. Invalidating Caches and TLBs. .2-20 2.6.5. Controlling the Processor . .2-20 2.6.6. Reading Performance Monitoring and Time Stamp Counters. .2-21 2.6.7. Reading and Writing Model-Specific Registers . .2-21 CHAPTER 3 PROTECTED-MODE MEMORY MANAGEMENT 3.1. MEMORY MANAGEMENT OVERVIEW . 3-1 3.2. USING SEGMENTS. 3-3 3.2.1. Flat Model . .3-3 3.2.2. Protected Flat Model . .3-4 iii TABLE OF CONTENTS 3.2.3. Multi-Segment Model. .3-5 3.2.4. Paging and Segmentation . .3-6 3.3. PHYSICAL ADDRESS SPACE . 3-7 3.4. LOGICAL AND LINEAR ADDRESSES . 3-7 3.4.1. Segment Selectors . .3-8 3.4.2. Segment Registers . .3-9 3.4.3. Segment Descriptors. .3-10 3.4.3.1. Code and Data Segment-Descriptor Types . .3-14 3.5. SYSTEM SEGMENT-DESCRIPTOR TYPES . 3-15 3.5.1. Segment Descriptor Tables. .3-16 3.6. PAGING (VIRTUAL MEMORY) . 3-18 3.6.1. Paging Options . .3-19 3.6.2. Page Tables and Directories . .3-20 3.6.2.1. Linear Address Translation (4-KByte Pages) . .3-20 3.6.2.2. Linear Address Translation (4-MByte Pages). .3-21 3.6.2.3. Mixing 4-KByte and 4-MByte Pages . .3-22 3.6.3. Base Address of the Page Directory . .3-22 3.6.4. Page-Directory and Page-Table Entries . .3-23 3.6.5. Not Present Page-Directory and Page-Table Entries . .3-27 3.7. TRANSLATION LOOKASIDE BUFFERS (TLBS) . 3-28 3.8. PHYSICAL ADDRESS EXTENSION . 3-29 3.8.1. Linear Address Translation With Extended Addressing Enabled (4-KByte Pages) . .3-29 3.8.2. Linear Address Translation With Extended Addressing Enabled (2-MByte Pages) . .3-30 3.8.3. Accessing the Full Extended Physical Address Space With the Extended Page Table Structure . .3-32 3.8.4. Page-Directory and Page-Table Entries With Extended Addressing Enabled . .3-32 3.9. MAPPING SEGMENTS TO PAGES . 3-34 CHAPTER 4 PROTECTION 4.1. ENABLING AND DISABLING SEGMENT AND PAGE PROTECTION . 4-1 4.2. FIELDS AND FLAGS USED FOR SEGMENT-LEVEL AND PAGE-LEVEL PROTECTION 4-2 4.3. LIMIT CHECKING . 4-4 4.4. TYPE CHECKING . 4-5 4.4.1. Null Segment Selector Checking. .4-6 4.5. PRIVILEGE LEVELS . 4-6 4.6. PRIVILEGE LEVEL CHECKING WHEN ACCESSING DATA SEGMENTS 4-8 4.6.1. Accessing Data in Code Segments. .4-9 4.7. PRIVILEGE LEVEL CHECKING WHEN LOADING THE SS REGISTER . 4-10 4.8. PRIVILEGE LEVEL CHECKING WHEN TRANSFERRING PROGRAM CONTROL BETWEEN CODE SEGMENTS 4-10 4.8.1. Direct Calls or Jumps to Code Segments . .4-10 4.8.1.1. Accessing Nonconforming Code Segments . .4-11 4.8.1.2. Accessing Conforming Code Segments. .4-13 4.8.2. Gate Descriptors . .4-13 4.8.3. Call Gates . .4-14 4.8.4. Accessing a Code Segment Through a Call Gate. .4-15 4.8.5. Stack Switching . ..
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