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Computer Organization EECC 550 • Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Week 1 Notation (RTN)

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Computer Organization EECC 550 • Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Week 1 Notation (RTN) Computer Organization EECC 550 • Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Week 1 Notation (RTN). [Chapters 1, 2] • Instruction Set Architecture (ISA) Characteristics and Classifications: CISC Vs. RISC. [Chapter 2] Week 2 • MIPS: An Example RISC ISA. Syntax, Instruction Formats, Addressing Modes, Encoding & Examples. [Chapter 2] • Central Processor Unit (CPU) & Computer System Performance Measures. [Chapter 4] Week 3 • CPU Organization: Datapath & Control Unit Design. [Chapter 5] Week 4 – MIPS Single Cycle Datapath & Control Unit Design. – MIPS Multicycle Datapath and Finite State Machine Control Unit Design. Week 5 • Microprogrammed Control Unit Design. [Chapter 5] – Microprogramming Project Week 6 • Midterm Review and Midterm Exam Week 7 • CPU Pipelining. [Chapter 6] • The Memory Hierarchy: Cache Design & Performance. [Chapter 7] Week 8 • The Memory Hierarchy: Main & Virtual Memory. [Chapter 7] Week 9 • Input/Output Organization & System Performance Evaluation. [Chapter 8] Week 10 • Computer Arithmetic & ALU Design. [Chapter 3] If time permits. Week 11 • Final Exam. EECC550 - Shaaban #1 Lec # 1 Winter 2005 11-29-2005 Computing System History/Trends + Instruction Set Architecture (ISA) Fundamentals • Computing Element Choices: – Computing Element Programmability – Spatial vs. Temporal Computing – Main Processor Types/Applications • General Purpose Processor Generations • The Von Neumann Computer Model • CPU Organization (Design) • Recent Trends in Computer Design/performance • Hierarchy of Computer Architecture • Hardware Description: Register Transfer Notation (RTN) • Computer Architecture Vs. Computer Organization • Instruction Set Architecture (ISA): – Definition and purpose – ISA Specification Requirements – Main General Types of Instructions – ISA Types and characteristics – Typical ISA Addressing Modes – Instruction Set Encoding – Instruction Set Architecture Tradeoffs – Complex Instruction Set Computer (CISC) – Reduced Instruction Set Computer (RISC) – Evolution of Instruction Set Architectures (Chapters 1, 2) EECC550 - Shaaban #2 Lec # 1 Winter 2005 11-29-2005 Computing Element Choices • General Purpose Processors (GPPs): Intended for general purpose computing (desktops, servers, clusters..) • Application-Specific Processors (ASPs): Processors with ISAs and architectural features tailored towards specific application domains – E.g Digital Signal Processors (DSPs), Network Processors (NPs), Media Processors, Graphics Processing Units (GPUs), Vector Processors??? ... • Co-Processors: A hardware (hardwired) implementation of specific algorithms with limited programming interface (augment GPPs or ASPs) • Configurable Hardware: – Field Programmable Gate Arrays (FPGAs) – Configurable array of simple processing elements • Application Specific Integrated Circuits (ASICs): A custom VLSI hardware solution for a specific computational task • The choice of one or more depends on a number of factors including: - Type and complexity of computational algorithm (general purpose vs. Specialized) - Desired level of flexibility/ - Performance requirements programmability - Development cost/time - System cost - Power requirements - Real-time constrains The main goal of this course is the study of fundamental design EECC550 - Shaaban techniques for General Purpose Processors EECC550 - Shaaban #3 Lec # 1 Winter 2005 11-29-2005 Computing Element Choices The main goal of this course is the study General Purpose of fundamental design techniques Processors for General Purpose Processors (GPPs): Processor : Programmable computing element that Flexibility runs programs written using a pre-defined set of Application-Specific instructions Processors (ASPs) Configurable Hardware Programmability / Selection Factors: - Type and complexity of computational algorithms Co-Processors (general purpose vs. Specialized) Application Specific - Desired level of flexibility - Performance Integrated Circuits - Development cost - System cost (ASICs) - Power requirements - Real-time constrains Specialization , Development cost/time Performance/Chip Area/Watt Performance (Computational Efficiency) EECC550 - Shaaban #4 Lec # 1 Winter 2005 11-29-2005 Computing Element Choices: ComputingComputing ElementElement ProgrammabilityProgrammability Fixed Function: Programmable: • Computes one function (e.g. • Computes “any” FP-multiply, divider, DCT) computable function (e.g. • Function defined at Processors) fabrication time • Function defined after • e.g hardware (ASICs) fabrication Parameterizable Hardware: Performs limited “set” of functions e.g. Co-Processors Processor = Programmable computing element that runs programs written using pre-defined instructions EECC550 - Shaaban #5 Lec # 1 Winter 2005 11-29-2005 Computing Element Choices: SpatialSpatial vs.vs. TemporalTemporal ComputingComputing Spatial Temporal (using hardware) (using software/program running on a processor) Processor Instructions Processor = Programmable computing element that runs programs written using a pre-defined set of instructions EECC550 - Shaaban #6 Lec # 1 Winter 2005 11-29-2005 MainMain ProcessorProcessor Types/ApplicationsTypes/Applications The main goal of this course is the study of fundamental design techniques for General Purpose Processors • General Purpose Processors (GPPs) - high performance. – RISC or CISC: Intel P4, IBM Power4, SPARC, PowerPC, MIPS ... – Used for general purpose software – Heavy weight OS - Windows, UNIX – Workstations, Desktops (PC’s), Clusters • Embedded processors and processor cores Increasing Cost/Complexity – e.g: Intel XScale, ARM, 486SX, Hitachi SH7000, NEC V800... – Often require Digital signal processing (DSP) support or other application-specific support (e.g network, media processing) – Single program volume Increasing – Lightweight, often realtime OS or no OS – Examples: Cellular phones, consumer electronics .. (e.g. CD players) • Microcontrollers – Extremely cost/power sensitive – Single program – Small word size - 8 bit common – Highest volume processors by far – Examples: Control systems, Automobiles, toasters, thermostats, ... EECC550 - Shaaban Examples of Application-Specific Processors #7 Lec # 1 Winter 2005 11-29-2005 TheThe ProcessorProcessor DesignDesign SpaceSpace Application specific architectures for performance Embedded Microprocessors Real-time constraints processors GPPs Specialized applications Low power/cost constraints Performance is everything & Software rules Performance The main goal of this course is the Microcontrollers study of fundamental design techniques for General Purpose Processors Cost is everything Chip Area, Power Processor Cost complexity Processor = Programmable computing element EECC550 - Shaaban that runs programs written using a pre-defined set of instructions #8 Lec # 1 Winter 2005 11-29-2005 General Purpose Processor/Computer System Generations Classified according to implementation technology: • The First Generation, 1946-59: Vacuum Tubes, Relays, Mercury Delay Lines: – ENIAC (Electronic Numerical Integrator and Computer): First electronic computer, 18000 vacuum tubes, 1500 relays, 5000 additions/sec (1944). – First stored program computer: EDSAC (Electronic Delay Storage Automatic Calculator), 1949. • The Second Generation, 1959-64: Discrete Transistors. – e.g. IBM Main frames • The Third Generation, 1964-75: Small and Medium-Scale Integrated (MSI) Circuits. – e.g Main frames (IBM 360) , mini computers (DEC PDP-8, PDP-11). • The Fourth Generation, 1975-Present: The Microcomputer. VLSI-based Microprocessors (single-chip processor) – First microprocessor: Intel’s 4-bit 4004 (2300 transistors), 1970. – Personal Computer (PCs), laptops, PDAs, servers, clusters … – Reduced Instruction Set Computer (RISC) 1984 Common factor among all generations: All target the The Von Neumann Computer Model or paradigm EECC550 - Shaaban #9 Lec # 1 Winter 2005 11-29-2005 TheThe VonVon--NeumannNeumann ComputerComputer ModelModel • Partitioning of the programmable computing engine into components: – Central Processing Unit (CPU): Control Unit (instruction decode, sequencing of operations), Datapath (registers, arithmetic and logic unit, buses). – Memory: Instruction (program) and operand (data) storage. – Input/Output (I/O). – The stored program concept: Instructions from an instruction set are fetched from a common memory and executed one at a time. Control Input Memory - (instructions, data) Datapath registers Output ALU, buses Computer System CPU I/O Devices Major CPU Performance Limitation: The Von Neumann computing model implies sequential execution one instruction at a time EECC550 - Shaaban #10 Lec # 1 Winter 2005 11-29-2005 GenericGeneric CPUCPU MachineMachine InstructionInstruction ProcessingProcessing StepsSteps (Implied by The Von Neumann Computer Model) Instruction Obtain instruction from program storage Fetch (memory) Instruction Determine required actions and instruction size Decode Operand Locate and obtain operand data Fetch Execute Compute result value or status Result Deposit results in storage for later use Store Next Determine successor or next instruction Instruction Major CPU Performance Limitation: The Von Neumann computing model EECC550 - Shaaban implies sequential execution one instruction at a time implies sequential execution one instruction at a time #11 Lec # 1 Winter 2005 11-29-2005 HardwareHardware ComponentsComponents ofof ComputerComputer SystemsSystems Five classic components of all computers: 1. Control Unit; 2. Datapath; 3. Memory; 4. Input;
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