SPIM S20: a MIPS R2000 Simulator∗
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MIPS IV Instruction Set
MIPS IV Instruction Set Revision 3.2 September, 1995 Charles Price MIPS Technologies, Inc. All Right Reserved RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure of the technical data contained in this document by the Government is subject to restrictions as set forth in subdivision (c) (1) (ii) of the Rights in Technical Data and Computer Software clause at DFARS 52.227-7013 and / or in similar or successor clauses in the FAR, or in the DOD or NASA FAR Supplement. Unpublished rights reserved under the Copyright Laws of the United States. Contractor / manufacturer is MIPS Technologies, Inc., 2011 N. Shoreline Blvd., Mountain View, CA 94039-7311. R2000, R3000, R6000, R4000, R4400, R4200, R8000, R4300 and R10000 are trademarks of MIPS Technologies, Inc. MIPS and R3000 are registered trademarks of MIPS Technologies, Inc. The information in this document is preliminary and subject to change without notice. MIPS Technologies, Inc. (MTI) reserves the right to change any portion of the product described herein to improve function or design. MTI does not assume liability arising out of the application or use of any product or circuit described herein. Information on MIPS products is available electronically: (a) Through the World Wide Web. Point your WWW client to: http://www.mips.com (b) Through ftp from the internet site “sgigate.sgi.com”. Login as “ftp” or “anonymous” and then cd to the directory “pub/doc”. (c) Through an automated FAX service: Inside the USA toll free: (800) 446-6477 (800-IGO-MIPS) Outside the USA: (415) 688-4321 (call from a FAX machine) MIPS Technologies, Inc. -
MIPS Architecture • MIPS (Microprocessor Without Interlocked Pipeline Stages) • MIPS Computer Systems Inc
Spring 2011 Prof. Hyesoon Kim MIPS Architecture • MIPS (Microprocessor without interlocked pipeline stages) • MIPS Computer Systems Inc. • Developed from Stanford • MIPS architecture usages • 1990’s – R2000, R3000, R4000, Motorola 68000 family • Playstation, Playstation 2, Sony PSP handheld, Nintendo 64 console • Android • Shift to SOC http://en.wikipedia.org/wiki/MIPS_architecture • MIPS R4000 CPU core • Floating point and vector floating point co-processors • 3D-CG extended instruction sets • Graphics – 3D curved surface and other 3D functionality – Hardware clipping, compressed texture handling • R4300 (embedded version) – Nintendo-64 http://www.digitaltrends.com/gaming/sony- announces-playstation-portable-specs/ Not Yet out • Google TV: an Android-based software service that lets users switch between their TV content and Web applications such as Netflix and Amazon Video on Demand • GoogleTV : search capabilities. • High stream data? • Internet accesses? • Multi-threading, SMP design • High graphics processors • Several CODEC – Hardware vs. Software • Displaying frame buffer e.g) 1080p resolution: 1920 (H) x 1080 (V) color depth: 4 bytes/pixel 4*1920*1080 ~= 8.3MB 8.3MB * 60Hz=498MB/sec • Started from 32-bit • Later 64-bit • microMIPS: 16-bit compression version (similar to ARM thumb) • SIMD additions-64 bit floating points • User Defined Instructions (UDIs) coprocessors • All self-modified code • Allow unaligned accesses http://www.spiritus-temporis.com/mips-architecture/ • 32 64-bit general purpose registers (GPRs) • A pair of special-purpose registers to hold the results of integer multiply, divide, and multiply-accumulate operations (HI and LO) – HI—Multiply and Divide register higher result – LO—Multiply and Divide register lower result • a special-purpose program counter (PC), • A MIPS64 processor always produces a 64-bit result • 32 floating point registers (FPRs). -
Computer Organization EECC 550 • Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Week 1 Notation (RTN)
Computer Organization EECC 550 • Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Week 1 Notation (RTN). [Chapters 1, 2] • Instruction Set Architecture (ISA) Characteristics and Classifications: CISC Vs. RISC. [Chapter 2] Week 2 • MIPS: An Example RISC ISA. Syntax, Instruction Formats, Addressing Modes, Encoding & Examples. [Chapter 2] • Central Processor Unit (CPU) & Computer System Performance Measures. [Chapter 4] Week 3 • CPU Organization: Datapath & Control Unit Design. [Chapter 5] Week 4 – MIPS Single Cycle Datapath & Control Unit Design. – MIPS Multicycle Datapath and Finite State Machine Control Unit Design. Week 5 • Microprogrammed Control Unit Design. [Chapter 5] – Microprogramming Project Week 6 • Midterm Review and Midterm Exam Week 7 • CPU Pipelining. [Chapter 6] • The Memory Hierarchy: Cache Design & Performance. [Chapter 7] Week 8 • The Memory Hierarchy: Main & Virtual Memory. [Chapter 7] Week 9 • Input/Output Organization & System Performance Evaluation. [Chapter 8] Week 10 • Computer Arithmetic & ALU Design. [Chapter 3] If time permits. Week 11 • Final Exam. EECC550 - Shaaban #1 Lec # 1 Winter 2005 11-29-2005 Computing System History/Trends + Instruction Set Architecture (ISA) Fundamentals • Computing Element Choices: – Computing Element Programmability – Spatial vs. Temporal Computing – Main Processor Types/Applications • General Purpose Processor Generations • The Von Neumann Computer Model • CPU Organization (Design) • Recent Trends in Computer Design/performance • Hierarchy -
IDT79R4600 and IDT79R4700 RISC Processor Hardware User's Manual
IDT79R4600™ and IDT79R4700™ RISC Processor Hardware User’s Manual Revision 2.0 April 1995 Integrated Device Technology, Inc. Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any respon- sibility for use of any circuitry described other than the circuitry embodied in an IDT product. ITD makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights, or other rights of Integrated Device Technology, Inc. LIFE SUPPORT POLICY Integrated Device Technology’s products are not authorized for use as critical components in life sup- port devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT. 1. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accor- dance with instructions for use provided in the labeling, can be reasonably expected to result in a sig- nificant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. -
MOTOROLA 1995 112P
High-Performance Internal Product Portfolio Overview Issue 10 Fourth Quarter, 1995 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and µ are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. -
Introduction to Playstation®2 Architecture
Introduction to PlayStation®2 Architecture James Russell Software Engineer SCEE Technology Group In this presentation ä Company overview ä PlayStation 2 architecture overview ä PS2 Game Development ä Differences between PS2 and PC. Technology Group 1) Sony Computer Entertainment Overview SCE Europe (includes Aus, NZ, Mid East, America Technology Group Japan Southern Africa) Sales ä 40 million sold world-wide since launch ä Since March 2000 in Japan ä Since Nov 2000 in Europe/US ä New markets: Middle East, India, Korea, China ä Long term aim: 100 million within 5 years of launch ä Production facilities can produce 2M/month. Technology Group Design considerations ä Over 5 years, we’ll make 100,000,000 PS2s ä Design is very important ä Must be inexpensive (or should become that way) ä Technology must be ahead of the curve ä Need high performance, low price. Technology Group How to achieve this? ä Processor yield ä High CPU clock speed means lower yields ä Solution? ä Low CPU clock speed, but high parallelism ä Nothing readily available ä SCE designs custom chips. Technology Group 2) Technical Aspects of PlayStation 2 ä 128-bit CPU core “Emotion Engine” ä + 2 independent Vector Units ä + Image Processing Unit (for MPEG) ä GS - “Graphics Synthesizer” GPU ä SPU2 - Sound Processing Unit ä I/O Processor (CD/DVD, USB, i.Link). Technology Group “Emotion Engine” - Specifications ä CPU Core 128 bit CPU ä System Clock 300MHz ä Bus Bandwidth 3.2GB/sec ä Main Memory 32MB (Direct Rambus) ä Floating Point Calculation 6.2 GFLOPS ä 3D Geometry Performance 66 Million polygons/sec. -
Sony's Emotionally Charged Chip
VOLUME 13, NUMBER 5 APRIL 19, 1999 MICROPROCESSOR REPORT THE INSIDERS’ GUIDE TO MICROPROCESSOR HARDWARE Sony’s Emotionally Charged Chip Killer Floating-Point “Emotion Engine” To Power PlayStation 2000 by Keith Diefendorff rate of two million units per month, making it the most suc- cessful single product (in units) Sony has ever built. While Intel and the PC industry stumble around in Although SCE has cornered more than 60% of the search of some need for the processing power they already $6 billion game-console market, it was beginning to feel the have, Sony has been busy trying to figure out how to get more heat from Sega’s Dreamcast (see MPR 6/1/98, p. 8), which has of it—lots more. The company has apparently succeeded: at sold over a million units since its debut last November. With the recent International Solid-State Circuits Conference (see a 200-MHz Hitachi SH-4 and NEC’s PowerVR graphics chip, MPR 4/19/99, p. 20), Sony Computer Entertainment (SCE) Dreamcast delivers 3 to 10 times as many 3D polygons as and Toshiba described a multimedia processor that will be the PlayStation’s 34-MHz MIPS processor (see MPR 7/11/94, heart of the next-generation PlayStation, which—lacking an p. 9). To maintain king-of-the-mountain status, SCE had to official name—we refer to as PlayStation 2000, or PSX2. do something spectacular. And it has: the PSX2 will deliver Called the Emotion Engine (EE), the new chip upsets more than 10 times the polygon throughput of Dreamcast, the traditional notion of a game processor. -
RIP Architecture L Technical Information
L Technical Information RIP Architecture A raster image processor (RIP) is a computer with a very specific task to perform. It translates a series of computer commands into something that an output device can print. For an imagesetter, this means the instructions that instruct the laser to expose certain areas on the film. Acronyms ASIC Application Specific Integrated Circuit RIP architecture refers to the CISC Complex Instruction Set Computer 1An excellent source of design of the RIP, particularly CPU Central Processing Unit information on computer EPROM Erasable Programmable Read-Only technology is The Computer the hardware and software Memory Glossary by Alan Freedman. that make the RIP work. It is I/O Input/Output It is available from The impossible to discuss RIP MHz Megahertz Computer Language architecture without MIPS Million Instructions Per Second Company, (215) 297-5999. mentioning a number of 1 (also the name of a company that computer buzz words , many manufactures CPUs) of which are acronyms (see PROM Programmable Read-Only Memory list to right). And so to begin, RIP Raster Image Processor we’ll start with a review of RISC Reduced Instruction Set Computer computer basics, and see how SPARC Scalable Performance ARChitecture those principles apply to RIPs. TAXI Transparent Asynchronous Xmitter receiver Interface XMO eXtended Memory Option Computer basics The CPU of a computer is where the bulk of the computing gets done. Microprocessor designations The CPU may also be called the Intel Corporation microprocessor if the CPU is built on a • 8080, 8088 single miniaturized electronic circuit (i.e. • 8086, 80286, 80386, 80486 chip). -
EOL Notification – E200 & E270 Series Industrial SLC Eusb Modules
EOL NOTIFICATION DOCUMENT TITLE: EOL Notification – E200 & E270 Series Industrial SLC eUSB Modules DEPT: Marketing DOCUMENT NO. 412-0052-00 PRINT DATE: 6/9/2020 REV A Page 1 of 2 REVISION HISTORY CHANGE REV DESCRIPTION OF CHANGE DATE REQUEST # A Initial Release 6/12/20 NA Title of EOL: E200 & E270 Series Industrial SLC eUSB Modules Date: 6/12/2020 EOL No: 412-0052-00 EOL Effective Date: 6/15/2020 Last Time Buy Date: 11/13/2020 Last Time Ship Date: 12/15/2021 Description: Due to the discontinuation of the controller and/or older process nodes of SLC NAND flash by the manufacturers, Delkin Devices is announcing end of life on the E200 & E270 Series Industrial SLC eUSB Module product lines. Products Affected: See part number list on page 2. Impact of Change: The part numbers listed will be offered for a Last Time Buy through 11/13/2020 and Last Time Shipment through 12/15/2021, subject to component availability from the manufacturer. Delkin recommends immediate qualification of our E300 Series Industrial SLC eUSB Module, which utilizes the latest controller and flash technology. Reference Documents/Attachments: Engineering Specification 401-0451-00 for the new E300 Series Industrial SLC eUSB Module can be downloaded at Delkin.com. Qualification Samples: Qualification samples of the replacement part numbers are available now, and you are encouraged to contact your Delkin Sales Representative to discuss your requirements and arrange for samples. Please direct any other questions to your Delkin Sales Representative. Sincerely, Tina Guidotti Director of Product Management Delkin Devices, Inc. -
3 Financial Mathematics
23/09/2017 SIMPLE INTEREST FINANCE AND GROWTH Interest is based only on the original • Simple Interest sum of money • Hire Purchase Agreements Rand value of interest remains constant • Compound Interest Formula: A = P(1 + n.i) • Inflation A = Total Amount • Population Growth P = Principle int erest _ rate • i Exchange Rates i = Interest Rate (where 100 ) n = Number of Years 1 2 Example 1: R1500 is invested for 2 years at 18% per Example 2: R50 000 is invested for 18 years at 16% p.a. annum (p.a.) simple interest. simple interest. Determine: a) the value of the investment after 18 years Value of investment after 1 year: A = R1500 + 18% of R1500 b) the simple interest earned after 18 years = R1500 + R270 P = R50 000 ; I = 0.16 p.a ; n = 18 years = R1770 a) A = P(1 + i.n) Value of investment after 2 years: A = R50 000 (1 + 0,16.18) A = R1770 + 18% of R1500 A = R194 000 = R1770 + R270 = R2040 b) Interest received Therefore value of interest remains constant. = A - P = R194 000 – R50 000 Using the Simple Interest formula: = R144 000. A = P(1 + i.n) A = R1500(1 + 0,18 x 2) A = R2040 3 4 Example 3: How much was invested 4 years ago if the Example 4: R1 600 accumlates to R3 000 after 4 years. value of the investment is currently worth R7 000? The Find the interest rate if the investment earned simple interest rate was 7% p.a. simple interest. interest. A = R3000 ; P = R1600 ; n = 4 years A = R7000 ; n = 4 years ; i = 0.07 A = P(1 + i.n) A = P(1+i.n) R3000 = R1600(1 + i.4) R7000 = P(1 + 0,07 x 4) R3000 = R1600 + 4800i R7000 = P(l + 0,28) R3000 – R1600 = 4800i R7000 = P(1,28) R1500 = 4800i R1500 4800 = i R7000 i = 0,3125 P 1,28 r = i x 100 = 0,3125 x 100 P = R5468,75 = 31,25% Simple Interest Calculator 5 6 1 23/09/2017 3. -
R1000/R2000/R3000 R4000/R6000/R8000-W Series Compact, Pressure Gauge Embedded
Regulator standard white Series R1000/R2000/R3000 R4000/R6000/R8000-W Series Compact, pressure gauge embedded. Port size: 1/8 to 1 JIS symbol Specifications Descriptions R1000-W R2000-W R3000-W R4000-W R6000-W R8000-W Appearance Working fluid Compressed air Max. working pressure MPa 1 Withstanding pressure MPa 1.5 Ambient temperature range °C 5 to 60 Note 1 Set pressure range MPa 0.05 to 0.85 Relief With relief mechanism 1/8, 1/4 1/4, 3/8 1/4, 3/8 1/4, 3/8, 1/2 3/4, 1 3/4, 1 Port size Rc, NPT, G (3/8 uses an adaptor) (1/2 uses an adaptor) (1/2 uses an adaptor) (3/4 uses an adaptor) (1 1/4 uses an adaptor) (1 1/4 uses an adaptor) Product weight kg 0.16 0.31 0.45 0.7 1.0 1.6 Standard accessories Pressure gauge, nut for panel mount Pressure gauge Note 1: The working temperature range of the pressure switch with indicator PPD assembly "R1" is 5 to 50°C. Ozone specifications (Ending 12) R*000 - ··· - W ··· - P11 Clean room specifications (catalog No. CB-033S) MDust generation preventing structure for use in cleanrooms R*000 - ··········· - P7* Secondary battery compatible specifications (catalog No. CC-947) MStructured for use in secondary battery manufacturing processes R*000 - ··········· - P4* 378 Regulator Series How to order How to order * Refer to page 274 for the explanation of the option. A Model no. R R R R R R R1000 6 W L A6W 1 2 3 4 6 8 G Attachment (attached) 0 0 0 0 0 0 F Piping adaptor set (attached) 0 0 0 0 0 0 0 0 0 0 0 0 Symbol Descriptions A Model no. -
R4600 Product Overview
Ò FOURTH GENERATION 64-BIT RISC MICROPROCESSOR IDT79R4600 Integrated Device Technology, Inc. FEATURES: - Standby mode reduces internal power to 90mA @ 5V • True 64-bit microprocessor and 60mA @ 3.3V (450mW @ 5V and 400mW @ - 64-bit integer operations 3.3V). • Standard operating system support includes: - 64-bit floating-point operations - Microsoft Windows NT - 64-bit registers - 64-bit virtual address space - UNISOFT Unix System V.4 • High-performance microprocessor • Fully software compatible with R4000 RISC Processor - 150 peak MIPS at 150MHz Family - 50peak MFLOP/s at 150MHz • Available in R4000PC/R4000PC pin-compatible 179-pin - 96 SPECint92 at 150Mz PGA or 208-pin MQUAD - Two-way set associative caches • 50MHz, 67MHz, 75MHz input frequencies with mode bit • High level of integration dependent output clock frequencies - 64-bit integer CPU - On-chip clock doubler for 150MHz pipeline - 64-bit floating-point unit • 64GB physical address space - 16KB instruction cache; 16KB data cache • Processor family for a wide variety of applications - Flexible MMU with large TLB - Desktop workstations and PCs • Low-power operation - Deskside or departmental servers - 3.3V or 5V power supply options - High-performance embedded applications (e.g. color - 20mW/MHZ typical internal power dissipation printers, multi-media and internetworking.) (2.0W @ 100MHz, 3.3V) - Notebooks BLOCK DIAGRAM: Data Tag A Data Set A Instruction Set A DTLB Physical Store Buffer Data Tag B SysAD Instruction Select Write Buffer Address Buffer Instruction Register Read Buffer