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R4600 Product Overview Ò FOURTH GENERATION 64-BIT RISC MICROPROCESSOR IDT79R4600 Integrated Device Technology, Inc. FEATURES: - Standby mode reduces internal power to 90mA @ 5V • True 64-bit microprocessor and 60mA @ 3.3V (450mW @ 5V and 400mW @ - 64-bit integer operations 3.3V). • Standard operating system support includes: - 64-bit floating-point operations - Microsoft Windows NT - 64-bit registers - 64-bit virtual address space - UNISOFT Unix System V.4 • High-performance microprocessor • Fully software compatible with R4000 RISC Processor - 150 peak MIPS at 150MHz Family - 50peak MFLOP/s at 150MHz • Available in R4000PC/R4000PC pin-compatible 179-pin - 96 SPECint92 at 150Mz PGA or 208-pin MQUAD - Two-way set associative caches • 50MHz, 67MHz, 75MHz input frequencies with mode bit • High level of integration dependent output clock frequencies - 64-bit integer CPU - On-chip clock doubler for 150MHz pipeline - 64-bit floating-point unit • 64GB physical address space - 16KB instruction cache; 16KB data cache • Processor family for a wide variety of applications - Flexible MMU with large TLB - Desktop workstations and PCs • Low-power operation - Deskside or departmental servers - 3.3V or 5V power supply options - High-performance embedded applications (e.g. color - 20mW/MHZ typical internal power dissipation printers, multi-media and internetworking.) (2.0W @ 100MHz, 3.3V) - Notebooks BLOCK DIAGRAM: Data Tag A Data Set A Instruction Set A DTLB Physical Store Buffer Data Tag B SysAD Instruction Select Write Buffer Address Buffer Instruction Register Read Buffer Instruction Tag A ITLB Physical Data Set B Instruction Set B Instruction Tag B DBus IBus Control Tag AuxTag Floating-point Integer Control Load Aligner Register File Joint TLB Integer Register File Unpacker/Packer Integer/Address Adder Data TLB Virtual Floating-point Coprocessor 0 DVA Add/Sub/Cvt/Div/Sqrt Shifter/Store Aligner Integer Divide Logic Unit PC Incrementer Floating-point Control Floating-point/Integer System/Memory Branch Adder Multiply Control Instruction TLB Virtual IVA Phase Lock Loop, Clocks Program Counter 3038 drw 01 The IDT logo is a registered trademark and Orion, R4600, R4400, R3081, R3052, R3051, R3041, RISController, and RISCore are trademarks of Intergrated Device Technology, Inc. All others are trademarks of their respective companies. COMMERCIAL TEMPERATURE RANGE March 1994 DSC 9075/1 1994 Integrated Device Technology, Inc. 5.7 1 IDT79R4600 COMMERCIAL TEMPERATURE RANGE DESCRIPTION: operating systems and applications. The IDT79R4600 supports a wide variety of processor- The 64-bit computing and addressing capability of the based applications, from 32-bit Windows NT desktop or R4600 enables a wide variety of capabilities previously lim- notebook systems through high-performance, 64-bit OLTP ited by a smaller address space. For example, the large systems. Compatible with the IDT79R4000PC family for address space allows operating systems with extensive file both hardware and software, the R4600 will serve in many mapping; direct access to large files can occur without of the same applications, but, in addition supports low- explicit I/O calls. Applications such as large CAD data- power operation for applications such as “green” desktops bases, multi-media, and high-quality image storage and and notebook computers. It does not provide integrated retrieval all directly benefit from the enlarged address secondary cache and multiprocessor support as found in space. the R4000SC and R4000MC, but an external secondary This data sheet provides an overview of the features and cache can lastly be designed around it. The large on-chip architecture of the R4600 CPU. A more detailed description two-way set associative caches make this unnecessary in of the processor is available in the “IDT79R4600 Processor most embedded control applications. Hardware User’s Manual”, available from IDT. Further The R4600 brings R4000SC performance levels to the information on development support, applications notes, R4000PC package, while at the same time providing lower and complementary products are also available from your cost and lower power. It does this by providing larger on- local IDT sales representative. chip caches that are two-way set associative, fewer pipe- line stalls, and early restart for data cache misses. The HARDWARE OVERVIEW result is 102 SPECint92 and >90SPECfp92 (exact figures The R4600 family brings a high-level of integration are system-dependent). designed for high-performance computing. The key ele- The R4600 provides complete upward application-soft- ments of the R4600 are briefly described below. A more ware compatibility with the IDT79R3000 family of micro- detailed description of each of these subsystems is avail- processors, including the IDT RISController 79R3051 / able in the User’s Manual. R3052 /R3041 /R3071 /R3081 as well as the IDT79R4000 family of microprocessors. Microsoft Windows Pipeline NT and UNISOFT Unix V.4 operating systems insure the The R4600 uses a 5-stage pipeline similar to the availability of thousands of applications programs, geared IDT79R3000. The simplicity of this pipeline allows the to provide a complete solution to a large number of pro- R4600 to be lower cost and lower power than super-scalar cessing needs. An array of development tools facilitates or super-pipelined processors. Unlike the R3000, the the rapid development of R4600-based systems, enabling R4600 does virtual-to-physical translation in parallel with a wide variety of customers to take advantage of the MIPS cache access. This allows the R4600 to operate at twice Open Architecture philosophy. the frequency of the R3000 and to support a larger TLB for Together with the R4000 family, the R4600 provides a address translation. compatible, timely, and necessary evolution path from 32- Compared to the 8-stage R4000 pipeline, the R4600 is bit to true, 64-bit computing. The original design objectives more efficient (requires fewer stalls). of the R4000 clearly mandated this evolution path; the Figure 2 shows the R4600 pipeline. result is a true 64-bit processor fully compatible with 32-bit Figure 1. CPU Registers General Purpose Registers 63 0 Multiply/Divide Registers 0 63 0 r1 HIGH r2 63 0 • LOW • • Program Counter • 63 0 r29 PC r30 r31 5.7 2 IDT79R4600 COMMERCIAL TEMPERATURE RANGE Figure 2. R4600 Pipeline I0 1I 2I 1R 2R 1A 2A 1D 2D 1W 2W I1 1I 2I 1R 2R 1A 2A 1D 2D 1W 2W I2 1I 2I 1R 2R 1A 2A 1D 2D 1W ••• I3 1I 2I 1R 2R 1A 2A 1D ••• I4 1I 2I 1R 2R 1A ••• one cycle 1I-1R Instruction cache access 2I Instruction virtual to physical address translation in ITLB 2A-2D Data cache access and load align 1D Data virtual to physical address translation in DTLB 1D-2D Virtual to physical address translation in JTLB 2R Register file read 2R Bypass calculation 2R Instruction decode 2R Branch address calculation 1A Issue or slip decision 1A-2A Integer add, logical, shift 1A Data virtual address calculation 2A Store align 1A Branch decision 2W Register file write Integer Execution Engine point registers, and a floating-point control/status register. The R4600 implements the MIPS Instruction Set archi- tecture, and thus is fully upward compatible with applica- Register File tions running on the earlier generation parts. The R4600 The R4600 has thirty-two general-purpose registers. includes the same additions to the instruction set as found These registers are used for scalar integer operations and in the R4000 family of microprocessors, targeted at improv- address calculation. The register file consists of two read ing performance and capability while maintaining binary ports and one write port, and is fully bypassed to minimize compatibility with earlier processors. The extensions result operation latency in the pipeline. in better code density, greater multi-processing support, improved performance for commonly used code ALU sequences in operating system kernels, and faster execu- The R4600 ALU consists of the integer adder and logic tion of floating-point intensive applications. All resource unit. The adder performs address calculations in addition to dependencies are made transparent to the programmer, arithmetic operations, and the logic unit performs all logical insuring transportability among implementations of the and shift operations. Each of these units is highly optimized MIPS instruction set architecture. and can perform an operation in a single pipeline cycle. In addition to the instruction extensions detailed above, new instructions have been defined to take advantage of Integer Multiply/Divide the 64-bit architecture of the processor. When operating as The R4600 uses the floating-point unit to perform integer a 32-bit processor, the R4600 will take an exception on multiply and divide. The results of the operation are placed these new instructions. in the HIGH and LOW registers. The values can then be The MIPS integer unit implements a load/store architec- transferred to the general purpose register file using the ture with single cycle ALU operations (logical, shift, add, MFHI/MFLO instructions. Table 1 below shows the number sub) and autonomous multiply/divide unit. The register of processor internal cycles required between an integer resources include: 32 general-purpose orthogonal integer multiply or divide and a subsequent MFHI or MFLO opera- registers, the HIGH/LOW result registers for the integer tion, in order that no interlock or stall occurs. multiply/divide unit, and the program counter. In addition, the on-chip floating-point co-processor adds 32 floating- 5.7 3 IDT79R4600 COMMERCIAL TEMPERATURE RANGE Table 2: Floating-Point Cycles Table 1: Integer multiply/divide cycles Single Double Operation Precision Precision 32-bit 64-bit MOV 1 1 MULT 10 12 NEG 1 1 DIV 42 74 LWC1, LDC1 2 2 Floating-Point Co-Processor SWC1, SDC1 1 1 The R4600 incorporates an entire floating-point co-pro- cessor on chip, including a floating-point register file and execution units. The floating-point co-processor forms a “seamless” interface with the integer unit, decoding and Floating-Point General Register File executing instructions in parallel with the integer unit.
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