MIPS R4000 Microprocessor User’s Manual Second Edition Joe Heinrich 1994 MIPS Technologies, Inc. All Rights Reserved. RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure of the technical data contained in this document by the Government is subject to restrictions as set forth in subdivision (c) (1) (ii) of the Rights in Technical Data and Computer Software clause at DFARS 52.227-7013 and/or in similar or successor clauses in the FAR, or in the DOD or NASA FAR Supplement. Unpublished rights reserved under the Copyright Laws of the United States. Contractor/manufacturer is MIPS Technologies, Inc., 2011 N. Shoreline Blvd., Mountain View, CA 94039-7311. RISCompiler, RISC/os, R2000, R6000, R4000, and R4400 are trademarks of MIPS Technologies, Inc. MIPS and R3000 are registered trademarks of MIPS Technologies, Inc. IBM 370 is a registered trademark of International Business Machines. VAX is a registered trademark of Digital Equipment Corporation. iAPX is a registered trademark of Intel Corporation. MC68000 is a registered trademark of Motorola Inc. UNIX is a registered trademark in the United States and other countries, licensed exclusively through X/Open Company, Ltd. MIPS Technologies, Inc. 2011 North Shoreline Mountain View, California 94039-7311 Acknowledgments for the First Edition First of all, special thanks go to Duk Chun for his patient help in supplying and verifying the content of this manual; that this manual is technically correct is, in a very large part, directly attributable to him. Thanks also to the following people for supplying portions of this book: Shabbir Latif, for, among other things, the exception handler flow charts, the description of the output buffer edge-control logic, and the interrupts; once again, Duk Chun, for his paper on R4000 processor synchronization support; Paul Ries, for confirming the accuracy of sections describing the memory management and the caches; John Mashey, for verifying the R4000 processor actually does employ the 64-bit architecture; Dave Ditzel, for raising the issue in the first place; and Mike Gupta, for substantiating various aspects of the errata. Finally, thanks to Ed Reidenbach for supplying a large portion of the parity and ECC sections of this manual, and Michael Ngo for checking their accuracy. Thanks also to the following folks for their technical assistance: Andy Keane, Keith Garrett, Viggy Mokkarala, Charles Price, Ali Moayedian, George Hsieh, Peter Fu, Stephen Przybylski, Michael Woodacre, and Earl Killian. Also to be thanked are the people at [email protected]: Bill Tuthill, Barry Shein, Bob Devine, and Alan Marr, for helping place RISC in a pecuniary perspective. Also, thanks to the following people at the mystery_train@swim2birds news group: toma, dan_sears, jharris@garnet, tut@cairo (again), and elvis@dalkey(mateo_b). Their night- for-day netversations, fueled by caffeine, concerning the viability of the cyberpsykinetic compute-core model helped form an important basis of this book. On the editorial front, thanks once again to Ms. Robin Cowan, of the Consortium of Editorial Arts for her labors in editing this manual. Thanks to Evelyn Spire for slaving over that bottomless black well we refer to as an “Index.” Thanks also, once again, to Karen Gettman, and Lisa Iarkowski at Prentice-Hall for their help. On the artistic side, thanks to Jeanne Simonian, of the Creative department here at Silicon Graphics, for the book cover design; and thanks to Pam Flanders for providing MarCom tactical support. Have we missed anyone? If so, here is where we apologize for doing so. Joe Heinrich April 1, 1993 Mt. View, California MIPS R4000 Microprocessor User's Manual iii MIPS R4000 Microprocessor User's Manual iv Acknowledgments for the Second Edition Thanks go to Shabbir Latif, from whose errata the major part of this second edition is derived. Thanks also to Charlie Price for, among other things, making available his revision of the ISA. On the production side, thanks to Kay Maitz, Beth Fraker, Molly Castor, Lynnea Humphries, and Claudia Lohnes for their assistance at the center of the hurricane. Joe Heinrich [email protected] April 1, 1994 Mt. View, California MIPS R4000 Microprocessor User's Manual v MIPS R4000 Microprocessor User's Manual vi Preface This book describes the MIPS R4000 and R4400 family of RISC microprocessors (also referred to in this book as processor). Overview of the Contents Chapter 1 is a discussion (including the historical context) of RISC development in general, and the R4000 microprocessor in particular. Chapter 2 is an overview of the CPU instruction set. Chapter 3 describes the operation of the R4000 instruction execution pipeline, including the basic operation of the pipeline and interruptions that are caused by interlocks and exceptions. Chapter 4 describes the memory management system including address mapping and address spaces, virtual memory, the translation lookaside buffer (TLB), and the System Control Processor (CP0). Chapter 5 describes the exception processing resources of R4000 processor. It includes an overview of the CPU exception handling process and describes the format and use of each CPU exception handling register. MIPS R4000 Microprocessor User's Manual vii Preface Chapter 6 describes the Floating-Point Unit (FPU), a coprocessor for the CPU that extends the CPU instruction set to perform floating- point arithmetic operations. This chapter lists the FPU registers and instructions. Chapter 7 describes the FPU exception processing. Chapter 8 describes the signals that pass between the R4000 processor and other components in a system. The signals discussed include the System interface, the Clock/Control interface, the Secondary Cache interface, the Interrupt interface, the Initialization interface, and the JTAG interface. Chapter 9 describes in more detail the Initialization interface, which includes the boot modes for the processor, as well as system resets. Chapter 10 describes the clocks used in the R4000 processor, as well as the processor status reporting mechanism. Chapter 11 discusses cache memory, including the operation of the primary and secondary caches, and cache coherency in a multiprocessor system. Chapter 12 describes the System interface, which allows the processor access to external resources such as memory and input/output (I/O). It also allows an external agent access to the internal resources of the processor, such as the secondary cache. Chapter 13 describes the Secondary Cache interface, including read and write cycle timing. This chapter also discusses the interface buses and signals. Chapter 14 describes the Joint Test Action Group (JTAG) interface. The JTAG boundary scan mechanism tests the interconnections between the R4000 processor, the printed circuit board to which it is mounted, and other components on the board. Chapter 15 describes the single nonmaskable processor interrupt, along with the six hardware and two software processor interrupts. Chapter 16 describes the error checking and correcting (ECC) mechanisms of the R4000 processor. viii MIPS R4000 Microprocessor User's Manual Preface Appendix A describes the R4000 CPU instructions, in both 32- and 64- bit modes. The instruction list is given in alphabetical order. Appendix B describes the R4000 FPU instructions, listed alphabetically. Appendix C describes sub-block ordering, a nonsequential method of retrieving data. Appendix D describes the output buffer and the ∆i/∆t control mechanism. Appendix E describes the passive components that make up the phase-locked loop (PLL). Appendix F describes Coprocessor 0 hazards. Appendix G describes the R4000 pinout. A Note on Style A brief note on some of the stylistic conventions used in this book: bits, fields, and registers of interest from a software perspective are italicized (such as Config register); signal names of more importance from a hardware point of view are rendered in bold (such as Reset*). A range of bits uses a colon as a separator; for instance, (15:0) represents the 16-bit range that runs from bit 0, inclusive, through bit 15. (In some places an ellipsis may used in place of the colon for visibility: (15...0).) MIPS R4000 Microprocessor User's Manual ix Preface x MIPS R4000 Microprocessor User's Manual Preface to the Second Edition Changes From the First Edition The second edition of this book incorporates certain low-level changes and technical additions, but retains a substantive identity with the original version. Changes from the first edition are indicated by left-margin vertical rules. Getting MIPS Documents On-Line MIPS documents (including an electronic version of the errata) are available on-line, through the file transport protocol (FTP). To retrieve them, follow the steps below. The text you are to type is shown in Courier Bold font; the computer’s responses are in shown in Courier Regular font. 1. First, place yourself in the directory on your system within which you want to store the retrieved files. Do this by typing: cd <directory_you_want_file_to_be_in> 2. Access the MIPS document server, sgigate, through FTP by typing: ftp sgigate.sgi.com 3. The server tells you when you are connected for FTP by responding: Connected to sgigate.sgi.com. MIPS R4000 Microprocessor User's Manual xi Preface 4. Next (after some announcements) the server asks you to log in by requesting a name and then a password. Name (sgigate.sgi.com:<login_name>): 5. Login by typing anonymous for your name and your electronic mail address for your password. Name (sgigate.sgi.com:<login_name>): anonymous 331 Guest login ok, type your name as password. Password: your_email_address 6. The system indicates you have successfully logged in by supplying an FTP prompt: ftp> 7. Go to the pub/doc directory by typing: ftp> cd pub/doc 8. You can take a look at the contents of the doc directory by listing them: ftp> ls 9. You will find several R4000-related subdirectories, such as R4200, R4400, and R4600. When you find the subdirectory you want, cd into that subdirectory and retrieve the file you want by typing: get <filename> This copies the file from sgigate back to your system.