DOCSLIB.ORG

MIPS SDE 6.X Programmers' Guide

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
MIPS SDE 6.X Programmers' Guide TECHNOLOGIES MIPS® SDE 6.x Programmers’ Guide Document Number: MD00428 Revision 1.17 April 4, 2007 MIPS Technologies, Inc 1225 Charleston Road Mountain View,CA94043-1353 Copyright © 1995-2007 MIPS Technologies, Inc. All rights reserved. Copyright © 1995-2007 MIPS Technologies, Inc. All rights reserved. Unpublished rights (if any) reserved under the copyright laws of the United States of America and other countries. This document contains information that is proprietary to MIPS Technologies, Inc. (‘‘MIPS Technologies’’). Any copying, reproducing, modifying or use of this information (in whole or in part) that is not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly prohibited. At a minimum, this information is protected under unfair competition and copyright laws. Violations thereof may result in criminal penalties and fines. Anydocument provided in source format (i.e., in a modifiable form such as in FrameMaker or Microsoft Word format) is subject to use and distribution restrictions that are independent of and supplemental to anyand all confidentiality restrictions. UNDER NO CIRCUMSTANCES MAYADOCUMENT PROVIDED IN SOURCE FORMATBEDISTRIBUTED TOATHIRD PARTY IN SOURCE FORMATWITHOUT THE EXPRESS WRITTEN PERMISSION OF MIPS TECHNOLOGIES, INC. MIPS Technologies reserves the right to change the information contained in this document to improve function, design or otherwise. MIPS Technologies does not assume anyliability arising out of the application or use of this information, or of anyerror or omission in such information. Anywarranties, whether express, statutory,implied or otherwise, including but not limited to the implied warranties of merchantability or fitness for a particular purpose, are excluded. Except as expressly provided in anywritten license agreement from MIPS Technologies or an authorized third party,the furnishing of this document does not give recipient anylicense to anyintellectual property rights, including anypatent rights, that coverthe information in this document. The information contained in this document shall not be exported, reexported, transferred, or released, directly or indirectly,inviolation of the lawofany country or international law, regulation, treaty,Executive Order,statute, amendments or supplements thereto. Should a conflict arise regarding the export, reexport, transfer,orrelease of the information contained in this document, the laws of the United States of America shall be the governing law. The information contained in this document constitutes one or more of the following: commercial computer software, commercial computer software documentation or other commercial items. If the user of this information, or anyrelated documentation of anykind, including related technical data or manuals, is an agency, department, or other entity of the United States government (‘‘Government’’), the use, duplication, reproduction, release, modification, disclosure, or transfer of this information, or anyrelated documentation of anykind, is restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of this information by the Government is further restricted in accordance with the terms of the license agreement(s) and/or applicable contract terms and conditions covering this information from MIPS Technologies or an authorized third party. MIPS, MIPS I, MIPS II, MIPS III, MIPS IV,MIPS V,MIPS−3D, MIPS16, MIPS16e, MIPS32, MIPS64, MIPS−Based, MIPSsim, MIPSpro, MIPS Technologies logo, MIPS RISC CERTIFIED POWER logo, MIPS−VERIFIED, 4K, 4Kc, 4Km, 4Kp, 4KE, 4KEc, 4KEm, 4KEp, 4KS, 4KSc, 4KSd, M4K, 5K, 5Kc, 5Kf, 20K, 20Kc, 24K, 24Kc, 24Kf, 24KE, 24KEc, 24KEf, 25Kf, 34K, 34Kc, 34Kf, R3000, R4000, R5000, ASMACRO, Atlas, ‘‘At the core of the user experience.’’,BusBridge, CorExtend, CoreFPGA, CoreLV, EC, JALGO, Malta, MDMX, MGB, PDtrace, the Pipeline, Pro Series, QuickMIPS, SEAD, SEAD−2, SmartMIPS, SOC−it, and YAMON are trademarks or registered trademarks of MIPS Technologies, Inc. in the United States and other countries. All other trademarks referred to herein are the property of their respective owners. Template: B1.15, Built with tags: 2B MIPS32/MIPS64 SUM 2 MIPS® SDE 6.x Programmers’ Guide, Revision 1.17 Copyright © 1995-2007 MIPS Technologies, Inc. All rights reserved. Open Source Copyright Notices Manyofthe utilities contained in this package are derivedfrom Free Software Foundation code, which require this notice: This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 1, or (at your option) any later version. This program is distributed in the hope that it will be useful, butWITHOUT ANY WARRANTY;without eventhe implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. Youshould have receivedacopyofthe GNU General Public License along with this program; if not, write to the Free Software Foundation, 675 Mass Ave,Cambridge, MA 02139, USA. See also http://www.fsf.org/licenses/licenses.html. The Windows version of MIPS® SDE is built using the Cygwin programming environment, produced by RedHat/Cygnus at http://www.cygwin.com, and is distributed under the terms of the GNU General Public License and Cygwin API license, see http://cygwin.com/licensing.html. Some of the target libraries contain modules which require this acknowledgement: This product includes software developed by the University of California, Berkeleyand its contributors. UNIX is a registered trademark in the United States and other countries, licensed exclusively through X/Open CompanyLtd. X/Open is a trademark of X/Open CompanyLtd. POSIX is a registered trademark of the Institute of Electrical and Electronics Engineers, Inc. ThreadX® is a registered trademark of Express Logic, Inc. Formore details on howthese copyrights affect the code that you develop using MIPS® SDE, see Appendix A ‘‘Copyrights’’. MIPS® SDE 6.x Programmers’ Guide, Revision 1.17 3 Copyright © 1995-2007 MIPS Technologies, Inc. All rights reserved. Table of Contents Chapter 1 Introduction ..................................................................................................................................................12 What’sinMIPS® SDE 6.x.........................................................................................................................12 The MIPS® SDE lite subset .......................................................................................................................12 Getting working fast ..................................................................................................................................12 Other reading.............................................................................................................................................13 Other toolchain documentation .................................................................................................................13 Chapter 2 SDE on UNIX and Windows ........................................................................................................................14 2.1 SDE on Windows and ‘‘Cygwin’’...................................................................................................................14 2.1.1 File pathnames in Windows with Cygwin ...........................................................................................14 2.1.2 Textand binary files in Cygwin ...........................................................................................................15 2.2 Environment variables .....................................................................................................................................15 Chapter 3 Installation ....................................................................................................................................................17 3.1 Minimum System Requirements.....................................................................................................................17 3.2 Environment Variable Setup............................................................................................................................17 3.3 Installation.......................................................................................................................................................17 What’sinthe internet download? ............................................................................................................17 Where should you install your package? ................................................................................................18 Install MIPSsim™ simulator and probes .................................................................................................18 Remove old SDE.....................................................................................................................................18 Windows: Install Cygwin........................................................................................................................19 Install SDE ..............................................................................................................................................21 3.4 Multi-User Installation....................................................................................................................................22
Load more

Recommended publications
  • Wind River Vxworks Platforms 3.8
    Wind River VxWorks Platforms 3.8 The market for secure, intelligent, Table of Contents Build System ................................ 24 connected devices is constantly expand- Command-Line Project Platforms Available in ing. Embedded devices are becoming and Build System .......................... 24 VxWorks Edition .................................2 more complex to meet market demands. Workbench Debugger .................. 24 New in VxWorks Platforms 3.8 ............2 Internet connectivity allows new levels of VxWorks Simulator ....................... 24 remote management but also calls for VxWorks Platforms Features ...............3 Workbench VxWorks Source increased levels of security. VxWorks Real-Time Operating Build Configuration ...................... 25 System ...........................................3 More powerful processors are being VxWorks 6.x Kernel Compatibility .............................3 considered to drive intelligence and Configurator ................................. 25 higher functionality into devices. Because State-of-the-Art Memory Host Shell ..................................... 25 Protection ..................................3 real-time and performance requirements Kernel Shell .................................. 25 are nonnegotiable, manufacturers are VxBus Framework ......................4 Run-Time Analysis Tools ............... 26 cautious about incorporating new Core Dump File Generation technologies into proven systems. To and Analysis ...............................4 System Viewer ........................
    [Show full text]
  • Vxworks Architecture Supplement, 6.2
    VxWorks Architecture Supplement VxWorks® ARCHITECTURE SUPPLEMENT 6.2 Copyright © 2005 Wind River Systems, Inc. All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means without the prior written permission of Wind River Systems, Inc. Wind River, the Wind River logo, Tornado, and VxWorks are registered trademarks of Wind River Systems, Inc. Any third-party trademarks referenced are the property of their respective owners. For further information regarding Wind River trademarks, please see: http://www.windriver.com/company/terms/trademark.html This product may include software licensed to Wind River by third parties. Relevant notices (if any) are provided in your product installation at the following location: installDir/product_name/3rd_party_licensor_notice.pdf. Wind River may refer to third-party documentation by listing publications or providing links to third-party Web sites for informational purposes. Wind River accepts no responsibility for the information provided in such third-party documentation. Corporate Headquarters Wind River Systems, Inc. 500 Wind River Way Alameda, CA 94501-1153 U.S.A. toll free (U.S.): (800) 545-WIND telephone: (510) 748-4100 facsimile: (510) 749-2010 For additional contact information, please visit the Wind River URL: http://www.windriver.com For information on how to contact Customer Support, please visit the following URL: http://www.windriver.com/support VxWorks Architecture Supplement, 6.2 11 Oct 05 Part #: DOC-15660-ND-00 Contents 1 Introduction
    [Show full text]
  • VAX MACRO and Instruction Set Reference Manual
    VAX MACRO and Instruction Set Reference Manual Order Number: AA-LA89A-TE April 1988 This document describes the features of the VAX MACRO instruction set and assembler. It includes a detailed description of MACRO directives and instructions, as well as information about MACRO source program syntax. Revision/Update Information: This manual supersedes the VAX MACRO and Instruction Set Reference Manual, Version 4.0. Software Version: VMS Version 5.0 digital equipment corporation maynard, massachusetts April 1988 The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document. The software described in this document is furnished under a license and may be used or copied only in accordance with the terms of such license. No responsibility is assumed for the use or reliability of software on equipment that is not supplied by Digital Equipment Corporation or its affiliated companies. Copyright © 1988 by Digital Equipment Corporation All Rights Reserved. Printed in U.S.A. The postpaid READER'S COMMENTS form on the last page of this document requests the user's critical evaluation to assist in preparing future documentation. The following are trademarks of Digital Equipment Corporation: DEC DIBOL UNIBUS DEC/CMS EduSystem VAX DEC/MMS IAS VAXcluster DECnet MASSBUS VMS DECsystem-10 PDP VT DECSYSTEM-20 PDT DECUS RSTS DECwriter RSX t:JD~DD5lD TM ZK4515 HOW TO ORDER ADDITIONAL DOCUMENTATION DIRECT MAIL ORDERS USA 8t PUERTO Rico* CANADA INTERNATIONAL Digital Equipment Corporation Digital Equipment Digital Equipment Corporation P.O.
    [Show full text]
  • MIPS IV Instruction Set
    MIPS IV Instruction Set Revision 3.2 September, 1995 Charles Price MIPS Technologies, Inc. All Right Reserved RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure of the technical data contained in this document by the Government is subject to restrictions as set forth in subdivision (c) (1) (ii) of the Rights in Technical Data and Computer Software clause at DFARS 52.227-7013 and / or in similar or successor clauses in the FAR, or in the DOD or NASA FAR Supplement. Unpublished rights reserved under the Copyright Laws of the United States. Contractor / manufacturer is MIPS Technologies, Inc., 2011 N. Shoreline Blvd., Mountain View, CA 94039-7311. R2000, R3000, R6000, R4000, R4400, R4200, R8000, R4300 and R10000 are trademarks of MIPS Technologies, Inc. MIPS and R3000 are registered trademarks of MIPS Technologies, Inc. The information in this document is preliminary and subject to change without notice. MIPS Technologies, Inc. (MTI) reserves the right to change any portion of the product described herein to improve function or design. MTI does not assume liability arising out of the application or use of any product or circuit described herein. Information on MIPS products is available electronically: (a) Through the World Wide Web. Point your WWW client to: http://www.mips.com (b) Through ftp from the internet site “sgigate.sgi.com”. Login as “ftp” or “anonymous” and then cd to the directory “pub/doc”. (c) Through an automated FAX service: Inside the USA toll free: (800) 446-6477 (800-IGO-MIPS) Outside the USA: (415) 688-4321 (call from a FAX machine) MIPS Technologies, Inc.
    [Show full text]
  • Multi-Method Dispatch Using Single-Receiver Projections
    Multi-Method Dispatch Using Single-Receiver Projections Wade Holst Duane Szafron Candy Pang Yuri Leontiev g fwade,duane,candy,yuri @cs.ualberta.ca Department of Computing Science University of Alberta Edmonton, Canada Abstract A new technique for multi-method dispatch, called Single-Receiver Projections and abbre- viated SRP, is presented. It operates by performing projections onto single-receiver dispatch tables, and thus benefits from existing research into single-receiver dispatch techniques. It pro- k vides method dispatch in O(k ), where is the arity of the method. Unlike existing multi-method dispatch techniques, it also maintains the set of all applicable methods. This extra information allows SRP to support languages like CLOS that use next-method. SRP is also highly incremen- tal in nature, so it is well-suited for languages that require separate compilation and languages that allow methods and classes to be added at run-time. SRP uses less data-structure memory than all existing multi-method techniques and has the second fastest dispatch time. Furthermore, if the other techniques are extended to support all applicable methods, SRP becomes the fastest dispatch techniques. RESEARCH PAPER Subject Areas: language design and implementation, programming environments Keywords: multi-method, dispatch, object-oriented, implementation, compiler Word Count: 8722 Contact Author: Duane Szafron Department of Computing Science University of Alberta Edmonton, Canada, T6G 2H1 Phone: (780) 492-5468 Fax: (780) 492-1071 Email: [email protected] 1 1 Introduction In object-oriented languages, the method to invoke is determined not only by the method (selector) name, but also by the dynamic types of its arguments.
    [Show full text]
  • Using Virtualization to Implement a Scalable Trusted Execution Environment in Secure Socs
    Using Virtualization to Implement a Scalable Trusted Execution Environment in Secure SoCs Document Number: MD00993 Revision 01.00 December 3, 2012 Unpublished rights (if any) reserved under the copyright laws of the United States of America and other countries. This document contains information that is proprietary to MIPS Tech, LLC, a Wave Computing company (“MIPS”) and MIPS’ affiliates as applicable. Any copying, reproducing, modifying or use of this information (in whole or in part) that is not expressly permitted in writing by MIPS or MIPS’ affiliates as applicable or an authorized third party is strictly prohibited. At a minimum, this information is protected under unfair competition and copyright laws. Violations thereof may result in criminal penalties and fines. Any document provided in source format (i.e., in a modifiable form such as in FrameMaker or Microsoft Word format) is subject to use and distribution restrictions that are independent of and supplemental to any and all confidentiality restrictions. UNDER NO CIRCUMSTANCES MAY A DOCUMENT PROVIDED IN SOURCE FORMAT BE DISTRIBUTED TO A THIRD PARTY IN SOURCE FORMAT WITHOUT THE EXPRESS WRITTEN PERMISSION OF MIPS (AND MIPS’ AFFILIATES AS APPLICABLE) reserve the right to change the information contained in this document to improve function, design or otherwise. MIPS and MIPS’ affiliates do not assume any liability arising out of the application or use of this information, or of any error or omission in such information. Any warranties, whether express, statutory, implied or otherwise, including but not limited to the implied warranties of merchantability or fitness for a particular purpose, are excluded. Except as expressly provided in any written license agreement from MIPS or an authorized third party, the furnishing of this document does not give recipient any license to any intellectual property rights, including any patent rights, that cover the information in this document.
    [Show full text]
  • RISC-V Geneology
    RISC-V Geneology Tony Chen David A. Patterson Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2016-6 http://www.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-6.html January 24, 2016 Copyright © 2016, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Introduction RISC-V is an open instruction set designed along RISC principles developed originally at UC Berkeley1 and is now set to become an open industry standard under the governance of the RISC-V Foundation (www.riscv.org). Since the instruction set architecture (ISA) is unrestricted, organizations can share implementations as well as open source compilers and operating systems. Designed for use in custom systems on a chip, RISC-V consists of a base set of instructions called RV32I along with optional extensions for multiply and divide (RV32M), atomic operations (RV32A), single-precision floating point (RV32F), and double-precision floating point (RV32D). The base and these four extensions are collectively called RV32G. This report discusses the historical precedents of RV32G. We look at 18 prior instruction set architectures, chosen primarily from earlier UC Berkeley RISC architectures and major proprietary RISC instruction sets. Among the 122 instructions in RV32G: ● 6 instructions do not have precedents among the selected instruction sets, ● 98 instructions of the 116 with precedents appear in at least three different instruction sets.
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • Wind River General Purpose Platform Vxworks® Edition PRODUCT NOTE
    Wind River General Purpose Platform VxWorks® Edition PRODUCT NOTE Wind River General Purpose Platform, VxWorks Edition (version The real-time operating system: 3.0) unifi es a robust real-time operating system, a powerful ® Integrated Development Environment (IDE), fl exible middleware VxWorks 6.0 solutions, training to jump-start your development, and VxWorks is the most established and most widely deployed device Professional Services when you need them to extend your software operating system. Its performance, scalability, and capabilities. footprint make more than 300 million devices worldwide run faster s 02 and more reliably. fy 05 WIND RIVER GENERAL PURPOSE PLATFORM 3.0, The next generation of VxWorks adds powerful new features and VXWORKS EDITION COMPONENTS: a focus on openness, performance, reliability and interoperability. VxWorks 6.0 A new release of Wind River’s industry-leading real-time With VxWorks 6.0 companies can: operating system. • Optimize developer productivity through open standards Wind River Workbench 2.2 • Increase reliability through MMU-based memory protection A new release of Wind River’s fully integrated IDE. • Accelerate time-to-market through enhanced error management Middleware • Seamlessly migrate existing VxWorks-based IP and other Powerful capabilities to support fl ash fi le systems, distributed existing IP, including open source message passing and shared backplane memory. • Continue to deliver products that rely on the core attributes of VxWorks, including high performance, reliability, determinism, low latency and scalability IDE Complementary solution elements include an integrated development environment (Wind River Workbench), broad middleware availability, broad processor and Board Support Package (BSP) availability, Wind River Services support, legions of experienced VxWorks developers and an expansive ecosystem Middleware Distributed Messaging* of tools, hardware, middleware and application providers.
    [Show full text]
  • Low-Power High Performance Computing
    Low-Power High Performance Computing Panagiotis Kritikakos August 16, 2011 MSc in High Performance Computing The University of Edinburgh Year of Presentation: 2011 Abstract The emerging development of computer systems to be used for HPC require a change in the architecture for processors. New design approaches and technologies need to be embraced by the HPC community for making a case for new approaches in system design for making it possible to be used for Exascale Supercomputers within the next two decades, as well as to reduce the CO2 emissions of supercomputers and scientific clusters, leading to greener computing. Power is listed as one of the most important issues and constraint for future Exascale systems. In this project we build a hybrid cluster, investigating, measuring and evaluating the performance of low-power CPUs, such as Intel Atom and ARM (Marvell 88F6281) against commodity Intel Xeon CPU that can be found within standard HPC and data-center clusters. Three main factors are considered: computational performance and efficiency, power efficiency and porting effort. Contents 1 Introduction 1 1.1 Report organisation . 2 2 Background 3 2.1 RISC versus CISC . 3 2.2 HPC Architectures . 4 2.2.1 System architectures . 4 2.2.2 Memory architectures . 5 2.3 Power issues in modern HPC systems . 9 2.4 Energy and application efficiency . 10 3 Literature review 12 3.1 Green500 . 12 3.2 Supercomputing in Small Spaces (SSS) . 12 3.3 The AppleTV Cluster . 13 3.4 Sony Playstation 3 Cluster . 13 3.5 Microsoft XBox Cluster . 14 3.6 IBM BlueGene/Q .
    [Show full text]
  • Proaptiv: Efficient Performance on a Fully-Synthesizable Core
    proAptiv: Efficient Performance on a Fully-Synthesizable Core 28 August 2012 Ranganathan “Suds” Sudhakar Chief Architect 1 © 2012 MIPS Technologies, Inc. All rights reserved. Aptiv Family Highlights Three new cores optimized for embedded markets 2 © 2012 MIPS Technologies, Inc. All rights reserved. Aptiv Core Portfolio Classic MIPS Products Aptiv™ Generation Family Single-Threaded 1 to 6 core configs, Area Optimized Hi-speed FPU and MP version L2 cache controller 1074K Series 74K Series Out of Order Dual issue Family Multi-Threaded MP version Power Optimized 1 to 4 core configs, 1004K 2-level MT/FPU and Series L2 cache controller 34K Series 24K/24KE Multi-threading Series 9-stage pipeline 8-stage pipeline Family DSP-Accelerated M14K/c MCU (cacheless) or Energy Optimized M4K/4KE Series Series MPU (caches/TLBs) with real-time/security Code compression 4 stage pipeline 5 stage pipeline 3 © 2012 MIPS Technologies, Inc. All rights reserved. What is a “Soft” Core? Fully synthesizable “package” . Design data • RTL • Configurator – MP/MT, FPU, Trace/Debug, cache/TLB/SPRAM/buffer sizes, bus widths . Physical design support • Reference floorplans, Synthesis + Place-and-Route scripts • DFT/Scan, Timing and Power Analysis scripts . Simulation models • Bus Functional Models and compliance checkers • Instruction accurate simulators, Cycle exact simulators . Verification collateral • Architectural Verification Test suites, core diagnostics • Sample testbench, build and run scripts . Documentation • ISA manuals, global configuration register tables, memory maps, boot procedures • Implementer’s Guide, Integrator’s Guide, Hardware/Software User manuals Available separately . FPGA development boards . EJTAG/debug probes . OS components, libraries, software toolchains (compiler, libraries, JITs, codecs) 4 © 2012 MIPS Technologies, Inc.
    [Show full text]
  • MIPS® Architecture for Programmers Volume II-A: the MIPS64® Instruction
    MIPS® Architecture For Programmers Volume II-A: The MIPS64® Instruction Set Document Number: MD00087 Revision 5.04 December 11, 2013 Unpublished rights (if any) reserved under the copyright laws of the United States of America and other countries. This document contains information that is proprietary to MIPS Tech, LLC, a Wave Computing company (“MIPS”) and MIPS’ affiliates as applicable. Any copying, reproducing, modifying or use of this information (in whole or in part) that is not expressly permitted in writing by MIPS or MIPS’ affiliates as applicable or an authorized third party is strictly prohibited. At a minimum, this information is protected under unfair competition and copyright laws. Violations thereof may result in criminal penalties and fines. Any document provided in source format (i.e., in a modifiable form such as in FrameMaker or Microsoft Word format) is subject to use and distribution restrictions that are independent of and supplemental to any and all confidentiality restrictions. UNDER NO CIRCUMSTANCES MAY A DOCUMENT PROVIDED IN SOURCE FORMAT BE DISTRIBUTED TO A THIRD PARTY IN SOURCE FORMAT WITHOUT THE EXPRESS WRITTEN PERMISSION OF MIPS (AND MIPS’ AFFILIATES AS APPLICABLE) reserve the right to change the information contained in this document to improve function, design or otherwise. MIPS and MIPS’ affiliates do not assume any liability arising out of the application or use of this information, or of any error or omission in such information. Any warranties, whether express, statutory, implied or otherwise, including but not limited to the implied warranties of merchantability or fitness for a particular purpose, are excluded. Except as expressly provided in any written license agreement from MIPS or an authorized third party, the furnishing of this document does not give recipient any license to any intellectual property rights, including any patent rights, that cover the information in this document.
    [Show full text]