Introduction to
PlayStation®2 Architecture
James Russell Software Engineer
SCEE Technology Group In this presentation
ä Company overview ä PlayStation 2 architecture overview ä PS2 Game Development ä Differences between PS2 and PC.
Technology Group 1) Sony Computer Entertainment Overview
SCE Europe (includes Aus, NZ, Mid East, America Technology Group Japan Southern Africa) Sales
ä 40 million sold world-wide since launch ä Since March 2000 in Japan ä Since Nov 2000 in Europe/US ä New markets: Middle East, India, Korea, China ä Long term aim: 100 million within 5 years of launch ä Production facilities can produce 2M/month.
Technology Group Design considerations
ä Over 5 years, we’ll make 100,000,000 PS2s
ä Design is very important ä Must be inexpensive (or should become that way) ä Technology must be ahead of the curve
ä Need high performance, low price.
Technology Group How to achieve this?
ä Processor yield ä High CPU clock speed means lower yields
ä Solution? ä Low CPU clock speed, but high parallelism
ä Nothing readily available ä SCE designs custom chips.
Technology Group 2) Technical Aspects of PlayStation 2
ä 128-bit CPU core “Emotion Engine” ä + 2 independent Vector Units ä + Image Processing Unit (for MPEG) ä GS - “Graphics Synthesizer” GPU ä SPU2 - Sound Processing Unit ä I/O Processor (CD/DVD, USB, i.Link).
Technology Group “Emotion Engine” - Specifications
ä CPU Core 128 bit CPU ä System Clock 300MHz ä Bus Bandwidth 3.2GB/sec ä Main Memory 32MB (Direct Rambus) ä Floating Point Calculation 6.2 GFLOPS ä 3D Geometry Performance 66 Million polygons/sec.
Technology Group System Architecture
VIDEO RAM Emotion Graphic OUT Engine Synthesiser (EE) (GS)
RAM I/O Sound AUDIO OUT Processor Processor EXTERNAL DEVICES (IOP) (SPU2)
ROM CD/DVD
Technology Group Emotion Engine architecture Overview
FPU COP1 VU0 VU1 CPU GIF GS Core COP2 EFU INTC
128bit Main Bus
Timer DMAC IPU DRAMC SIF
DRAM IOP Technology Group Emotion Engine architecture CPU Core
ä 128 bit CPU FPU COP1 äVU0300 MHz clockVU1 frequency CPU GIF GS Core ä MIPS instruction set COP2 EFU INTC ä 64 bit instructions, 2-way superscalar 128bit ä 128 bit multimedia instructionsMain Bus
Timer DMAC IPU DRAMC SIF
DRAM IOP Technology Group Emotion Engine architecture CPU Core
FPU COP1 VU0 VU1 CPU GIF GS Core COP2 EFU INTC
128bit Main Bus
Timer DMAC IPU DRAMC SIF
DRAM IOP Technology Group Emotion Engine architecture CPU Core
ä 16Kb I-Cache FPU COP1 äVU08Kb D-CacheVU1 CPU GIF GS Core ä 16Kb scratchpad COP2 EFU INTC
128bit Main Bus
Timer DMAC IPU DRAMC SIF
DRAM IOP Technology Group Emotion Engine architecture Floating Point Unit (FPU)
FPU COP1 VU0 VU1 CPU GIF GS Core COP2 EFU INTC
128bit Main Single FPU for the CPU core Bus
Timer DMAC IPU DRAMC SIF
DRAM IOP Technology Group Emotion Engine architecture DMA Controller (DMAC)
FPU COP1 VU0 VU1 CPU GIF GS Core COP2 EFU INTCä Moves data from memory to devices
ä Essential to maximising EE performance128bit Main Bus
Timer DMAC IPU DRAMC SIF
DRAM IOP Technology Group Emotion Engine architecture Vector Processing Units (VU0 & VU1)
FPU COP1 VU0 VU1 CPU GIF GS Core COP2 EFU INTC
128bit ä Used for mathematical operations Main Bus ä FMACs for addition and multiplication ä FDIVTimer for divisionDMAC and squareIPU rootDRAMC operationsSIF ä Built-in memory for microprograms
DRAM IOP Technology Group Emotion Engine architecture Vector Unit 0 (VU0)
FPU COP1 VU0 VU1 CPU GIF GS Core COP2 EFU INTC
128bit ä 4 FMACs, 1 FDIV Main Bus ä Connected to the CPU, executing macroinstructions ä 4 KBTimer VUMemDMAC(data), 4 IPUKB MicroMemDRAMC(instructions)SIF ä Usually used for animation and physics.
DRAM IOP Technology Group Emotion Engine architecture Vector Unit 0 (VU0)
FPU COP1 VU0 VU1 CPU GIF GS Core COP2 EFU INTC
128bit Main Bus ä The VU0 is a 128 bit SIMD/VLIW design. ä ATimer SIMD processorDMAC operatesIPU DRAMC on vectorsSIF of data. As an example, when a SIMD instruction adds 64 bit numbers, the 64 data streams are sent to 64 ALUs to perform 64 sums in a single clock cycle DRAM IOP Technology Group Emotion Engine architecture Vector Unit 1 (VU1)
FPU COP1 VU0 VU1 CPU GIF GS Core COP2 EFU INTC
128bit ä No direct path to CPU core, but direct path to GIFMain Bus ä 16 Kb VUMem (data), 16 Kb MicroMem (instructions) ä UsedTimer for geometryDMAC transformationsIPU DRAMC SIF
DRAM IOP Technology Group Emotion Engine architecture Vector Unit 1 (VU1)
FPU COP1 VU0 VU1 CPU GIF GS Core COP2 EFU INTC ä VU1 ishas architecturally 16K instruction identical memory to and VU0, data but has128bit Main somememory additional while VU0 features has only that 8K/8k are ofrelated memory. toBus the factThis larger that VU1 amount acts asis because a geometry VU1 processor is a geometry for theprocessorTimer GS. One andDMAC of thereforethese IPUfeatures is requiredDRAMC is the toEFU, SIFhandle which is composedmuch more of data 1 FMAC than andVU0 1 FDIV unit, and it is used to perform more basic calculations for
geometry processing No directDRAM path to CPUIOP core, Technology butGroup direct path to GIF Emotion Engine architecture Image Processing Unit (IPU)
FPU COP1 VU0 VU1 CPU GIF GS Core COP2 EFU äINTCImage data decompression processor
ä Decodes MPEG2 streams 128bit Main Bus
Timer DMAC IPU DRAMC SIF
DRAM IOP Technology Group System Architecture
VIDEO RAM Emotion Graphic OUT Engine Synthesiser (EE) (GS)
RAM I/O Sound AUDIO OUT ä Clock FrequencyProcessor150 Mhz Processor EXTERNALä Embedded DRAM 4MB DEVICES (IOP) (SPU2) ä Total memory bandwidth 1.2Gb/sec ä Pixel fill rate 2.4GPixel/sec. ROM CD/DVD
Technology Group GS specifications
ä Clock Frequency 150 Mhz ä Embedded DRAM 4MB ä Total memory bandwidth 1.2Gb/sec ä Pixel fill rate 2.4GPixel/sec.
Technology Group System Architecture
VIDEO RAM Emotion Graphic OUT Engine Synthesiser (EE) (GS)
RAM I/O Sound AUDIO OUT Processor Processor EXTERNAL DEVICES (IOP) (SPU2)
ROM DiscCD/DVD Drive
Technology Group IOP (Input/Output Processor)
ä Contains an R3000 (PlayStation CPU+) ä Used for backwards compatibility ä 2 MB of RAM ä Handles all external devices ä Controllers ä USB ä SPU 2 ä CD/DVD unit ä IEEE1394 ä Hard disc, ethernet/modem. Technology Group System Architecture
VIDEO RAM Emotion Graphic OUT Engine Synthesiser (EE) (GS)
RAM I/O Sound AUDIO OUT Processor Processor EXTERNAL DEVICES (IOP) (SPU2)
ROM CD/DVD
Technology Group SPU 2
ä 48 Channels ä 2MB sound memory ä Output to DAC or Optical digital output (Dolby 5.1) ä Realtime DTS 5.1 is possible.
Technology Group Coming Soon..
ä Broadband Adaptor ä HDD interface & 100/10 Ethernet port ä Ethernet allows access to broadband (via ADSL/CATV/Satellite/etc) ä HDD used by game for local storage, or downloadable content.
Technology Group 3) Game Development
ä Programming a game on the PS2.
Technology Group PS2 Development Environment The TOOL
ä TOOL = PlayStation 2 with TV more RAM, and network Controllers
ä A separate Linux/Windows box runs the compilers and debuggers ä Connects over the network to LAN the TOOL.
PC ä Use Linux-based tools (provided), or 3rd-party Windows development tools Technology Group Console programming
ä Halfway between embedded system and PC. ä Small & basic OS ä Large amount of control
ä Low level coding ä No drivers ä Standard hardware means you can optimise for the system ä Performance analysis has benefit.
Technology Group Differences between PS2 and PC
ä Uses parallelism ä Information should ‘stream’ through the system ä But not all algorithms are parallelisable ä Random memory access hits hard ä Data must be reorganised so that related parts sit together ä Optimisation is easier on PS2 ä Standard hardware means optimisation works on all machines.
Technology Group Basic Rendering Pipeline
+-*/ Calculate CPU + coprocessor VU0 animation
Traverse List processing DMA scene
+-*/ Transform to 2D VU1
Rasterisation GS
Technology Group 1st Attempt At A PC Port (max 0.5 million polys)
IOP SPU IPU
Memory DMA bus: 2.4Gb/sec Geometry and texture
FPU CPU VU0 VU1 GS
Transformation
Technology Group 2nd Attempt At A PC Port (max 1.5 million polys)
IOP SPU IPU
Memory DMA bus: 2.4Gb/sec Geometry and texture
FPU CPU VU0 VU1 GS
Transformation in parallel with CPU Technology Group Complete Game (lighting, animation) (typical 5-10 million polys)
IOP SPU IPU
Memory DMA bus: 2.4Gb/sec
Geometry Texture
FPU CPU VU0 VU1 GS
Transformation
Technology Group How To Improve PS2 Performance
ä By not treating the PS2 as a PC ä Think parallel – think ‘assembly line’ ä Code for small Instruction and Data Cache
Technology Group Summary
ä PS2 is a state-of-the-art machine
ä Achieves high performance and low cost through high parallelism
ä But it requires a different way of programming
ä Question Time!
Technology Group