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IDT MIPS Microprocessor Family Software Reference Manual

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IDT MIPS Microprocessor Family Software Reference Manual Integrated Device Technology, Inc. IDT MIPS Microprocessor Family Software Reference Manual Version 2.0 October 1996 2975 Stender Way, Santa Clara, California 95054 Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674 Printed in U.S.A. ©1996 Integrated Device Technology, Inc. Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry de- scribed herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc. LIFE SUPPORT POLICY Integrated Device Technology's products are not authorized for use as critical components in life sup- port devices or systems unless a specific written agreement pertaining to such intended use is exe- cuted between the manufacturer and an officer of IDT. 1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in ac- cordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The IDT logo is a registered trademark, and BiCameral, BurstRAM, BUSMUX, CacheRAM, DECnet, Double-Density, FASTX, Four-Port, FLEXI-CACHE, Flexi-PAK, Flow-thruEDC, IDT/c, IDTenvY, IDT/sae, IDT/sim, IDT/ux, MacStation, MICROSLICE, PalatteDAC, REAL8, R3041, R3051, R3052, R3071, R3081, R36100, R3721, R4600, R4640, R4650, R4700, R4761, R4762, R5000, RISController, RISCore, RISC Subsystem, RISC Windows, SARAM, SmartLogic, SyncFIFO, SyncBiFIFO, SPC, TargetSystem and WideBus are trademarks of Inte- grated Device Technology, Inc. MIPS is a registered trademark, and RISCompiler, RISComponent, RISComputer, RISCware, RISC/os, R3000, and R3010 are trademarks of MIPS Computer Systems, Inc. Postscript is a registered trademark of Adobe Systems, Inc. AppleTalk, LocalTalk, and Macintosh are registered trademarks of Apple Computer, Inc. Centronics is a registered trademark of Genicom, Inc. Ethernet is a registered trademark of Digital Equipment Corp. PS2 is a registered trademark of IBM Corp. About This Manual About This Manual Integrated Device Technology, Inc. This manual provides an introduction and design overview as well as more detailed descriptions and instructions for the following IDT product families: • IDT79R30xx family of 32-bit RISC controllers • IDT79R4xxx ORION family of high-performance 64-bit CPUs • IDT79R5000 family of MIPS-4 ISA compatible CPU devices Summary of Contents Chapter 1, “Introduction,” presents an overview of IDT’s micropro- cessor families, including a discussion of the CPU Pipeline, and a compar- ison of MIPS ISA and CISC architecture. Chapter 2, “MIPS Architecture,” discusses the high-level architec- ture from the programmer’s point of view, including comparisons of the basic address space of the R30xx, R4600/4700, and R4650. Chapter 3, “System Control Co-Processor Architecture,” discusses the aspects of the MIPS architecture that must be managed by the oper- ating system, including details about CPU Control and Co-Processor 0. Chapter 4, “Exception Management,” examines the software tech- niques used to manage exceptions, and includes several code examples. Chapter 5, “Cache Management,” discusses IDT’s implementation of the on-chip caches for instructions (I-cache) and data (D-cache). Chapter 6, “Memory Management,” discusses memory management and the Translation Lookaside Buffer (TLB). Also included is a discussion of the R4650’s simple base-bounds mechanism, which it uses instead of a TLB. Chapter 7, “Reset Initialization,” reviews the CPU reset, compares it to an exception, and includes information on bootstrap sequences and starting up an application. Chapter 8, “Floating Point Co-Processor,” describes the operation of floating points, and compares the implementations in the various IDT MIPS microprocessors. Chapter 9, “Assembler Language Programming,” discusses the tech- niques and conventions of reading and writing MIPS assembler code, including a complete table of assembler instructions. Chapter 10, “C Programming,” provides an overview of the principles of designing an efficient C run-time environment, including a discussion of optimization. Chapter 11, “Portability Considerations,” discusses the main facets of designing for portability. Chapter 12, “Writing Power-On Diagnostics,” provides a pragmatic, hands-on look at producing usable diagnostics in the MIPS environment. Chapter 13, “Instruction Timing and Optimization,” discusses the scheduling implications in using MIPS instructions, and includes infor- mation about additional hazards. iii About This Manual About This Manual Chapter 14, “Software Tools for Board Bring-Up,” describes the soft- ware tools typically used by IDT when debugging a new board. Chapter 15, “Software Design Examples,” contains examples of C programs for applications and embedded systems. Chapter 16, “Assembly Language Programming Tips,” contains tips on optimizing your programming in a MIPS environment. Appendix A, “CPU Instruction Set,” provides an overview of the CPU instruction set. Following the overview, in alphabetical order, are command pages describing the individual CPU instructions. Appendix B, “FPU Instruction Set,” provides an overview of the floating point instruction set. Following the overview, in alphabetical order, are command pages describing the individual floating point instructions. iv Table of Contents List of Tables Integrated Device Technology, Inc. INTRODUCTION CHAPTER 1 OVERVIEW 1-1 IDT’s MICROPROCESSOR FAMILIES 1-1 CPU PIPELINE 1-3 32-bit vs. 64-bit CPUs 1-4 MIPS ARCHITECTURE LEVELS 1-4 MIPS ISA COMPARED WITH CISC ARCHITECTURES 1-5 Instruction encoding features 1-5 Addressing and memory accesses 1-6 Operations not directly supported 1-7 Multiply and divide operations 1-7 Programmer-visible pipeline effects 1-7 A NOTE ON MACHINE AND ASSEMBLER LANGUAGE 1-9 MIPS ARCHITECTURE CHAPTER 2 PROGRAMMER’S VIEW OF THE PROCESSOR ARCHITECTURE 2-1 Registers 2-1 Conventional names and uses of general-purpose registers 2-2 Integer multiply unit and registers 2-4 Instruction types 2-5 Loading and storing: addressing modes 2-6 Data types in memory and registers 2-6 BASIC ADDRESS SPACE OF R30xx 2-10 SUMMARY OF R30xx SYSTEM ADDRESSING 2-11 Kernel vs. user mode 2-11 Memory map for CPUs without MMU hardware 2-12 R36100 Address Translation 2-14 BASIC ADDRESS SPACE OF R4600/R4700 2-15 BASIC ADDRESS SPACE OF R4650 2-18 SYSTEM CONTROL CO-PROCESSOR ARCHITECTURE CHAPTER 3 CPU CONTROL SUMMARY 3-1 CPU CONTROL AND “CO-PROCESSOR 0” 3-3 CPU control instructions 3-3 Standard CPU control registers 3-3 Control Register Formats 3-4 Processor-specific registers 3-12 CPO Registers and System Operation Support 3-23 EXCEPTION MANAGEMENT CHAPTER 4 EXCEPTIONS 4-1 Precise Exceptions 4-1 Exception Timing 4-2 Exception Vectors 4-2 Exception Handling – Basics 4-3 Nesting Exceptions 4-4 Exception Routines 4-5 v Table of Contents Table of Contents INTERRUPTS 4-16 Software Interrupts 4-16 CACHE MANAGEMENT CHAPTER 5 CACHES AND CACHE MANAGEMENT 5-1 R30xx cache characteristics 5-2 Cache locking 5-3 Cache isolation and swapping in R30xx 5-4 R4600/R4700/R4650/R5000 Cache Characteristics 5-5 Initializing and Sizing the Caches 5-7 Initializing R30xx cache 5-11 Initializing R4xxx cache 5-12 Invalidation 5-14 Locking set A of R4650 caches 5-16 Testing and probing 5-17 Configuration (R3041/71/81 only) 5-17 WRITE BUFFER 5-18 Implementing wbflush() 5-19 MEMORY MANAGEMENT CHAPTER 6 MEMORY MANAGEMENT AND THE TRANSLATION LOOKASIDE BUFFER (TLB) 6-1 MEMORY MANAGEMENT AND BASE-BOUNDS 6-3 MMU REGISTERS 6-3 Description of MMU Registers 6-4 TLB CONTROL INSTRUCTIONS 6-13 PROGRAMMING TO THE TLB 6-13 How refills occur 6-13 Memory translation – setup 6-14 TLB exception sample code 6-15 Simulating dirty bits 6-16 USE OF TLB IN DEBUGGING 6-17 TLB MANAGEMENT UTILITIES 6-17 RESET INITIALIZATION CHAPTER 7 STARTING UP 7-1 Probing and recognizing the CPU 7-9 Bootstrap sequences 7-9 Starting up an application 7-10 FLOATING POINT CO-PROCESSOR CHAPTER 8 WHAT IS FLOATING POINT? 8-1 THE IEEE 754 STANDARD AND ITS BACKGROUND 8-2 IEEE exponent field and bias 8-3 IEEE mantissa and normalization 8-3 Reserved Exponent Values 8-3 MIPS FP Data formats 8-4 MIPS IMPLEMENTATION OF IEEE 754 8-5 FLOATING POINT REGISTERS (R30xx) 8-5 FLOATING POINT REGISTERS (R4xxx/R5000) 8-5 FLOATING POINT EXCEPTIONS/INTERRUPTS 8-6 THE FLOATING POINT CONTROL/STATUS REGISTER 8-6 FLOATING-POINT IMPLEMENTATION/REVISION REGISTER 8-8 vi Table of Contents Table of Contents GUIDE TO FP INSTRUCTIONS 8-9 Load/store 8-9 Move between registers 8-10 3-operand arithmetic operations 8-10 4-operand arithmetic operations 8-11 Unary (sign-changing) operations 8-11 Conversion operations 8-11 Conditional branch and test instructions 8-12 Other floating point instructions 8-13 INSTRUCTION TIMING REQUIREMENTS 8-13 INSTRUCTION TIMING FOR
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