DOCSLIB.ORG

The Mc68020 32-Bit Microprocessor by Paul F

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
The Mc68020 32-Bit Microprocessor by Paul F NEW C HIPS THE MC68020 32-BIT MICROPROCESSOR BY PAUL F. GROEPLER AND JAMES KENNEDY The latest member of Motorola's 68000 family includes on-board cache and virtual memory THE MC68020, the newest addition to the chip managers. They control inter- ate control for the micromachine. the Motorola M68000 family of micro- nal buses, registers, and the execution The instruction prefetch and decode processors, is a full 32-bit processor unit. unit fetches and decodes an instruc- with separate 32-bit data and address The execution unit contains the pro- tion for execution by the execution buses, an on-board instruction cache, gram counter (PC), the address, and unit. The prefetch is a three-word- dynamic bus sizing, and a coproces- the data . The PC section calculates in- deep on-chip instruction store. It elim- sor interface. It is object-code com- struction addresses and manages inates the need for the processor to patible with the earlier members of pointers. The address section calcu- sequentially fetch an instruction from the M68000 family but has new ad- lates operand addresses and stores external memory, decode and ex- dressing modes in support of high- the registers available to the user. The ecute it, and fetch another. level languages. data section performs all data opera- Instead, because of the sequential The MC68020 is an HCMOS (high- tions, such as immediate data value nature of instruction accesses, the speed complementary metal-oxide moves . It also contains the barrel prefetch can anticipate the next ac- semiconductor) microprocessor with shifter, which performs one-cycle cess and make it before it is needed. some 200,000 individual transistors shifts of any amount on data. Thus, external memory fetches are an- on a 375- by 350-millimeter die, The bus controller manages cache ticipated and overlapped with current operating at a 16 . 67-MHz clock fre- and external memory accesses. It also processor execution. quency (60-nanosecond clock period) provides control for the various parts The instruction addresses for the and dissipating less than 1 . 5 watts of of the 68020 microprocessor and in- prefetch are calculated independently power. It can process instructions at terprets the nanorom information. of data addresses, allowing for par- a sustained rate of 2 to 3 million in- This information is combined with de- allel accesses of instruction and data structions per second ( MIPS) and at coding the instruction pipe to gener- addresses. This simultaneous access burst rates exceeding 8 MIPS. ....................................... will occur if the data access is from Paul F. Groepler is a systems applications external memory and the instruction MC68020 PARTS designer in the High-end Applications Engi- access is from the instruction cache. Figure I is a block diagram of the neering Department at Motorola. James When this happens, a simultaneous MC68020 with the various internal Kennedy is a software engineer in the MPU instruction and data access occurs. sections labeled. We'll briefly describe Design Department at Motorola. You can The 256-byte instruction cache in- their functions. reach them at Motorola Inc ., POB 6000, creases performance by reducing the The sequencer and control unit are Austin, TX 78762. (continued) NOVEMBER 1984 • BYTE 159 Circle 58 on inquiry card. WHY THE MC68020 JOHNNY CAN'T number of instruction fetches, or bus register is used only for the clear en- cycles, from main memory. This lets try (CE) function in conjunction with READ system performance increase because the CACR. the processor's bus use is decreased, HIS freeing the bus for other system bus DYNAMIC B us SIZING masters. Only instructions are stored A nice feature of the MC68020 for the in the cache. Data accesses must still designer as well as the programmer OWN be read from main memory. is the dynamic bus. Now a designer Hardware and software may control need not worry about excessive hard- the cache. Hardware control is in the ware "glue" to interface to 16- or 8-bit CODE form of the cache disable (CDIS pin), peripherals and a programmer need which can disable the cache. The not worry about word or long-word Johnny's CDIS pin has priority and overrides aligned data in data space. The A Good any software setting. MC68020 allows transfers of 8-, 16-, Programmer, Software control is in the form of and 32-bit data between 8-, 16-, and two control registers: the cache con- 32-bit ports. The only requirement for Even Brilliant, trol register (CACR) and the cache ad- data alignment is that it occur on a But-Johnny works in 8080/Z80 assembly dress register (CAAR). The CACR and byte boundary. Instructions and any language, with a conventional assembler. CAAR are organized as shown in fig- associated extension words must still That can make yesterday's brilliance ures 2 and 3. Bits 4 to 31 are unused fall on word address boundaries, but today's garble, a maze of mnemonics and a jumble of meaningless labels. Johnny's and always read as zeros. The CACR word/long-word alignment is no program is less than self-explanatory- lets the systems programmer enable longer required for program space even for Johnny. or freeze the cache, clear an entry, or operands. Johnny could read his own code if he used clear the entire cache. The CAAR is The processor lets misaligned trans- SMAL/80-the superassembler-and so can you. SMAL/80 boosts your program's a 32-bit register that provides an ad- fers occur by determining the data clarity and your productivity by giving you: dress for cache control functions. This (continued) n Familiar algebraic notation in place of cryptic mnemonics-"A=A-3" for example, instead of "SUI 3" (if you know BASIC or SEQUENCER Pascal, you already know SMAL/80) n CONTROL Control structures like BEGIN... END, UNIT LOOP... REPEAT WHILE, and IF...THEN... INSTRUCTION ELSE... to replace tangled branches and PREFETCH AND arbitrary label names (eliminating up to 90% DECODE of labels with no overhead imposed) n Complete control over your processor- because SMAL/80 is a true assembler, it doesn't reduce execution speed or burden your program with its own runtime routines. SMAL/80, the assembler that handles like a high-level language , lets you do it right the first time, and lets you read and understand LER = BUS CONTROL your work afterward-the next day or a EXECUTION INSTRUCTION ADDRESS/ UNIT DATA BUS year later. Users say SMAL/80 has doubled BUS ^; CACHE and even tripled their output of quality code. 32 But don't take our word for it-TRY IT! 32 Use SMAL/80 for 30 days. If you're not completely satisfied with it-for any rea- Figure l: MC68020 block diagram. son-return the package for a full refund. SPECIAL BONUS : Order before Dec. 31, 1984, and get Structured Microprocessor 3 8 7 0 Programming-a $25 book FREE! C SMAL/80 for CP/M-80 systems (all CP/M C =CLEAR CACHE CE -CLEAR ENTRY disk formats available-please specify); F =FREEZE CACHE produces 8080/8085 and Z80 code. Now E =ENABLE CACHE supports Microsoft REL.ONLY $149.95 SMAL/80 for CP/M-80 systems, Figure 2: The cache control register. 8080/8085 output only. SAVE $20 : $129.95 NEW! SMAL /80X65-for Apple II and lie (requires Z80 card and CP/M); produces Z80 and 6502 object code. $ 169.95 s 7 2 I 0 CACHE FUNCTION ADDRESS INDEX Mastercard We pay Visa SMALshipping/80 on C.o. D.'s CHROMOD ASSOCIATES prepaid Figure 3 : The cache address register. (201) 653-7615 orders 1030 Park Ave. Hoboken, N.J. 07030 160 BYTE • NOVEMBER 1984 THE MC68020 port size during each bus cycle. By the misaligned data across the port only data bits Dal to D24 need to be handshaking lines between the pro- within one bus cycle. A normal trans- connected to the peripheral. Four bus cessor and external memory or pe- fer occurring from an aligned 32-bit cycles are necessary to complete this ripherals, the MC68020 can transfer operand address across a 32-bit bus transfer with only I byte being moved this mismatched or mis-sized data. to a 32-bit peripheral would take only across the bus per cycle. Figure 4 illustrates the workings of the one transfer cycle. The MC68020 relaxes word and internal hardware that makes this pos- In a mis-sized transfer, as well as a long-word alignment restrictions for sible and the alignment of operand normal transfer, the peripheral uses data. It is now possible to execute an bytes for an 8-, 16-, and 32-bit bus in- the DSACKO and DSACKI pins to sig- operand transfer across a memory terfacing with the MC68020. nal to the processor that it has a bus boundary that only needs to be byte Misaligned operand transfers can width of 8, 16, or 32 bits. The proces- aligned. Even and odd word restric- lead to an increased number of bus sor outputs the operand transfer size tions are gone. Some performance cycles because the processor might using the SIZO and SIZI pins. degradation can occur, due to extra not be able to successfully transfer Notice that with an 8-bit peripheral, bus cycles needed to transfer mis- aligned long-word or word data across MC68020 boundaries. OPO OP1 OP2 OP3 Figure 5 shows a misaligned long- INTERNAL SOURCE / DESTINATION word transfer across a word-wide bus. In the example, a byte box with "xxx" MULTIPLEXOR denotes that the location in memory is not overwritten and remains un- EXTERNAL DATA BUS changed. As you can see from this ex- ample, it is important for the system designer to control the enabling/dis- abling of the appropriate data buffers 32-BIT PORT to avoid overwriting or misreading 31 0 nonpertinent data during a mis- aligned cycle.
Load more

Recommended publications
  • Historical Perspective and Further Reading 162.E1
    2.21 Historical Perspective and Further Reading 162.e1 2.21 Historical Perspective and Further Reading Th is section surveys the history of in struction set architectures over time, and we give a short history of programming languages and compilers. ISAs include accumulator architectures, general-purpose register architectures, stack architectures, and a brief history of ARMv7 and the x86. We also review the controversial subjects of high-level-language computer architectures and reduced instruction set computer architectures. Th e history of programming languages includes Fortran, Lisp, Algol, C, Cobol, Pascal, Simula, Smalltalk, C+ + , and Java, and the history of compilers includes the key milestones and the pioneers who achieved them. Accumulator Architectures Hardware was precious in the earliest stored-program computers. Consequently, computer pioneers could not aff ord the number of registers found in today’s architectures. In fact, these architectures had a single register for arithmetic instructions. Since all operations would accumulate in one register, it was called the accumulator , and this style of instruction set is given the same name. For example, accumulator Archaic EDSAC in 1949 had a single accumulator. term for register. On-line Th e three-operand format of RISC-V suggests that a single register is at least two use of it as a synonym for registers shy of our needs. Having the accumulator as both a source operand and “register” is a fairly reliable indication that the user the destination of the operation fi lls part of the shortfall, but it still leaves us one has been around quite a operand short. Th at fi nal operand is found in memory.
    [Show full text]
  • Motorola 68000 Opcodes
    Motorola 68000 CPU Opcodes Mnemonic Size Single Effective Address Operation Word Data Mnemonic Size Single Effective Address Operation Word Data Addressing Mode Format M Xn ORI to CCR B 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 B I RTE 0 1 0 0 1 1 1 0 0 1 1 1 0 0 1 1 Data register Dn 0 0 0 reg ORI to SR W 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 W I RTS 0 1 0 0 1 1 1 0 0 1 1 1 0 1 0 1 Address register An 0 0 1 reg ORI B W L 0 0 0 0 0 0 0 0 S M Xn I TRAPV 0 1 0 0 1 1 1 0 0 1 1 1 0 1 1 0 Address (An) 0 1 0 reg ANDI to CCR B 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 B I RTR 0 1 0 0 1 1 1 0 0 1 1 1 0 1 1 1 Address with Postincrement (An)+ 0 1 1 reg ANDI to SR W 0 0 0 0 0 0 1 0 0 1 1 1 1 1 0 0 W I JSR 0 1 0 0 1 1 1 0 1 0 M Xn Address with Predecrement -(An) 1 0 0 reg ANDI B W L 0 0 0 0 0 0 1 0 S M Xn I JMP 0 1 0 0 1 1 1 0 1 1 M Xn Address with Displacement (d16, An) 1 0 1 reg SUBI B W L 0 0 0 0 0 1 0 0 S M Xn I MOVEM W L 0 1 0 0 1 D 0 0 1 S M Xn W M Address with Index (d8, An, Xn) 1 1 0 reg ADDI B W L 0 0 0 0 0 1 1 0 S M Xn I LEA L 0 1 0 0 An 1 1 1 M Xn Program Counter with Displacement (d16, PC) 1 1 1 0 1 0 EORI to CCR B 0 0 0 0 1 0 1 0 0 0 1 1 1 1 0 0 B I CHK W 0 1 0 0 Dn 1 1 0 M Xn Program Counter with Index (d8, PC, Xn) 1 1 1 0 1 1 EORI to SR W 0 0 0 0 1 0 1 0 0 1 1 1 1 1 0 0 W I ADDQ B W L 0 1 0 1 Data 0 S M Xn Absolute Short (xxx).W 1 1 1 0 0 0 EORI B W L 0 0 0 0 1 0 1 0 S M Xn I SUBQ B W L 0 1 0 1 Data 1 S M Xn Absolute Long (xxx).L 1 1 1 0 0 1 CMPI B W L 0 0 0 0 1 1 0 0 S M Xn I Scc B 0 1 0 1 Condition 1 1 M Xn Immediate #imm 1 1 1 1 0 0 BTST B L 0 0 0 0 1 0 0
    [Show full text]
  • Computer Architectures
    Computer Architectures Motorola 68000, 683xx a ColdFire – CISC CPU Principles Demonstrated Czech Technical University in Prague, Faculty of Electrical Engineering AE0B36APO Computer Architectures Ver.1.10 1 Original Desktop/Workstation 680X0 Feature 68000 'EC000 68010 68020 68030 68040 68060 Data bus 16 8/16 16 8/16/32 8/16/32 32 32 Addr bus 23 23 23 32 32 32 32 Misaligned Addr - - - Yes Yes Yes Yes Virtual memory - - Yes Yes Yes Yes Yes Instruct Cache - - 3 256 256 4096 8192 Data Cache - - - - 256 4096 8192 Memory manager 68451 or 68851 68851 Yes Yes Yes ATC entries - - - - 22 64/64 64/64 FPU interface - - - 68881 or 68882 Internal FPU built-in FPU - - - - - Yes Yes Burst Memory - - - - Yes Yes Yes Bus Cycle type asynchronous both synchronous Data Bus Sizing - - - Yes Yes use 68150 Power (watts) 1.2 0.13-0.26 0.13 1.75 2.6 4-6 3.9-4.9 at frequency of 8.0 8-16 8 16-25 16-50 25-40 50-66 MIPS/kDhryst. 1.2/2.1 2.5/4.3 6.5/11 14/23 35/60 100/300 Transistors 68k 84k 190k 273k 1,170k 2,500k Introduction 1979 1982 1984 1987 1991 1994 AE0B36APO Computer Architectures 2 M68xxx/CPU32/ColdFire – Basic Registers Set 31 16 15 8 7 0 User programming D0 D1 model registers D2 D3 DATA REGISTERS D4 D5 D6 D7 16 15 0 A0 A1 A2 A3 ADDRESS REGISTERS A4 A5 A6 16 15 0 A7 (USP) USER STACK POINTER 0 PC PROGRAM COUNTER 15 8 7 0 0 CCR CONDITION CODE REGISTER 31 16 15 0 A7# (SSP) SUPERVISOR STACK Supervisor/system POINTER 15 8 7 0 programing model (CCR) SR STATUS REGISTER 31 0 basic registers VBR VECTOR BASE REGISTER 31 3 2 0 SFC ALTERNATE FUNCTION DFC CODE REGISTERS AE0B36APO Computer Architectures 3 Status Register – Conditional Code Part USER BYTE SYSTEM BYTE (CONDITION CODE REGISTER) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T1 T0 S 0 0 I2 I1 I0 0 0 0 X N Z V C TRACE INTERRUPT EXTEND ENABLE PRIORITY MASK NEGATIVE SUPERVISOR/USER ZERO STATE OVERFLOW CARRY ● N – negative ..
    [Show full text]
  • RTEMS CPU Supplement Documentation Release 4.11.3 ©Copyright 2016, RTEMS Project (Built 15Th February 2018)
    RTEMS CPU Supplement Documentation Release 4.11.3 ©Copyright 2016, RTEMS Project (built 15th February 2018) CONTENTS I RTEMS CPU Architecture Supplement1 1 Preface 5 2 Port Specific Information7 2.1 CPU Model Dependent Features...........................8 2.1.1 CPU Model Name...............................8 2.1.2 Floating Point Unit..............................8 2.2 Multilibs........................................9 2.3 Calling Conventions.................................. 10 2.3.1 Calling Mechanism.............................. 10 2.3.2 Register Usage................................. 10 2.3.3 Parameter Passing............................... 10 2.3.4 User-Provided Routines............................ 10 2.4 Memory Model..................................... 11 2.4.1 Flat Memory Model.............................. 11 2.5 Interrupt Processing.................................. 12 2.5.1 Vectoring of an Interrupt Handler...................... 12 2.5.2 Interrupt Levels................................ 12 2.5.3 Disabling of Interrupts by RTEMS...................... 12 2.6 Default Fatal Error Processing............................. 14 2.7 Symmetric Multiprocessing.............................. 15 2.8 Thread-Local Storage................................. 16 2.9 CPU counter...................................... 17 2.10 Interrupt Profiling................................... 18 2.11 Board Support Packages................................ 19 2.11.1 System Reset................................. 19 3 ARM Specific Information 21 3.1 CPU Model Dependent Features..........................
    [Show full text]
  • Designing PCI Cards and Drivers for Power Macintosh Computers
    Designing PCI Cards and Drivers for Power Macintosh Computers Revised Edition Revised 3/26/99 Technical Publications © Apple Computer, Inc. 1999 Apple Computer, Inc. Adobe, Acrobat, and PostScript are Even though Apple has reviewed this © 1995, 1996 , 1999 Apple Computer, trademarks of Adobe Systems manual, APPLE MAKES NO Inc. All rights reserved. Incorporated or its subsidiaries and WARRANTY OR REPRESENTATION, EITHER EXPRESS OR IMPLIED, WITH No part of this publication may be may be registered in certain RESPECT TO THIS MANUAL, ITS reproduced, stored in a retrieval jurisdictions. QUALITY, ACCURACY, system, or transmitted, in any form America Online is a service mark of MERCHANTABILITY, OR FITNESS or by any means, mechanical, Quantum Computer Services, Inc. FOR A PARTICULAR PURPOSE. AS A electronic, photocopying, recording, Code Warrior is a trademark of RESULT, THIS MANUAL IS SOLD “AS or otherwise, without prior written Metrowerks. IS,” AND YOU, THE PURCHASER, ARE permission of Apple Computer, Inc., CompuServe is a registered ASSUMING THE ENTIRE RISK AS TO except to make a backup copy of any trademark of CompuServe, Inc. ITS QUALITY AND ACCURACY. documentation provided on Ethernet is a registered trademark of CD-ROM. IN NO EVENT WILL APPLE BE LIABLE Xerox Corporation. The Apple logo is a trademark of FOR DIRECT, INDIRECT, SPECIAL, FrameMaker is a registered Apple Computer, Inc. INCIDENTAL, OR CONSEQUENTIAL trademark of Frame Technology Use of the “keyboard” Apple logo DAMAGES RESULTING FROM ANY Corporation. (Option-Shift-K) for commercial DEFECT OR INACCURACY IN THIS purposes without the prior written Helvetica and Palatino are registered MANUAL, even if advised of the consent of Apple may constitute trademarks of Linotype-Hell AG possibility of such damages.
    [Show full text]
  • Computer Organization EECC 550 • Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Week 1 Notation (RTN)
    Computer Organization EECC 550 • Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Week 1 Notation (RTN). [Chapters 1, 2] • Instruction Set Architecture (ISA) Characteristics and Classifications: CISC Vs. RISC. [Chapter 2] Week 2 • MIPS: An Example RISC ISA. Syntax, Instruction Formats, Addressing Modes, Encoding & Examples. [Chapter 2] • Central Processor Unit (CPU) & Computer System Performance Measures. [Chapter 4] Week 3 • CPU Organization: Datapath & Control Unit Design. [Chapter 5] Week 4 – MIPS Single Cycle Datapath & Control Unit Design. – MIPS Multicycle Datapath and Finite State Machine Control Unit Design. Week 5 • Microprogrammed Control Unit Design. [Chapter 5] – Microprogramming Project Week 6 • Midterm Review and Midterm Exam Week 7 • CPU Pipelining. [Chapter 6] • The Memory Hierarchy: Cache Design & Performance. [Chapter 7] Week 8 • The Memory Hierarchy: Main & Virtual Memory. [Chapter 7] Week 9 • Input/Output Organization & System Performance Evaluation. [Chapter 8] Week 10 • Computer Arithmetic & ALU Design. [Chapter 3] If time permits. Week 11 • Final Exam. EECC550 - Shaaban #1 Lec # 1 Winter 2005 11-29-2005 Computing System History/Trends + Instruction Set Architecture (ISA) Fundamentals • Computing Element Choices: – Computing Element Programmability – Spatial vs. Temporal Computing – Main Processor Types/Applications • General Purpose Processor Generations • The Von Neumann Computer Model • CPU Organization (Design) • Recent Trends in Computer Design/performance • Hierarchy
    [Show full text]
  • Programmable Digital Microcircuits - a Survey with Examples of Use
    - 237 - PROGRAMMABLE DIGITAL MICROCIRCUITS - A SURVEY WITH EXAMPLES OF USE C. Verkerk CERN, Geneva, Switzerland 1. Introduction For most readers the title of these lecture notes will evoke microprocessors. The fixed instruction set microprocessors are however not the only programmable digital mi• crocircuits and, although a number of pages will be dedicated to them, the aim of these notes is also to draw attention to other useful microcircuits. A complete survey of programmable circuits would fill several books and a selection had therefore to be made. The choice has rather been to treat a variety of devices than to give an in- depth treatment of a particular circuit. The selected devices have all found useful ap• plications in high-energy physics, or hold promise for future use. The microprocessor is very young : just over eleven years. An advertisement, an• nouncing a new era of integrated electronics, and which appeared in the November 15, 1971 issue of Electronics News, is generally considered its birth-certificate. The adver• tisement was for the Intel 4004 and its three support chips. The history leading to this announcement merits to be recalled. Intel, then a very young company, was working on the design of a chip-set for a high-performance calculator, for and in collaboration with a Japanese firm, Busicom. One of the Intel engineers found the Busicom design of 9 different chips too complicated and tried to find a more general and programmable solu• tion. His design, the 4004 microprocessor, was finally adapted by Busicom, and after further négociation, Intel acquired marketing rights for its new invention.
    [Show full text]
  • I.T.S.O. Powerpc an Inside View
    SG24-4299-00 PowerPC An Inside View IBM SG24-4299-00 PowerPC An Inside View Take Note! Before using this information and the product it supports, be sure to read the general information under “Special Notices” on page xiii. First Edition (September 1995) This edition applies to the IBM PC PowerPC hardware and software products currently announced at the date of publication. Order publications through your IBM representative or the IBM branch office serving your locality. Publications are not stocked at the address given below. An ITSO Technical Bulletin Evaluation Form for reader′s feedback appears facing Chapter 1. If the form has been removed, comments may be addressed to: IBM Corporation, International Technical Support Organization Dept. JLPC Building 014 Internal Zip 5220 1000 NW 51st Street Boca Raton, Florida 33431-1328 When you send information to IBM, you grant IBM a non-exclusive right to use or distribute the information in any way it believes appropriate without incurring any obligation to you. Copyright International Business Machines Corporation 1995. All rights reserved. Note to U.S. Government Users — Documentation related to restricted rights — Use, duplication or disclosure is subject to restrictions set forth in GSA ADP Schedule Contract with IBM Corp. Abstract This document provides technical details on the PowerPC technology. It focuses on the features and advantages of the PowerPC Architecture and includes an historical overview of the development of the reduced instruction set computer (RISC) technology. It also describes in detail the IBM Power Series product family based on PowerPC technology, including IBM Personal Computer Power Series 830 and 850 and IBM ThinkPad Power Series 820 and 850.
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • 6809 the Design Philosophy by Terry Ritter and Joel Boney
    The 6809 ing the performance of an unwieldy bureaucratic Part 1: Design Philosophy organization. And the computer makers clearly thought that processor time was valuable too; or Terry Ritter was a severely limited resource, worth as much as Joel Boney the market would bear. Motorola, Inc. Processor time was a limited resource. But 3501 Ed Blustein Blvd. some of us, a few small groups of technologists, Austin, TX 78721 are about to change that situation. And we hope we will also change how people look at computers, This is a story. It is a story of computers in and how professionals see them too. Computer general, specifically microcomputers, and of one time should be cheap; people time is 70 years and particular microprocessor - with revolutionary counting down. social change lurking in the background. The story The large computer, being a very expensive could well be imaginary, but it happens to be true. resource, quickly justified the capital required to In this 3 part series we will describer the design of investigate optimum use of that resource. Among what we feel is the best 8 bit machine so far made the principal results of these projects was the by human: the Motorola M6809. development of batch mode multiprocessing. The computer itself would save up the various tasks it Philosophy had to do, then change from one to the other at computer speeds. This minimized the wasted time A new day is breaking; after a long slow twi- between jobs and spawned the concept of an oper- light of design the sun is beginning to rise on the ating system.
    [Show full text]
  • Euf-Snt-T1469
    Freescale Recommendations for Avionic and Defense Applications EUF-SNT-T1469 Pierre Juste | Senior Field Application Engineer M A Y . 2 0 1 5 TM External Use Session Introduction • Freescale processors have been widely utilized in Aerospace and Defense applications for many generations. • This two hour session will describe the most commonly selected devices from: − i.MX applications processors − 32-bit Qorivva microcontrollers built on Power Architecture® technology − QorIQ communications platforms • This presentation will provide examples of successful approaches used on Freescale products for improving robustness and safety and mitigating system failures in aeronautics and defense environments. • The session will also summarize the design documentation and resources available to support the certification process. TM External Use 1 Session Objectives After completing this session you will be able to: • Select processors from the Freescale portfolio targeting Aerospace and Defense applications. • Identify key functions associated with safety. • Locate essential documentation and collateral. • Explain the advantages of Freescale devices to support safety. • Describe the capabilities of the products that will help you meet your design challenges for Aerospace and Defense applications and how they can provide you a with a competitive and differentiating advantage. TM External Use 2 Agenda • Freescale experience in Aerospace and Defense applications • Key factors • Development Assurance Level (DAL), criticality & Freescale processors • Freescale
    [Show full text]
  • Lecture #3 PIC Microcontrollers
    Integrated Technical Education Cluster Banna - At AlAmeeria ‎ © Ahmad © Ahmad El E-626-A Real-Time Embedded Systems (RTES) Lecture #3 PIC Microcontrollers Instructor: 2015 SPRING Dr. Ahmad El-Banna Banna Agenda - What’s a Microcontroller? © Ahmad El Types of Microcontrollers Features and Internal structure of PIC 16F877A RTES, Lec#3 , Spring Lec#3 , 2015 RTES, Instruction Execution 2 Banna What is a microcontroller? - • A microcontroller (sometimes abbreviated µC, uC or MCU) is a small computer on a single integrated circuit © Ahmad El containing a processor core, memory, and programmable input/output peripherals. • It can only perform simple/specific tasks. • A microcontroller is often described as a ‘computer-on-a- chip’. RTES, Lec#3 , Spring Lec#3 , 2015 RTES, 3 Microcomputer system and Microcontroller Banna based system - © Ahmad © Ahmad El RTES, Lec#3 , Spring Lec#3 , 2015 RTES, 4 Banna Microcontrollers.. - • Microcontrollers are purchased ‘blank’ and then programmed with a specific control program. © Ahmad El • Once programmed the microcontroller is build into a product to make the product more intelligent and easier to use. • A designer will use a Microcontroller to: • Gather input from various sensors • Process this input into a set of actions • Use the output mechanisms on the microcontroller to do something useful. RTES, Lec#3 , Spring Lec#3 , 2015 RTES, 5 Banna Types of Microcontrollers - • Parallax Propeller • Freescale 68HC11 (8-bit) • Intel 8051 © Ahmad El • Silicon Laboratories Pipelined 8051 Microcontrollers • ARM processors (from many vendors) using ARM7 or Cortex-M3 cores are generally microcontrollers • STMicroelectronics STM8 (8-bit), ST10 (16-bit) and STM32 (32-bit) • Atmel AVR (8-bit), AVR32 (32-bit), and AT91SAM (32-bit) • Freescale ColdFire (32-bit) and S08 (8-bit) • Hitachi H8, Hitachi SuperH (32-bit) • Hyperstone E1/E2 (32-bit, First full integration of RISC and DSP on one processor core [1996]) • Infineon Microcontroller: 8, 16, 32 Bit microcontrollers for Spring Lec#3 , 2015 RTES, automotive and industrial applications.
    [Show full text]