NEW C HIPS
THE MC68020 32-BIT MICROPROCESSOR BY PAUL F. GROEPLER AND JAMES KENNEDY
The latest member of Motorola's 68000 family includes on-board cache and virtual memory
THE MC68020, the newest addition to the chip managers. They control inter- ate control for the micromachine. the Motorola M68000 family of micro- nal buses, registers, and the execution The instruction prefetch and decode processors, is a full 32-bit processor unit. unit fetches and decodes an instruc- with separate 32-bit data and address The execution unit contains the pro- tion for execution by the execution buses, an on-board instruction cache, gram counter (PC), the address, and unit. The prefetch is a three-word- dynamic bus sizing, and a coproces- the data . The PC section calculates in- deep on-chip instruction store. It elim- sor interface. It is object-code com- struction addresses and manages inates the need for the processor to patible with the earlier members of pointers. The address section calcu- sequentially fetch an instruction from the M68000 family but has new ad- lates operand addresses and stores external memory, decode and ex- dressing modes in support of high- the registers available to the user. The ecute it, and fetch another. level languages. data section performs all data opera- Instead, because of the sequential The MC68020 is an HCMOS (high- tions, such as immediate data value nature of instruction accesses, the speed complementary metal-oxide moves . It also contains the barrel prefetch can anticipate the next ac- semiconductor) microprocessor with shifter, which performs one-cycle cess and make it before it is needed. some 200,000 individual transistors shifts of any amount on data. Thus, external memory fetches are an- on a 375- by 350-millimeter die, The bus controller manages cache ticipated and overlapped with current operating at a 16 . 67-MHz clock fre- and external memory accesses. It also processor execution. quency (60-nanosecond clock period) provides control for the various parts The instruction addresses for the and dissipating less than 1 . 5 watts of of the 68020 microprocessor and in- prefetch are calculated independently power. It can process instructions at terprets the nanorom information. of data addresses, allowing for par- a sustained rate of 2 to 3 million in- This information is combined with de- allel accesses of instruction and data structions per second ( MIPS) and at coding the instruction pipe to gener- addresses. This simultaneous access burst rates exceeding 8 MIPS...... will occur if the data access is from Paul F. Groepler is a systems applications external memory and the instruction MC68020 PARTS designer in the High-end Applications Engi- access is from the instruction cache. Figure I is a block diagram of the neering Department at Motorola. James When this happens, a simultaneous MC68020 with the various internal Kennedy is a software engineer in the MPU instruction and data access occurs. sections labeled. We'll briefly describe Design Department at Motorola. You can The 256-byte instruction cache in- their functions. reach them at Motorola Inc ., POB 6000, creases performance by reducing the The sequencer and control unit are Austin, TX 78762. (continued)
NOVEMBER 1984 • BYTE 159 Circle 58 on inquiry card.
WHY THE MC68020 JOHNNY CAN'T number of instruction fetches, or bus register is used only for the clear en- cycles, from main memory. This lets try (CE) function in conjunction with READ system performance increase because the CACR. the processor's bus use is decreased, HIS freeing the bus for other system bus DYNAMIC B us SIZING masters. Only instructions are stored A nice feature of the MC68020 for the in the cache. Data accesses must still designer as well as the programmer OWN be read from main memory. is the dynamic bus. Now a designer Hardware and software may control need not worry about excessive hard- the cache. Hardware control is in the ware "glue" to interface to 16- or 8-bit CODE form of the cache disable (CDIS pin), peripherals and a programmer need which can disable the cache. The not worry about word or long-word Johnny's CDIS pin has priority and overrides aligned data in data space. The A Good any software setting. MC68020 allows transfers of 8-, 16-, Programmer, Software control is in the form of and 32-bit data between 8-, 16-, and two control registers: the cache con- 32-bit ports. The only requirement for Even Brilliant, trol register (CACR) and the cache ad- data alignment is that it occur on a But-Johnny works in 8080/Z80 assembly dress register (CAAR). The CACR and byte boundary. Instructions and any language, with a conventional assembler. CAAR are organized as shown in fig- associated extension words must still That can make yesterday's brilliance ures 2 and 3. Bits 4 to 31 are unused fall on word address boundaries, but today's garble, a maze of mnemonics and a jumble of meaningless labels. Johnny's and always read as zeros. The CACR word/long-word alignment is no program is less than self-explanatory- lets the systems programmer enable longer required for program space even for Johnny. or freeze the cache, clear an entry, or operands. Johnny could read his own code if he used clear the entire cache. The CAAR is The processor lets misaligned trans- SMAL/80-the superassembler-and so can you. SMAL/80 boosts your program's a 32-bit register that provides an ad- fers occur by determining the data clarity and your productivity by giving you: dress for cache control functions. This (continued) n Familiar algebraic notation in place of cryptic mnemonics-"A=A-3" for example, instead of "SUI 3" (if you know BASIC or SEQUENCER Pascal, you already know SMAL/80) n CONTROL Control structures like BEGIN... END, UNIT LOOP... REPEAT WHILE, and IF...THEN... INSTRUCTION ELSE... to replace tangled branches and PREFETCH AND arbitrary label names (eliminating up to 90% DECODE of labels with no overhead imposed) n Complete control over your processor- because SMAL/80 is a true assembler, it doesn't reduce execution speed or burden your program with its own runtime routines. SMAL/80, the assembler that handles like a high-level language , lets you do it right the first time, and lets you read and understand LER = BUS CONTROL your work afterward-the next day or a EXECUTION INSTRUCTION ADDRESS/ UNIT DATA BUS year later. Users say SMAL/80 has doubled BUS ^; CACHE and even tripled their output of quality code. 32 But don't take our word for it-TRY IT! 32 Use SMAL/80 for 30 days. If you're not completely satisfied with it-for any rea- Figure l: MC68020 block diagram. son-return the package for a full refund. SPECIAL BONUS : Order before Dec. 31, 1984, and get Structured Microprocessor 3 8 7 0 Programming-a $25 book FREE! C
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160 BYTE • NOVEMBER 1984 THE MC68020
port size during each bus cycle. By the misaligned data across the port only data bits Dal to D24 need to be handshaking lines between the pro- within one bus cycle. A normal trans- connected to the peripheral. Four bus cessor and external memory or pe- fer occurring from an aligned 32-bit cycles are necessary to complete this ripherals, the MC68020 can transfer operand address across a 32-bit bus transfer with only I byte being moved this mismatched or mis-sized data. to a 32-bit peripheral would take only across the bus per cycle. Figure 4 illustrates the workings of the one transfer cycle. The MC68020 relaxes word and internal hardware that makes this pos- In a mis-sized transfer, as well as a long-word alignment restrictions for sible and the alignment of operand normal transfer, the peripheral uses data. It is now possible to execute an bytes for an 8-, 16-, and 32-bit bus in- the DSACKO and DSACKI pins to sig- operand transfer across a memory terfacing with the MC68020. nal to the processor that it has a bus boundary that only needs to be byte Misaligned operand transfers can width of 8, 16, or 32 bits. The proces- aligned. Even and odd word restric- lead to an increased number of bus sor outputs the operand transfer size tions are gone. Some performance cycles because the processor might using the SIZO and SIZI pins. degradation can occur, due to extra not be able to successfully transfer Notice that with an 8-bit peripheral, bus cycles needed to transfer mis- aligned long-word or word data across MC68020 boundaries. OPO OP1 OP2 OP3 Figure 5 shows a misaligned long- INTERNAL SOURCE / DESTINATION word transfer across a word-wide bus. In the example, a byte box with "xxx"
MULTIPLEXOR denotes that the location in memory is not overwritten and remains un-
EXTERNAL DATA BUS changed. As you can see from this ex- ample, it is important for the system designer to control the enabling/dis- abling of the appropriate data buffers 32-BIT PORT to avoid overwriting or misreading 31 0 nonpertinent data during a mis- aligned cycle. For clarity's sake, figure 5 also shows BYTE 0 BYTE I 16-BIT PORT line A2 in offset of the transferred BYTE 2 BYTE 3 data into word memory. The first cycle 31 16 runs with A2/A1/A0 being 001, show-
BYTE 0 ing an offset of 1 byte in memory.
BYTE 1 SIZI/SIZO is 00, indicating that the 8-BIT PORT processor has a long word left to BYTE 2 transfer. The second cycle shows A2/ BYTE 3 Al/A0 with a 2-byte displacement, 31 24 and SIZI/SIZO showing the processor with 3 bytes left to transfer. The third Figure 4 : The MC68020 interface to various port sizes. cycle has no offset on the address pins and the SIZE pins indicating I
LONG -WORD OPERAND byte left to transfer. There is a two- OPO OPI OP2 OP3 bus-cycle degradation here, but it is 31 0 transparent to the programmer, let- ting him ignore the restrictions of data DATA BUS alignment.
031 D16 COPROCESSOR INTERFACE WORD MEMORY MC68020 MEMORY CONTROL Though the MC68020 is powerful, it
MSB LSB SIZI SIZO A2 Al AO DSACKI DSACKO might not have all the special com- mands or capabilities that a designer XXX OPO 0 0 0 0 1 L H requires. For this reason, the design- H Opi OP2 1 1 0 1 0 L ers of the MC68020 incorporated a OP3 xxx 0 1 1 0 0 L H general coprocessor interface and in- structions. The coprocessor interface Figure 5: Example of a misaligned long-word transfer to a word-wide bus. provides a means by which Motorola (continued)
162 BY TE • NOVEMBER 1984 THE MC68020
and other coprocessors (floating tion sequences that emulate the pro- The coprocessor identifier (Cp-ld) point, fast Fourier transform, or graph- tocol of the coprocessor interface. field identifies which coprocessor is ics processors) can extend the The coprocessor operates based on to be selected. The Type field iden- MC68020. an F-line operation code, essentially tifies which type of coprocessor oper- The coprocessor interface is de- the first word of a coprocessor in- ation is to be performed (branch, signed to support synchronous oper- struction. It is so named because the general, save, etc.). ation between the MC68020 and up hexadecimal F in the upper nybble of Communication between the main to eight coprocessors. With this inter- the instruction word causes the pro- processor and coprocessors is syn- face, downward compatibility is pos- cessor to flag the instruction during chronous, but the main processor sible because a coprocessor can be decode. The F-line indicates to the might not need to wait for the copro- coupled with a main processor other main processor that it must call the cessor to complete an instruction than the MC68020 (e.g., 68008, coprocessor for proper execution of before it begins execution of its next 68000, 68010, 68012). All the main the instruction. See figure 6 for the instruction. processor must do is provide instruc- format of the Pine word. Hardware connection is a simple ex- tension of the MC68000 bus interface 15 14l 1313 1212 1111 10 9 8 7 6 5 4 3 2 2 1 0 and is shown in figure 7. The copro- 31 I 1 1 co-IdCpId TYPE 7 TYPE DDEPENDENTEPE NDENT cessor is connected as a peripheral to the main processor and is selected Figure 6: F-line format. based on combinations of function codes (FC2-FCO are I11) and address bits (A19-A16 are 0010) as well as bits A15-13, described in figure 6.
OVERLAP
ADDRESS Overlap occurs when the sequencer COPROCESSOR I/O MEMORY DECODE and bus controller are operating on different instructions simultaneously. For example, in figure 8 a MOVE (An), (An) instruction and a SUB Dn,Dn in- FCO-FC2 struction can operate concurrently for some of the total execution time. The MC68020 BUS overlap takes place during the exter- AO-A31 EXTENSION nal bus activity associated with the ^uu MOVE. Since for a certain clock time DO-D31 5 the bus controller is busy performing the write to external memory asso- ciated with the MOVE, the sequencer Figure 7 : Coprocessor system configuration. can continue with the next instruction, subtract (SUB). The SUB instruction does not require any external bus ac- 1 2 3 4 5 6 7 8 9 tivity, so the sequencer alone can CLOCK operate on it. This overlap time is shown from clocks 4 through 6. Also note that part of the instruc- BUS ACTIVITY PREFETCH WRITE NEXT INSTRUCTION tion following the SUB might have some of its execution time overlapped under the MOVE instruction. This oc- PREFETCH PERFORM WRITE NEXT BUS CONTROLLER INSTRUCTION AFTER FOR MOVE INSTRUCTIO N curs if calculations, such as effective SUB address calculations, are needed to perform the instruction. An example SEQUENCER PERFORM MOVE PERFORM SUB NEXT INSTRUCTION of this would be if another MOVE in-
INSTRUCTION struction followed the SUB instruction. MOVE ( An), (An) NEXT INST UCTION EXECUTION TIME Because the bus controller was per- forming an external bus cycle asso- CLOCK COUNT (6) ciated with the MOVE during the time the SUB was taking place internally, Figure 8 : Overlap example. (continued)
164 BY TE • NOVEMBER 1984 THE MC68020
the execution time is attributed to the dividual instruction is dependent on seven 32-bit general addressing MOVE instruction alone. If the pipe the instruction previous to it and is registers, three 32-bit stack pointers had been depleted and the SUB in- subject to the rules built into the (user, master, and interrupt), a 32-bit struction had not been inside, the prefetch mechanism. The best timings program counter, a 16-bit status described overlap would not have that can be given are in terms of best, register, a 32-bit vector base register, taken place. average, and worst-case boundaries. two 3-bit alternate function code This example illustrates an impor- Performance ratios and benchmarks registers, a 32-bit cache address tant point about this concurrent become requisite in measuring per- register, and a 32-bit cache control machine. With a sequential micropro- formance. register. The MC68020 is object-code cessor (no prefetch and no concur- compatible with the M68000 family rency of operation), instruction timing PROGRAMMING but has several new addressing mode is easy to calculate. It is virtually im- As shown in the programming model capabilities (table 1) and several new possible with a concurrent micropro- (figure 9), the MC68020 has eight and enhanced instructions (table 2). cessor such as the MC68020. Each in- 32-bit multifunction data registers, A principle in the MC68020 design is support for high-level language and system software implementation. This 31 16 15 87 0 support is provided by the inclusion DO of special instructions that allow array D1 D2 bounds checking with a single instruc- D3 tion, safe manipulation of system DATA REGISTERS D4 queues, support for linked lists, ex- D5 pansion of system trap capabilities, 06 and module support. D7 The MC68020 has three new 32-bit 31 16 15 0 registers: the master stack pointer AO (MSP), cache control register (CACR), Al and cache address register (CAAR) A2 (figure 8). The interrupt stack pointer A3 ADDRESS REGISTER A4 is virtually the same as the M68000 A5 family's supervisor stack pointer and A6 therefore is not really a new register. The terminology has been changed to 31 16 15 0 A7(USP ) USER STACK POINTER reflect a multiprocessing environ- ment. The MSP was created to facili- 31 0 PC PROGRAM COUNTER tate multiprocessing by letting each process have a small master stack 15 _ 0 CCR CONDITION CODE REGISTER area where process-specific exception data is stored, while maintaining a common large interrupt stack area 31 16 15 0 among all the processes. The CACR A7'(ISP) INTERRUPT STACK POINTER clears the entire cache, clears a single 31 16 15 0 cache entry, freezes the cache, and ( A7"(MSP ) MASTER STACK POINTER enables the cache. Each of these func- 15 87 0 tions is controlled by simply setting (CCR) SR STATUS REGISTER a bit in the CACR. The CAAR is used 31 0 with the cache clear entry function to ( VBR VECTOR BASE REGISTER clear a single entry in the cache. 2 0 31 ------Table I shows the MC68020 ad- SFC ALTERNATE FUNCTION dressing modes. Of particular interest DFC CODE REGISTERS are the memory indirect and program 31 0 counter memory indirect addressing REGISTER I CACR CACHE CONTROL modes. 31 0 There are two forms of memory in- CAAR CACHE ADDRESS REGISTER direct addressing and program counter memory indirect addressing: indirect pre-indexed and indirect post- Figure 9: MC68020 programming model. (continued)
166 BYTE • NOVEMBER 1984 THE MC68020
indexed. Program counter memory in- indexed and indirect post-indexed ad- indexed can be used to access oper- direct is similar to memory indirect dressing modes, the base displace- ands through an array of pointers or addressing; however, where the ad- ment (bd) and outer displacement through a pointer located in a record dress register is normally added into (od) can be null (zero), word (16-bit), item or an array of records. The ad- the calculation, the current program or long-word (32-bit) sizes. dress register or program counter, counter is used. The result is position- Indirect pre-indexed addressing index register, and base displacement independent code where the memory adds the index register into the ad- are added together and used as the pointer is accessed relative to the cur- dress calculation before the memory address of the memory pointer. The rent program counter. In indirect pre- indirection is performed. Indirect pre- 32-bit memory pointer is fetched and the outer displacement is added to form the effective address. Table l: MC68020 addressing modes. Indirect post-indexed addressing Addressing Modes Syntax performs the memory indirection and then adds the index register to calcu- Register direct late the effective address. Indirect Data register direct Dn post-indexed can be used to access Address register direct An an element of an array that is pointer Register indirect addressed. The base displacement Address register indirect (An) and address register or program Address register indirect with postincrement (An) + counter are added to form the mem- Address register indirect with predecrement - (An) Address register indirect with displacement (d16,An) ory pointer address. The 32-bit quan- tity at the memory pointer address is Register indirect with index fetched and added to the index Address register indirect with index (8-bit displacement) (d8, An, Xn) register and outer displacement to Address register indirect with index (base displacement) (bd,An,Xn) form the operand's effective address. Memory indirect Memory indirect post-indexed ([bd,An],Xn,od) SCALING AND SUPPRESSION Memory indirect pre-indexed ([bd,An,Xn],od) An index register can be scaled-the Program counter indirect with displacement (d16,PC) value in the register is read and then logically shifted (zero fill) zero, one, Program counter indirect with index two, or four bit positions to the left PC indirect with index (8-bit displacement) (d8,PC,Xn) before it is used. This has the effect PC indirect with index (base displacement) (bd,PC,Xn) of multiplying the value in the register Program counter memory indirect by 1, 2, 4, or 8. The original value in PC memory indirect post-indexed ([bd,PC],Xn,od) the register is not affected by this ([bd,PC,Xn],od) PC memory indirect pre-indexed operation. Using scaling, the same in- Absolute dex value can be used to point to in- Absolute short xxx.W dividual bytes, words, long words, and Absolute long xxx.L quad words, without disrupting the Immediate $ value. Let address register AO be used as Notes: an index and contain the value 3. The Dn = Data Register, DO-D7. AO* 1 (assuming 0 to be the first ele- An = Address Register, AO-A7. ment in the array) will point to the d8,d16 = A two's-complement or sign-extended displacement; ad ded as part of the effective address calculation; size is 8 or 16 bits (d16 and d8 are 16- and 8-bit fourth element in a byte-wide array, displacements); when omitted, assemblers use a value of zero. A0*2 will point to the fourth element Xn = Address or data register used as an index register; form is Xn.SIZE*SCALE, in a word-wide array, A0*4 will point where SIZE is W or L (indicates index register size) and SCALE is 1, 2, 4, or 8 to the fourth element in a long-word- (index register is multiplied by SCALE); use of SIZE and/or SCAL E is optional. wide array, and A0*8 will point to the bd = A two's-complement base displacement; when present, size can be 16 or 32 fourth element in a quad-word-wide bits. array. This scaling takes no overhead od = Outer displacement, added as part of effective address calculation after any memory indirection; use is optional with a size of 16 or 32 bits. on the MC68020. PC = Program Counter. The suppression of the base ad- = Immediate value of 8, 16, or 32 bits. dress register or program counter () = Effective address. allows the use of any index register in [ ] = Use as indirect address to long-word address. place of the base register. Since data (continued)
168 BYTE • NOVEMBER 1984 THE MC68020
registers can be used as index regis- mnemonics are described in table 2. field width determines the number of ters, this gives the MC68020 the abil- A bit field is simply an array of bits. bits to be included in the field. The ity to have addresses in data registers, It can be small enough to be con- base address is the effective address Also, with suppression of the program tained in a register or large enough and can be in memory or a data counter the user has access to pro- to require millions of bytes of mem- register. gram space. ory. Some examples of bit-field ap- In a data register, the offset starts plications are bit-mapped graphics, with the leftmost bit, bit 31, and the BIT FIELD INSTRUCTIONS communications with packed data, width determines the amount of bits The MC68020 has eight new bit-field and assembler op-code construction. to the right of the offset. Register manipulation instructions over the In each bit-field instruction, the field wraparound is allowed; that is, if the previous M68000 instruction set. selection is specified by a field offset combination of offset and width ex- These instructions can be used to and field width. The field offset tend the bit field past bit 0 in the manipulate individual bits in registers denotes the starting bit of the field in register, the field wraps back around or memory. The bit-field instruction bits from the base address, and the (continued)
Table 2: MC68020 instruction set summary.
Mnemonic Description Mnemonic Description Mnemonic Description
ABCD Add decimal with extend DBcc Test condition, decrement, RESET Reset external devices ADD Add and branch ROL,ROR Rotate left, right ADDA Add address DIVS,DIVSL Signed divide ROXL,ROXR Rotate with extend left, ADDI Add immediate DIVU,DIVUL Unsigned divide right ADDQ Add quick RTD Return and deallocate ADDX Add with extend FOR Logical exclusive OR RTE Return from exception AND Logical AND EORI Logical exclusive OR RTM Return from module ANDI Logical AND immediate immediate RTR Return and restore ASL,ASR Arithmetic shift left, right EXG Exchange registers condition codes EXT Sign extend RTS Return from su brouti ne Bcc Branch conditionally JMP Jump BCHG Test bit and change SBCD Subtract decimal with JSR Jump to subroutine BCLR Test bit and clear extend Scc Set conditionally BFCHG Test bit field and change LEA Load effective address STOP Stop BFCLR Test bit field and clear LINK Link and allocate SUB Subtract BFEXTS Signed bit field extract LSL , LSR Logical shift left , right BFEXTU Unsig ned bit field extract SUBA Subtract address BFFFO Bit field find first one MOVE Move SUBI Subtract immediate BFINS Bit field insert MOVEA Move address SUBO Subtract quick BFSET Test bit field and set MOVE CCR Move condition code SUBX Subtract with extend BFTST Test bit field register SWAP Swap register words BRA Branch MOVE SR Move status register TAS Test operand and set BSET Test bit and set MOVE USP Move user stack pointer TRAP Trap BSR Branch to subroutine MOVEC Move control register TRAPcc Trap conditionally BTST Test bit MOVEM Move multiple registers TRAPV Trap on overflow MOVEP Move peripheral TST Test operand CALLM Call module MOVEO Move quick CAS Compare and swap MOVES Move alternate address UNLK Unlink operands space UNPK Unpack BCD CAS2 Com pare and swap dual operands MULS Signed multiply Coprocessor Instructions CHK Check register agai nst MULU Unsi g ned multi ply bound cpBcc Branch conditionally CHK2 Check register against NBCD Negate decimal with extend cpDBcc Test coprocessor condition, upper and lower bounds NEG Negate decrement, and branch CLR Clear NEGX Negate with extend cpGEN Coprocessor general CMP Compare NOP No operation instruction Logical complement CMPA Compare address NOT cpRESTORE Restore internal state of coprocessor CMPI Compare immediate OR Logical inclusive OR CMPM Compare memory to ORI Logical OR immediate cpSAVE Save internal state of memory coprocessor CMP2 Compare register against PACK Pack BCD cpScc Set conditionally upper and lower bounds PEA Push effective address cpTRAPcc Trap conditionally
170 BYTE • NOVEMBER 1984 Circle 125 on inquiry card.
THE MC68020
ea The MC68020 is an multiplication with a 64-bit result, and 5'/4" SSOD a 64-bit dividend with a 32-bit divisor $1 5g S and quotient for division. Lo city. 50 Oty.50 5'/a" DSDD improvement on the 21 0e8. The MC68020 also has special mul- ea. ea. 5'/4" M68000 family. tiply and divide instructions for high- SSDD-96TPI 94 level languages where the result is the $233 5'/4" DSDD-96TPI 2 same size as the operands. That is, a SOFT SECTOR ONLYI and continues with bits 31, 30, etc. 32-bit operand times a 32-bit operand MINIMUM ORDER : 20 DISKETTES Table 3 shows the Motorola assem- yields a 32-bit result. This is equiva- These are factory-fresh 3M diskettes packed in boxes of 10 with Tyvek sleeves, reinforced hubs, identifica- bler syntax and examples of the bit- lent to multiplication in Pascal or C, tion labels and write-protect tabs. Add 5% for orders less than 50 on 51/4' only. field instructions. where an integer times an integer results in an integer of the same size LIFETIME WARRANTYI ON ALL 3M SCOTCH DISKETTES! DIVISION AND MULTIPLICATION data type. If overflow occurs, it will be The MC68020 has several enhance- reflected in the setting of the condi- ments to the original M68000 multi- tion codes after the operation. For ply and divide instructions. The most division there is provision for a 32-bit
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172 BY TE • NOVEMBER 1984 THE MC68020
mainder. Several variations of syntax and operations exist for divide and multiply instructions. For more infor- mation, see the Motorola assembler syntax and operation examples shown in table 4.
BINARY-CODED DECIMAL Two MC68020 instructions, PACK and UNPACK, can store BCD (binary- coded decimal) data in packed form (two digits per byte) and then be ex- panded after calculations. The PACK instruction reduces 2 bytes of numeric The Quick Silver FoxTM data into a single byte, while the UN- PACK instruction reverses this opera- Jumps Over The Big Blue Dog. tion. In both cases, a user-defined constant is added to the original value We really hate to pick on the systems built by hand. The Fox to allow conversion from or to ASCII, big guys but compared to the is burned and tested for 14 days Silver Fox your basic IBM-PCTM in Japan, and further tested after EBCDIC (extended binary-coded- is an overpriced dog. final assembly here in the good decimal interchange code), or any old U. S.ofA. other data format. 256k RAM Why? Well, for starters, your One Year Warranty HIGH-LEVEL LANGUAGES basic Silver Fox comes with 256k The Silver Fox is built better of RAM which acts like a disk so we can back it with a limited, AND SYSTEM SOFTWARE drive so that more of your soft- one-year warranty , four times The MC68020 has extended the ware is accessed at the speed of longer than IBM. We 're Scotts- bounds-checking capability of the light rather than the speed of a dale Systems and since 1980 M68000 family with the introduction mechanical drive head. we've shipped over $ 10,000,000 of microcomputer equipment of two new instructions, CHK2 and 1.6 Megabytes directly to microcomputer users. CMP2 (check 2 and compare 2). CHK2 You also have more than twice Because we deal directly with and CMP2 perform comparisons on as much software to access be- users, we think we have a better the upper and lower bounds and can cause the Silver Fox comes with idea of what you want. So the dual 800k disk drives for a total Silver Fox includes graphics be signed or unsigned. The CMP2 in- of 1.6 Megabytes. Yet the Silver with twice IBM's resolution, a struction sets the condition codes ac- Fox can read and write to all printer port, a keyboard with a cording to the result of the operation. popular PC formats. big return key, and a 12 ", high- The CHK2 instruction sets the condi- 13 Free Programs resolution monitor as standard tion codes and causes a system trap equipment. 1. MS-DOS TM Of course, you could spend if either boundary condition fails. 2. HAGEN-DOS $4729 at Computerland for an The MC68020 also offers other new 3. M-DISK IBM-PC that will perform almost security and system-level instructions. 4. WordStarTM as well as a Silver Fox . But why 5. EasyWriter bother when you can call The CAS and CAS2 instructions use 6. DataStar the same read-modify-write cycle as 7. ReportStar 1-800-FOR-A-FOX the M68000's TAS (test and set). 8. FILEBASE and get your These operations are indivisible and 9. CalcStar 10. Color Graphics Basic noninterruptible, which ensures data 11. MailMerge security in single and multiprocessor 12. SpellStar $1398 systems. 13. 25 Games, graphics to perform like $4729? The CAS (compare and swap) in- and utilities For additional information call 1-800 - 367-2369, or in AZ, The best free software bundle AK, or HI call (602 ) 941-5856 . Or write Silver Fox Computers, struction compares the contents of a 617 N . Scottsdale Road #B , Scottsdale , AZ 85257. in the business, and the Fox will IBM-PC price is based on a phone quote from the data register (the compare register) to run some programs written for Mesa , Az Computerland on July 30 , 1984. Price included 256k RAM , dual 360K drives (80OK ' s weren 't available), the operand at the effective address. the IBM-PC like dBase II and software, and a graphics monitor. If the operand and the contents of the Multiplan , and programe written Trademarks : Silver Fox and Hagen-DOS, Scottsdale Systems Ltd . IBM-PC , International Business Machines data register are equal, the contents for Sanyo's new MBC-550 series. Corporation. Wordstar , Calcstar, Mailmerge, Spellstar, and Infostar , Micropro International. MS-DOS , Multiplan, of a second data register (the update Reliability Microsoft Corporation . Filebase , EWDP Software. Inc. dBASE II , Ashton-Tate. register) are used to update the op- Because the Silver Fox is Ordering : Telemarketing only, Silver Fox price is for cash , F.O.B. Scottsdale , price subject to change , product erand at the effective address. If the born on a totally automated subject to limited supply . Visa, Mastercard add 3%, AZ production line in Japan it is residents add 6 %. Returned merchandise subject to a (continued) 20% restocking fee. Personal/company checks take up to inherently more reliable than 3 weeks to clear No C.O . D.'s or A.P.O.'s.
NOVEMBER 1984 • BYTE 173 THE MC68020
compare register and the operand are The MC68020 introduces module change and type I where the access not equal, the operand is unchanged, support to the M68000 family. level can be changed . No external but the value in the compare register Modules are high-level subroutines hardware is necessary for type 0, but is updated with the operand at the ef- that can have different levels of pro- for type I CALLM, the MC68020 fective address. The CAS2 instruction tection or access. Tvo new instruc- relies on external hardware (a mem- is.basically the same as CAS, but there tions, CALLM and RTM , support this ory management unit) to verify that are two compare registers (upper and module implementation. calling modules possess the proper lower bound), two update registers, The CALLM instruction initiates the access level for the called module. and two operands at two different ef- module call by referencing a module fective addresses. The CAS and CAS2 descriptor. The module descriptor VIRTUAL MEMORY instructions are useful for updating contains access information , control The MC68020 supports virtual mem- system counters and for insertion and information , and the entry point for ory, the ability to make a small deletion from linked lists. the called module. If the module ac- amount of main memory look like a The MC68020 also has expanded cess is valid, the CALLM instruction large or infinite amount of memory by system trap capabilities in the form of creates a module stack frame, stores using secondary storage devices to the TRAPcc instruction, where any the current module state in that frame, swap currently executing code seg- condition code is allowed to be the and loads a new module state from ments into the main memory. In a vir- trapping condition. The TRAPcc in- the module descriptor. tual memory system, the processor struction can be followed by a word The RTM instruction removes the has access to a limited amount of fast or long-word quantity that can be module state that was stored on the main memory (the physical memory used to convey information to the module stack frame and returns to the of the system), while the user writes trap handler, such as a high-level lan- calling module. The MC68020 module programs that might require millions guage statement number or other de- support is broken into two types: type of bytes of memory (the virtual mem- bugging information. 0 where there is no access level ory of the system). If the processor attempts to access a memory location not currently re- siding in physical memory, a page fault occurs. The processor suspends the current instruction until the re- quired memory is moved into physical memory from slower but larger sec- ondary storage. When the required program segment is in physical mem- ReadAny ory, the instruction is allowed to com- plete execution. All this activity is transparent to the user, so physical memory appears to be the same size as virtual memory. Virtual memory size has been increased from a Good Mintls 16-megabyte direct addressing range ALIMMI, in the MC68010 to 4 gigabytes in the MC68020.
CONCLUSION Laluly?* The MC68020 is a fully compatible member of, and an improvement on, the M68000 family of processors. It With the Mind Prober' you can. In just minutes you can have is backed by the same powerful soft- a scientifically accurate personality profile of anyone.This new ware and hardware design-support expert systems software lets you discover the things most tools that back other members of the people are afraid to tell you. Their strengths, weaknesses, M68000 family. For more informa- sexual interests and more. Mind Prober. Another insightful product from the Human Edge' Software Corporation. Call tion, see the MC68020 32-Bit Micropro- 1-800-624-5227 (in California 1-800-824-7325) for more cessor User's Manual (Prentice-Hall, informationst the local 1984) and the three-part article by ' '" " lion of the nearest retailer. Thomas W. Starnes, "Design Philos- IBM • Apple • Macintosh • Commodore ind Pmhei ophy Behind Motorola's MC68000" Software That Lets You Read People Like A Book. (April-June 1983 BYTE). n
174 B Y T E • NOVEMBER 1984 Circle 200 on inquiry card.