BY GREGG ZEHR

MEMORY MANAGEMENT UNITS FOR 68000 ARCHITECTURES taches to the system bus and is idle to an unused section of memory. Al­ Design options that most of the time. the MMU attaches though the MMU is obviously useful directly to the CPU address bus and in a system that has multiple users speed up memory intercepts each CPU read or write running separate programs. it is just cycle. The CPU and MMU combine to as useful in a multitasking single-user management form a new functional unit. Several system. manufacturers have even moved the In a simple 68000 system that does · MMU onto the same silicon as the not have an MMU (figure 1). a typical he Motorola 68000 family CPU. in effect declaring that you can't memory read cycle begins when the of microprocessors has have one without the other. CPU asserts an address and address spawned a whole new The most important function pro­ strobe (AS). and the cycle ends when group of computer sys­ vided by all MMU designs is the abili­ the memory places data on the data tems. The original 68000. with its ty to relocate a program to another bus and activates the data transfer large. linear addressing range. makes part of memory according to a set of acknowledge (DTACK) line. Assuming itT a natural for single-user. personal pre-assigned translation rules. This that the memory is very fast. the cycle graphics workstations such as the relocation is done in hardware. with­ can be completed in eight transitions Macintosh. And multiuser systems out requiring any modification to the of the clock. or 500 nanoseconds for based on the 68020 can offer com­ application software. an 8-MHz CPU. puting power and speed that rival Before a system with an MMU runs In a 68000 system that has an MMU many minicomputers-often at a frac­ a program. the operating system con­ in series with the CPU's address bus tion of the cost. Not surprisingly, figures the MMU so that the program (figure 2). for each read cycle the CPU many of the design features for these can be moved to and run in an avail­ asserts a logical address and logical larger systems have evolved from well­ able section of memory. The program address strobe (LAS). (The address established minicomputer architec­ then begins execution. unaware of the and address strobe lines are now tures. Memory management units. or MMU's actions. For example. if a pro­ (continued) MMUs. are one example. The MMU gram has been compiled and linked Gregg Zehr is a senior design engineer at function came about as minicomputer with a starting location of 400 but that Altos Computer Systems (2 641 Orchard designers began to include special location is being used for some other Parkway, San Jose. CA 9 5121) . He received hardware to expand the amount of purpose. the operating system con­ his M.S.E.E. from the University of Illinois addressable memory. MMUs have figures the MMU hardware to convert and is interested in advanced computer now become a key feature in modern all the program's memory references architectures. computer architectures. In fact. several MMUs designed specifically for the 68000-family architecture are available (see table 1).

THEORY OF OPERAT ION The MMU functions at a very low level in the computer system. Unlike a UART or other peripheral chip that at-

NOVEMBER 1986 BYTE • 127 MEMORY MANAGEMENT UNITS

prefaced with the term logical since these addresses are physically at­ translation. Second. the MMU must they are the absolute addresses from tached to the memory.) The memory monitor a wide input bus and drive the CPU's point of view.) The MMU ac­ again responds by putting dataon the a wide output bus. Expect a single­ cepts the address and logical address data bus and asserting DfAC K. chip MMU for a 68000/680! 0-based strobe and then translates the logical But. as the saying goes. nothing is system to have at least 64 pins and address according to a set of transla­ free. There are two penalties for at­ an MMU for the 68020 to have over tion rules into a physical address. It taching the MMU in series with a !20 pins. Although the cqst of a then asserts a physical address and a bus-speed and pin count. First. each device is directly proportional to the physical address strobe (PAS). (The memory cycle must now be slowed number of pins on the package. in term ph!fsical is used to indicate that down while the MMU performs the most systems. fortunately. the cost of adding MMU hardware is less than developing a layer of software to per­ Table l: A summar!f of memor!f management units. form similar functions. Device Manufacturer Translation CPU Supported Since the MMU operates on each memory access. it is the perfect place 68451 Motorola Segmented 68008/00/1 0 to add special hardware support for 68905 Signetics Segmented/Paged 68000/1 0 certain operating system functions 68070 Signetics/Philips Segmented/Paged Integrated 68000 that are not strictly related to address 68910 Signetics Demand paged 68010 68920 Signetics Demand paged 68020 translation. The most important extras 68461 Motorola Demand paged 68010/20 are memory protection. cache. and 68851/MMB Motorola Demand paged 68010/20 virtual memory support hooks. For 68851 Motorola Demand paged 68010/20 example. by monitoring the three function code bits from the 68000. the MMU can divide the CPU's ad­ dress space into user- and supervisor­ level instruction and data areas. Thus. Address while you debug a program. the MMU can trap unauthorized (usually unin­ AS tentional) attempts to access reserved 68000 MEM system functions such as memory­ CPU Data mapped l/0 or interrupt vectors. In this case. the MMU hardware ensures DTACK that a bug in a program does not hang the system.

PAGED TRANSLATION Block Diagram The translation rules that an MMU CPU sends address and AS to MEM uses can be classified as being either 1 paged or segmented. Paged systems usually divide memory into equal-size 2 pieces (pages). while segmented sys­ tems divide memory into variable-size State Diagram MEM returns data and DT ACK to CPU pieces (segments). Both of these con­ cepts first appeared in mainframe and S1 S2 S3 S4 S5 S6 S7 so so minicomputer systems. In a paged translation (figure 3). the CLOCK MMU divides the logical addresses into two parts: the upper bits are called the segment number and the CPU - AS lower bits are called the page index. The page index. which determines the page size. is passed directly through ....______.n the MMU unmodified. The segment MEM - DTACK number is used as an address mto a segment table. The data from the seg­ Timing .______.n ment table is called the page address and forms the upper part of the Figure l: A 68000-based S!fStem without an MMU. physical address. Logically then. a memory location is described by a

128 BYTE • NOVEMBER 1986 MEMORY MANAGEMENT UNITS

13-bit offset into one of 2048 pages. ory. The descriptor also includes the segmented MMUs. occurs when vari­ Physically. memory is divided into 2 K length of the segment. The segment able-size segments leave holes in pages with a fixed size of 8K bytes . . offset should be smaller than the physical memory that are too small . Although several popular 68000/ length; if it is not. the memory cycle for practical use. Several algorithms 68010 systems have been ' built by is aborted and an error is indicated. have been developed to simplify simply implementing the segment Assuming there is no error. the trans­ allocation in segmented systems and table with high-speed static RAM. lation is completed by arithmetically are described by Baer and Knowlton such an approach does not fit into adding the segment offset to the base (see the Bibliography). 32-bit 68020 designs very well. If the address. Physical memory can now be lowest 12 lines are used for the page divided into 2 56 variable-size s·eg­ DEMAND·PAGED TRANSLATION

index. there are 20 lines left. This im­ ments. Each ?egment can be from I As CPU buses become wider. the plies that the segment table RAM to 64K bytes long. amount of memory required to store must hold I megabyte of page Although variable segment size page tables or segment descriptors numbers. allows memory allocation to fit mem­ becomes larger. This in turn increases Since pages have a fixed si�e. this ory requests better. it leads to another the cost of the MMU and the over­ type of translation is susceptible to in­ problem called external fragmenta­ head associated with task switching. ternal memory fragmentation. This tion. This problem. which is unique to (continued) means that some segments will likely include memory that is unused. For Logical Physical example. suppose that a program address address needs I K byte of storage for its data. LAS MMU PAS When run. the system assigns the pro­ _... gram one 4K-byte segment. The other 68000 MEM 3 K bytes become a memory fragment . that cannot be used by any other pro­ CPU Data gram. Most paged systems include at least two levels of translation and a DTAC K ""' smaller page size that reduces such - internal fragmentation. Translation A simple trick. however. can in­ Block Diagram crease the capabilities of this ap­ 2 proach. The segment table RAM can MMU checks authorization MMU translates logical address be wider than the segment number to provide additional control bits. and from the physical address bus. these control bits cannot be distinguished from normal 68000 control lines. So these extra bits can be used as ad­ dress lines. and in fact this technique 5 has worked to extend the addressing MEM returns data and DTACK to CPU capability of CPUs ranging from the State Diagram 6502 to the PDP-ll. Other uses for so S1 S2 S3 S4 S5 w S6 S7 SO these bits include memory protection attributes. virtual memory paging in­ CLOCK dicators. and cache inhibit mark bits.

SEGMENTED TRANSLATION . . CPU - LAS In theory. segmented translation .._____ should be more efficient since most memory requests are not integer __.n multiples of some fixed-size page. The MMU - PAS upper bits of the address are called the segment number and the lower bits are called the segment displace­ MEM - DTACK ment or offset (figure 4). The segment number is used to address a table of Timing Diagram .._-'1� Tr anslation delay descriptors. The descriptor includes a base address. which is the starting ad­ Figure 2: A 68000-based system with an MMU. dress of the segment in physical mem-

NOVEMBER 1986 • BYTE 129 14 Intensive MEMORY MANAGEMENT UNITS On-Line Users At Same Time? Accessing a Common Data Base? ly more efficient than loading all the No Waiting At The Terminal ? The demand-paged MMU provides support for 32-bit microprocessors by descriptors each time the program No Performance Degradation? allowing translation tables to be runs. stored in main memory (figure 5). When a demand-paged MMU finds YOU BET! When the system initializes. the CPU the translation information in its TLB. With CompuPro's Multi-Processor writes the translation tables into main it translates the logical address into memory and then tells the MMU a physical address. If the translation MP14'" where they are by writing a pointer in­ information is not in the TLB. the to a control register. The MMU in­ MMU must back the CPU off the bus cludes bus control logic that allows it while it searches the translation tables to search the tables and find the cor­ in the main memory. This search pro­ rect translation information. To avoid cess is referred to as a table walk. At searching the tables for each transla­ the end of its table walk. the MMU Bill tion. the MMU maintains a buffer of writes the new descriptor into its TLB Godbout, recently used translation information and tells the CPU to retry the access. architect in a small cache memory called a Although the demand-paged MMU of the translation lookaside buffer (TLB). provides an elegant solution to a dif­ Comp uPro Thus. once the tables are established. ficult problem. the table walk process MPJ4, the MMU can translate any logical ad­ is slow. A typical table walk will cost .__ ---' says, ______dress without advance warning from the CPU 20 or more wait states. This "The only way to get this kind of per­ the CPU (translation on demand). This means that the performance of the fo rmance is to build it in, chip by chip. arrangement also means that the MMU is governed by the percentage That's what we've done. The MP14 con­ MMU will only take time to fetch of times that it finds the needed in­ tains 8 separate 10 MHz Intel 286 and those descriptors that are actually formation in the TLB-the TLB hit rate. 186 CPUs, all processing at the same used by a program; in a timeshared. If the CPU includes an efficient cache time. It has 6.5 megabytes ofhigh-speed multiuser system this method is usual- memory. the TLB hit rate may very no-wait-state RAM. And it has 80 megabytes of buffe red high-speed hard 24-bit logical address disk storage. " 23 13 12 0 Here's the best part: With the same operating system, the same application llllllllll llllllllllll software, you can start with the $5,995 CompuPro 10 Plus'" ( 4 intensive users at . I I I the same time), move up to the $18,995 CompuPro MP14, and go way beyond that to the CompuPro MP42'" inten­ Segment number (42 11 sive users on-line at the same time, 24 separate 286 and 186 CPUs, 19.5 mega­ Page indeX bytes of RAM, no waiting, no perform­ Segment table 13 ance degradation, $49,995!). RAM 2048x11 These superb multi -processor sys­ tems . are completely tested, are oper­ ating today at customer sites, and will be shipped 23 days after receipt of order. The MP14 is available through Compu­ Pro's 127 dealers. Third party mainte­ nance is available through Sperry Corp. Page address The MP14 could be the answer to your 11 hardware problems. Call today, (415) 786-0909, fo r the complete story of this 23 13 12 0 remarkable multi-processor system, and the telephone number of your near­ est CompuPro dealer. OEMs and VARs I I I I I I I I I I I I I I I I I I I I I I who wish to port their applications to the I 24-bit phIysical address I MP14, please contact Bill Godbout. Figure 3: In a paged translation the upper bits are called the segment number and the lower bits are called the page index.

Trademarks: M Pl4.{ii M 1'42.mp \0 Plus.uP CompuroPro: Vias)'n·· Corporation.

130 BYTE • NOVEMBER 1986 Inquiry 387

MEMORY MANAGEMENT UNITS ·------· . I I well become the factor that limits demand-paged memory system pro­ :- Boost : system performance. vides the best features of both paged If you plan to include an MMU in and segmented systems and has : cursor : your next design. you must match the become the standard for multiuser CPU and MMU combination with the UNIX machines. overall system architecture and cost. iI speed. iI For each possible MMU design alter­ MMU DESIGN OPTIONS native you must consider hardware Given an understanding of the MMU's and software issues. The most impor­ theory of operation and the system tant hardware issues include how to design considerations. there remain : Stop : minimize translation delay. how the the actual design implementation op­ MMU should signal error conditions tions. The first and most obvious op­ to the CPU. and how to reduce hard­ tion is to not usean MMU at all. That's i cursor i• ware overhead related to a software exac ly the design decision made for • t I task. Of course. the nature of these the Apple Macintosh. the Cmmo­ With all the recent hooplaover performance, I issues depend on whether you are dore Amiga. and the Atari 520ST. Al­ I it'srun ironic that two of the-o PC's ergonomicn. I deficiencies have been overlooked -its slow using a 68000. 68010. or 68020. though the graphics interface used by I cursor, and the tendency of thecursor to I remain in motion (run-iln) after a cursor key In typical systems. a discrete paged these machines. which includes multi­ I has been released. Finally, the solution - I Cruise Control™ from Revolution Software. MMU will support a simple operating ple windows and desk accessories. I I system or real-time executive in · a may give the impression the systems Cruise Control is a new productivity tool for 1 serious PC. users. It boosts cursor speed, 1 small single�user or embedded con­ perform multitasking quite naturally. typically by 3-5 X. It eliminates annoying I cursor run-on. And it adds hands-free 1 trol system. Segmented systems have none of these systems includes any cursor navigation to any application. . been used in large computers for MMU hardware. Instead. they place I If you use 1-2-3, Symphony, dBASE, Reflex, I or Paradox, you need Cruise Control's Anti- many years. but the advantages are the burden of memory management I Skid Braking. Here's what the leader of one 1 probably not worth the additional on application software. In each case 1 Lotus users group said about Cruise Control: 1 (continued) complexity in a small system. The "OrJce I used it, I wanted it! Excellent idea. I Verypractical . One of the best prpgrams I I ever sent to us for review!" 1 If you useWord Perfect, MS-Word, Q&A, 24-bit logical address I Display Write, MultiMate, WordStar 2000, I 23 Framework, PC-Write, or SideKick, you Q I need Cruise Control's Screen Runner, the I high-performance, adjustable-speed cursor.

I Cruise Control's namesake feature takes the I I drudgery out of paging through data base I i l I I I l I records, long documents,and large I I spreadsheets. It lets you repeat any key, I III I I I I,I I I I I I I I I I Il hands-free - at the speed of your choice. I I Segment descriptors 8 16 ,-\nd there's more. A Chronometer "types" 1 the time or date into your application at the 1 (256) Segment number Segment offset current cursor position. The keyboard- 1 controlled Screen Dimmer protects your 1 privacy. The programmable Auto-Dimmer I extends the life of your display screen. I length base Compatible with thousands of today's I popular programs, including Lightning, I SuperKey, and Ready!. Uses only 3K RAM. I For DOS 2.0 or later. Not copy-protected. 1 1 No risk, 60-day money-back guarantee. 1 I I • Cr,uise • 8 Segment base From now until 12/31186: :I Collii-ol� :I + 1 1 CailOn nowly to order$29 by .95.credit I card (VISA/MC/AX): I

23 0 I 1 I I 20Or, mail1- $29.95366 plus-4445 $3.50 I shipping and handling to: I I l I l I I l I I I !llllll_l_L ] I I 1 1 24-bit physical address I I I Revolution Figure 4: In a segmented translation the upper bits are called the segment number and the lower bits are called the segment displacement or offset. : @�[.��,..0 : ·------·

NOVEMBER 1986 • BYTE 131 MEMORY MANAGEMENT UNITS

the designers have provided a real· an application running on one of to decide what to do if those routines time executive with a set of low-level these machines must understand cannot allocate the requested interface routines and a complex set when and how to call low-level rou­ memory. of so-called gentlemen's agreements tines for tasks such as memory alloca­ Also. when a program runs on one to provide multitasking. For example. tion. It is also up to the application of these machines. it has access to all system resources. and a programming error can easily write over any of the other programs in memory including the operating system. This is usually TLB hit or miss MMU looks in TLB for page descriptor a fatal situation to the system. requir· IF descriptor in TLB ing a power reset. Even a modest THEN MMU sends physical address and physical AS to amount of MMU hardware could im­ CPU sends logical MEM (5) prove the performance and reliabili­ address and .logical ELSE MMU searches descriptor ty of these machines by reducing the AS to MMU table in MEM for correct page amount of memory management the descriptor (4a), updates the TLB operating system has to perform and (4b), and signals the CPU to retry by providing memory protection in the memory cycle (6) · hardware. A paged MMU can also be built using discrete logic and high-speed 7 static RAM to hold the segment table. MEM returns data and DTACK to CPU This approach was very common in early 68000-based multiuser systems. Figure 5: Demand-paged translation state diagram. The basic paged-translation concept is usually extended to two levels (figure 6). In this approach. the logical address is divided into three fields. Function Context The segment number is extended to code register 24-bit logical address include the 68000 function code bits FC2 FC1 3 0 23 17 16 11 10 0 and a context register. The additional field, called the page number. is used to address the page table indicated I I I I II I I I I II I I I I II I I I I I I I by the segment table output. Most I J operating systems set up the segment I I tables once. then use the context Segment number register and page tables to allocate 13 memory for each task. The page tables are small enough that they can be paged to main memory when a Page number task switch occurs. Segment table 6 THE 68451 MMU - Page index Shortly after the first 68000 CPU chip 11 made its debut the Motorola 684 51 appeared. It was. in fact. one of the � first monolithic MMUs available to system designers. The 684 5 is a seg­ Page table I I mented MMU that comes packaged as a 64-pin DIP (figure 7). It includes 3 2 segment descriptors that partition Page �ddress memory into variable-size segments. 23 11 10 0 Each of these descriptors also in­ cludes an 8-bit status register that pro· vides support for a virtual memory I I I architecture. l11J I I 24-bitI I I physicalI I I I Iaddress I I I I 11J There are several serious limitations with this device. however. The biggest Figure 6: 'TWo-level paged translation. problem is that 32 descriptors are not enough. The 684 51 includes special

BYTE NOVEMBER 1986 132 • Inquiry 207

· MEMORY MANAGEMENT UNITS MicroCom Systems OUTSTANDING SOFTWARE For IBM PC's and Compatibles

PER PER I lines that allow several chips to be If you are porting an operating sys­ $ 50 DISK $ 00 DISK chained together to expand the tem to a machine that does use this SMALL3 QUANTITIES FOR3 TEN OR MORE 11 OFF 5 DISKS OR MORE WrTH THIS COUPON number of descriptors. but since the device. you should consider using the D CAD 1 Altamira, an object oriented CAD MMU still costs almost twice as much binary buddy memory allocation program,- and Supergraph 3. Color gr. req'd. COMM 1 as the CPU. this is an expensive op­ algorithm as described by Knowlton. D The ever popular QMODEM 2.0E modem commun- ications program. COMM 2 tion. The 684 51 is also relatively slow. This algorithm should allow you to 0 PROCOMM 2.3, an excellent modem program- with terminal emulation. TYpically, translation requires more take advantage of the variable seg­ 3 D COMM Communications utilities to be than one wait state (especially in a ment size while reducing fragmenta­ used with -QMODEM or PROCOMM. DATABASE 3 multi-MMU system), and if a task tion and operating system memory 0 The Pbase relational database manager- with query language. switch requires CPU intervention (and allocation overhead. FINANCE 1,2 (2 disks) PC-Accountant and 0 a personal finance manager. most do). the overhead is greater than - D GAMES 1 Chess. 3-D Packman, Kong. that of a simple paged system. The THE 68905 BMAC Spacewar, Janitjoe,- and more. Color gr. req'd. D GAMES 2 Oubert. Pango, Centipede, 684 51 also lacks support for CPU The 68905 basic memory access con­ Monopoly, Zoarre,- and more. Color gr. req'd. 3 cache memory or the 32-bit 68020. troller (BMAC) is the first in a series D GAMES Blackjack (you sel rules). Arm Chair QB, and- Empire (war game). Since all of these problems have been of ambitious announcements by GAMES 4 D Star Trek. the original Collossal resolved with a new Motorola MMU Signetics and its parent company, Caves ADVENTURE,- and Castle. D GAMES 5 The HACK adventure game chip, the 688 51, the 684 51 will prob­ Philips. The BMAC integrates MMU from the uni-versities. Like Rogue. ably not be used in many new and cache control functions for 0 GAMES 6 Pinball, Othello. Dragons, Sopwith (fly- one). and more. Color gr. req'd. designs. (continued) GAMES 7 D Round42 (16 color graphics), Backgammon,- Risk, and more. Colo r gr. req'd. LANGUAGE 2 0 The renowned SMALL-C compiler and a - C interpretert FCO C3 LANGUAGE 3 8086/8088 assembler, Logical 0 disassembler, and tutorials. address Cycle address R/W - r - LANGUAGE 4 assembler language A8-A23 D 370 Address space space number on the PCI A must- for IBM 370 users. LANGUAGE 5 Turbo Pascal interactive table D I Address Address Write debug. pop-up -help, formatters, etc. MUSIC 1 I space space protect D Many clever tunes. and an Logical base address excellent color- graphics music editor. mask number bit ORGANIZER 1 I 0 DESKMATE, a sidekick clone, and the JUDY- calendar program. Logical It ORGANIZER 2 t It t t D Menu driven project address - fMask � Mask management using- critical path scheduling. Write ORGANIZER 3 mask 0 The PC-OUTLINE ' violation windowing outline editor/thought organizer. ., Logical Logical - PICTURES 2 I logic 0 High res digitized graphics compare compare pictures. Color- graphics required. D PINUP 2 Provocative high res digitized Range match Space match graphics pinup- s. Color graphics required. [ J D PRINTER 1 Font and sideways utilities, Physical base No write spoolers, banner- makers, and more. f SPREAD 1 The PC-CALC spreadsheet .---"'-'· L---'L-...1...- address violation 0 program. Physical address - I ·o UNIX 1 A Unix command shell and various format1on ! 1 Unix commands- for DOS. Emacs, etc. 1 \ I D UTILITIES 1 A collection of invaluable I general purpose- DOS utilities. A must. 1 of 32 descriptors D UTILITIES 2 More invaluable general I purpose utilities- including NEWKEY. 3 D UTILITIES A comprehensive set of I debugging and- diagnostic utilities. Physical address UTILITIES 4 I 0 The Ultra File Utilities; · Norton-like utilities- for diskettes. 1 WORD 2 ?�- 0 Waterloo Script (like IBM's Descriptor format SCRIPT) text- formatter for the PC. I NEW (LATEST) RELEASES -

I COMM 4,5,6,7 (4 disks) Latest RBBS E!] - I Bulletin Board System- 14.1A. 10 DATABASE 1,2 (2 disks) File Express 3.7, I menu driven database- manager. EDUCATION 1 Interactive DOS tutorial for I Logical base address I D new PC users. Makes- learning DOS painless. 1 LANGUAGE 1 The artificial intelligence Log1ca1 address mask D Segment status register languages LISP -(XLISP 1.6) and PROLOG. I LANGUAGE 7 D Pascal interpreter/compiler. Great for learning/debugging Pascal. 1------P _hys_ ic-al_bas_e _a E I - , d_d ...,.re_s___s _-+_.- � PRINTER 2 Letter quality print for your Address space Segment status IIli P HwPI I D Epson compatible printer. be eg s e ______I I I ___..::".:::um::.::::___..::-' _:_:r '-"'.:::i t::.r =--=--____ --_lu - WORD __ __ 1 PC-WRITE 2.6, a powerful and 1-- Address space -+ ---7-- - D I complete word processing system. - mask - 1 WORD 3 0 The PC STYLE writing style analysis program. Bbits Sbit 1 - � � Cost of Disks 1-- ·lo( I CA Res 7% Tax Ship/Handling ------$1.00 I Total Enclosed --..-iiil Figure 7: 68451 MMU. MlcroCom Systems P. O. Box 51657, Palo Alto, CA 94303 _) ------NOVEMBER 1986 • BYTE 133 MEMORY MANAGEMENT UNITS

68000/68010-based systems into a provide fast access to private data controller that effectively provides single 84-pin grid array package structures. demand-paging capability for 68010 (figure 8). Yo u can program the BMAC The BMAC also provides support and 68020 systems. to perform segmented or paged for a logical bus cache memory. Plac­ translation. ing the cache on the logical bus allows THE 68461 MMC Most MMUs that support paging translation and cache searches to oc­ Shortly after introducing the 32-bit data between hierarchies of memory cur in parallel. but in order to avoid 68020 CPU chip. Motorola an­ allow two levels that are usually cache coherency problems. care nounced its plans to develop a dedicated to primary memory (RAM) should always be taken to flush the demand-paged virtual MMU. which and secondary memory (disk). The cache at each task switch. Although would support multitasking. multiuser BMAC also supports a third level. a logical cache is fast. it may not. how­ environments such as UNIX. Unfor­ local memory (RAM). Although most ever. be transparent to the operating tunately. the new MMU chip was not operating systems do not currently system. ready in time to be shipped with the support this third level. local memory Signetics has also announced the first CPUs. Recognizing the need for could be used to provide improved 68910 and 68920 memory access MMU support. Motorola made the performance in a multiprocessor sys­ controllers. or MACs. that extend the 68461 memory management con­ tem. Using this local memory would BMAC design by including a micro- troller (MMC) available as an interim solution-until the single-chip 688 51 paged MMU is available. The 68461 is fast; it's built with Cache memory (TLB) A10-A23 Cache controller Cache control and Motorola's 2800-series bipolar gate Page . CADDO-CADD4 array. and it can translate a 16-MHz description CAM CAM RAM 68020 access in one wait state. The MMC is housed in a 147 -pin grid ar­ ray package. which requires a heat sink. The MMC does not include everything required to implement a demand-paged MMU. To use this device. you must use external logic to implement the TLB function. A single­ set-associative TLB can be built with 15 or 16 external chips (figure 9). Even this simple TLB architecture. however. DO-D15 offers a hit rate in the UNIX environ­ ment of better than 90 percent. which is high enough to provide good sys­ Control signals tem throughput. An MMU incorporating the MMC Figure 8: 68905 block diagram. can provide demand-paged memory support for either the 68010 or the 68020. It includes the extra control bits that are required for memory pro­ tection. virtual memory. and CPU LA10-16. FC1 . FC2 Address TLB RAM cache memory functions. It maintains its translation descriptors in a tree TAG (1 K x 22) comparator HIT1 , 2 Data structure in main memory. The trans­ lation process divides the logical ad­ 2 X TMS2150 dress into three fields. which are used 68461 to search three levels of descriptors MMC (figure 10). Limit fields at each level - 0"'LA1 0-31 ll PA 10-31 of the table reduces the total amount of RAM needed to hold the descrip­ Logical address bus Physical address bus Ut tors. Yet a typical system requires LA0-9 PA0-9 ) about 128K bytes for the MMU. Pro­ Data bus tection bits at each level of the table D0-31 can provide read and write access protection based on the function Figure 9: Block diagram of MMU using 68461. codes. For example. you can con­ figure a page to allow supervisor read

134 BYTE • NOVEMBER 1986 MEMORY MANAGEMENT UNITS

and write access while a user mode write will generate an error. FC2-0 Logical address LA31-0 2 0 31 25 24 18 17 10 9 0 THE 68851 PMMU The Motorola 68851 paged MMU. or -----., PMMU. provides complete demand­ D L-----L-----.1...-----11 r--1 7 8 10 paged MMU support in a single chip. Root This advanced design includes a 64-entry fully associative TLB that is more efficient than the single-set design of the 68461 MMC. Since the PMMU attaches to the 68020's co­ processor interface. its registers are extensions to the existing program­ Fetch mer's model of the CPU. The CPU/ 8-byte PMMU combination adds new MMU pointer instructions to the existing 68020 in­ Fetch struction set. While all the other 8-byte devices discussed here decode the pointer MMU's control registers as mem­ ory-mapped i/0. this coprocessor ap­ proach integrates the PMMU into the Fetch 4-byte programming environment. For exam­ page descriptor ple. a single instruction allows a con­ Limit ditional branch based on the condi­ tion of the PMMU status register. Fill TLB The PMMU's translation mechanism is similar to the MMC. but the PMMU 10 TLB offers more flexibility. The PMMU forms physical page sizes can range from 2 56 to 32K address on retry bytes. and page tables are not fixed 31 10 9 0 at three levels. The PMMU can parti­ Physical address PA31-0 tion the logical address into one to four fields. each of which serves as an index to the table at that level. Figure I 0: Demand-paged translation. PMMU hardware includes arbitra­ tion logic for both the logical and the ' physical bus. A separate pointer already assembled on a printed cir­ 68000 CPU and a simplified 68920 register is provided for an alternate cuit board. which is pin-for-pin com­ MMU in a single device. such as the logical bus master. such as a DMA patible with the 688 51. Yo u can plug recently announced Signetics/Philips controller. In a multiprocessor en­ this board-level product. the 68070. are sure to abound in the vironment. PMMU's can share de­ 68KVMMB851. into your next 68020 future. The advantages of putting the scriptor tables in main memory, design to provide MMU support until · CPU and MMU on the same silicon in­ reducing storage requirements. The the 688 51 is available in production clude faster translation. lower pin PMMU offers full support for system quantities. count (and therefore cost). and im­ functions such as virtual memory. proved software portability. Moreover. cache memory. and a floating-point FUTURE TRENDS by offering silicon that can simplify coprocessor. · it's difficult to determine which has the layer of software required for Besides using the CPU function advanced more rapidly. the micropro­ multitasking, this device is sure to find code bits for memory protection. the cessor or the MMU. Certainly the its way into the next generation of

PMMU adds up to eight levels of ac­ supermicrocomputers available today mouse-and-windows machines. • cess authorization. This concept is depend on the MMU just as much as also extended into the 68020 call the microprocessor to provide high BIBLIOGRAPHY module (CALLM) and return from performance for a lower-than-ever · Baer. )ean-i..Dup. Computer Sijstems Architec­ module (RTM) instructions so that cost per user. If history is any indica­ ture. Rockville. MD: Computer Science authorization can be verified at the tion. IC manufacturers will continue to Press. 1980. subroutine level. integrate more and more system func­ Knowlton. Kenneth C. Fast Storage Al­ "A For the faint of heart. Motorola also tions onto silicon. locator." Communications of the ACM. vol. offers the 68461 and discrete TLB Integrated units that combine the 8 (October 1965). pages 623-62 5.

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