BY GREGG ZEHR MEMORY MANAGEMENT UNITS FOR 68000 ARCHITECTURES taches to the system bus and is idle to an unused section of memory. Al­ Design options that most of the time. the MMU attaches though the MMU is obviously useful directly to the CPU address bus and in a system that has multiple users speed up memory intercepts each CPU read or write running separate programs. it is just cycle. The CPU and MMU combine to as useful in a multitasking single-user management form a new functional unit. Several system. manufacturers have even moved the In a simple 68000 system that does · MMU onto the same silicon as the not have an MMU (figure 1). a typical he Motorola 68000 family CPU. in effect declaring that you can't memory read cycle begins when the of microprocessors has have one without the other. CPU asserts an address and address spawned a whole new The most important function pro­ strobe (AS). and the cycle ends when group of computer sys­ vided by all MMU designs is the abili­ the memory places data on the data tems. The original 68000. with its ty to relocate a program to another bus and activates the data transfer large. linear addressing range. makes part of memory according to a set of acknowledge (DTACK) line. Assuming itT a natural for single-user. personal pre-assigned translation rules. This that the memory is very fast. the cycle graphics workstations such as the relocation is done in hardware. with­ can be completed in eight transitions Macintosh. And multiuser systems out requiring any modification to the of the clock. or 500 nanoseconds for based on the 68020 can offer com­ application software. an 8-MHz CPU. puting power and speed that rival Before a system with an MMU runs In a 68000 system that has an MMU many minicomputers-often at a frac­ a program. the operating system con­ in series with the CPU's address bus tion of the cost. Not surprisingly, figures the MMU so that the program (figure 2). for each read cycle the CPU many of the design features for these can be moved to and run in an avail­ asserts a logical address and logical larger systems have evolved from well­ able section of memory. The program address strobe (LAS). (The address established minicomputer architec­ then begins execution. unaware of the and address strobe lines are now tures. Memory management units. or MMU's actions. For example. if a pro­ (continued) MMUs. are one example. The MMU gram has been compiled and linked Gregg Zehr is a senior design engineer at function came about as minicomputer with a starting location of 400 but that Altos Computer Systems (2 641 Orchard designers began to include special location is being used for some other Parkway, San Jose. CA 9 5121) . He received hardware to expand the amount of purpose. the operating system con­ his M.S.E.E. from the University of Illinois addressable memory. MMUs have figures the MMU hardware to convert and is interested in advanced computer now become a key feature in modern all the program's memory references architectures. computer architectures. In fact. several MMUs designed specifically for the 68000-family architecture are available (see table 1). THEORY OF OPERAT ION The MMU functions at a very low level in the computer system. Unlike a UART or other peripheral chip that at- NOVEMBER 1986 BYTE • 127 MEMORY MANAGEMENT UNITS prefaced with the term logical since these addresses are physically at­ translation. Second. the MMU must they are the absolute addresses from tached to the memory.) The memory monitor a wide input bus and drive the CPU's point of view.) The MMU ac­ again responds by putting data on the a wide output bus. Expect a single­ cepts the address and logical address data bus and asserting DfAC K. chip MMU for a 68000/680! 0-based strobe and then translates the logical But. as the saying goes. nothing is system to have at least 64 pins and address according to a set of transla­ free. There are two penalties for at­ an MMU for the 68020 to have over tion rules into a physical address. It taching the MMU in series with a !20 pins. Although the cqst of a then asserts a physical address and a bus-speed and pin count. First. each device is directly proportional to the physical address strobe (PAS). (The memory cycle must now be slowed number of pins on the package. in term ph!fsical is used to indicate that down while the MMU performs the most systems. fortunately. the cost of adding MMU hardware is less than developing a layer of software to per­ Table l: A summar!f of memor!f management units. form similar functions. Device Manufacturer Translation CPU Supported Since the MMU operates on each memory access. it is the perfect place 68451 Motorola Segmented 68008/00/1 0 to add special hardware support for 68905 Signetics Segmented/Paged 68000/1 0 certain operating system functions 68070 Signetics/Philips Segmented/Paged Integrated 68000 that are not strictly related to address 68910 Signetics Demand paged 68010 68920 Signetics Demand paged 68020 translation. The most important extras 68461 Motorola Demand paged 68010/20 are memory protection. cache. and 68851/MMB Motorola Demand paged 68010/20 virtual memory support hooks. For 68851 Motorola Demand paged 68010/20 example. by monitoring the three function code bits from the 68000. the MMU can divide the CPU's ad­ dress space into user- and supervisor­ level instruction and data areas. Thus. Address while you debug a program. the MMU can trap unauthorized (usually unin­ AS tentional) attempts to access reserved 68000 MEM system functions such as memory­ CPU Data mapped l/0 or interrupt vectors. In this case. the MMU hardware ensures DTACK that a bug in a program does not hang the system. PAGED TRANSLATION Block Diagram The translation rules that an MMU CPU sends address and AS to MEM uses can be classified as being either 1 paged or segmented. Paged systems usually divide memory into equal-size 2 pieces (pages). while segmented sys­ tems divide memory into variable-size State Diagram MEM returns data and DTACK to CPU pieces (segments). Both of these con­ cepts first appeared in mainframe and S1 S2 S3 S4 S5 S6 S7 so so minicomputer systems. In a paged translation (figure 3). the CLOCK MMU divides the logical addresses into two parts: the upper bits are called the segment number and the CPU - AS lower bits are called the page index. The page index. which determines the page size. is passed directly through ...._______.n the MMU unmodified. The segment MEM - DTACK number is used as an address mto a segment table. The data from the seg­ Timing ._______.n ment table is called the page address and forms the upper part of the Figure l: A 68000-based S!fStem without an MMU. physical address. Logically then. a memory location is described by a 128 BYTE • NOVEMBER 1986 MEMORY MANAGEMENT UNITS 13-bit offset into one of 2048 pages. ory. The descriptor also includes the segmented MMUs. occurs when vari­ Physically. memory is divided into 2 K length of the segment. The segment able-size segments leave holes in pages with a fixed size of 8K bytes . offset should be smaller than the physical memory that are too small . Although several popular 68000/ length; if it is not. the memory cycle for practical use. Several algorithms 68010 systems have been ' built by is aborted and an error is indicated. have been developed to simplify simply implementing the segment Assuming there is no error. the trans­ allocation in segmented systems and table with high-speed static RAM. lation is completed by arithmetically are described by Baer and Knowlton such an approach does not fit into adding the segment offset to the base (see the Bibliography). 32-bit 68020 designs very well. If the address. Physical memory can now be lowest 12 lines are used for the page divided into 2 56 variable-size s·eg­ DEMAND·PAGED TRANSLATION index. there are 20 lines left. This im­ ments. Each ?egment can be from I As CPU buses become wider. the plies that the segment table RAM to 64K bytes long. amount of memory required to store must hold I megabyte of page Although variable segment size page tables or segment descriptors numbers. allows memory allocation to fit mem­ becomes larger. This in turn increases Since pages have a fixed si�e. this ory requests better. it leads to another the cost of the MMU and the over­ type of translation is susceptible to in­ problem called external fragmenta­ head associated with task switching. ternal memory fragmentation. This tion. This problem. which is unique to (continued) means that some segments will likely include memory that is unused. For Logical Physical example. suppose that a program address address needs I K byte of storage for its data. LAS MMU PAS When run. the system assigns the pro­ _... gram one 4K-byte segment. The other 68000 MEM 3 K bytes become a memory fragment . that cannot be used by any other pro­ CPU Data gram. Most paged systems include at least two levels of translation and a DTAC K ""' smaller page size that reduces such - internal fragmentation. Translation A simple trick. however. can in­ Block Diagram crease the capabilities of this ap­ 2 proach. The segment table RAM can MMU checks authorization MMU translates logical address be wider than the segment number to provide additional control bits.