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KA650 CPU Module Technical Manual

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KA650 CPU Module Technical Manual KA6S0 CPU Module Technical Manual Order Number EK-KA650-UG.003 KA650 CPU Module Technical Manual Order Number EK-KA650-UG.003 digital equipment corporation maynard, massachusetts First Edition. December 1987 Second Edition. August 1988 Third Edition. March 1989 The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document. The software described in this document is furnished under a license and may be used or copied only in accordance with the terms of such license. No responsibility is assumed for the use or reliability of software on equipment that is not supplied by Digital Equipment Corporation or its affiliated companies. Copyright @1989 by Digital Equipment Corporation. All Rights Reserved. Printed in U.S.A. The followlIlg are trademarks of Digital Equipment Corporation: DEC MicroVAX II RSX DECmate MicroVAX3500 RT DECUS MicroVAX 3600 UNIBUS DECwriter PDP VAX DIBOL P/OS VAXstation LSI-ll Professional VMS MASSBUS Q-bus VT MicroPDP-ll Q22-bus VT100 MicroVAX Rainbow Work Processor MicroVAX I RSTS FCC NOTICE: The equipment described in this manual generates, uses, and may emit radio frequency energy. The equipment has been type tested and found to comply with the limits for a Class A computing device pursuant to Subpart J of Part 15 of FCC Rules, which are designed to provide reasonable protection against such radio frequency interference when operated in a commercial environment. Operation of this equipment in a residential area may cause interference, in which case the user at his own expense may be required to take measures to· correct the interference. Contents About This Manual xv 1 Overview 1.1 KA650 Central Processor Module. 1-1 1.2 Clock Functions . 1-5 1.3 Central Processing Unit. 1-5 1.4 Floating-Point Accelerator . 1-6 1.5 Cache Memory . 1-6 1.6 Memory Controller ...................... " ..... " . 1-6 1.7 MicroVAX System Support Functions ................. 1-7 1.8 Resident Firmware ......... "..................... 1-7 1.9 Q22-bus Interface. 1-8 1.10 MS650-AA Memory Modules . 1-8 1.11 MS650-BA Memory Modules . 1-8 2 Installation and Configuration 2.1 Installing the KA650 ............................. 2-1 2.2 Configuring the KA650 ........................... 2-4 2.3 KA650 Connectors ............................... 2-4 2.3.1 Console SLU Connector (J1) ..................... 2-4 2.3.2 Configuration and Display Connector (J2) ........... 2-5 2.3.3 Memory Expansion Connector (J3) ................ 2-7 2.4 H3600-SA CPU Cover Panel ....................... 2-8 2.5 KA630CNF Configuration Board .................... 2-9 2.6 Compatible System Enclosures ..................... 2-14 Contents-iii Contents-iv 3 Architecture 3.1 Central Processor ................................ 3-1 3.1.1 Processor State ............................... 3-1 3.1.1.1 General Purpose Registers ..................... 3-2 3.1.1.2 Processor Status Longword .................... 3-3 3.1.1.3 Internal Processor Registers ................... 3-4 3.1.2 Data Types ................................... 3-8 3.1.3 Instruction Set ................................ 3-9 3.1.4 Memory Management .......................... 3-10 3.1.4.1 Translation Buffer ........................... 3-11 3.1.4.2 Memory Management Control Registers .......... 3-11 3.1.5 Exceptions and Interrupts ....................... 3-12 3.1.5.1 Interrupts ................................. 3-12 3.1.5.2 Exceptions . .............................. 3-15 3.1.5.3 Information Saved on a Machine Check Exception .. 3-18 3.1.5.4 System Control Block ......................... 3-24 3.1.5.5 Hardware Detected Errors ..................... 3-26 3.1.5.6 Hardware Halt Procedure ..................... 3-27 3.1.6 System Identification ........................... 3-29 3.1.7 CPU References ............................... 3-31 3.1.7.1 Instruction-Stream Read References ............. 3-31 3.1.7.2 Data-Stream Read References .................. 3-31 3.1. 7.3 Write References ............................. 3-32 3.2 Floating-Point Accelerator. 3-32 3.2.1 Floating-Point Accelerator Instructions ............. 3-32 3.2.2 Floating-Point Accelerator Data Types .............. 3-32 3.3 Cache Memory .................................. 3-33 3.3.1 Cacheable References ........................... 3-33 3.3.2 First-Level Cache .............................. 3-34 3.3.2.1 First-Level Cache Organization ................. 3-34 3.3.2.2 First-Level Cache Address Translation ........... 3-36 3.3.2.3 First-Level Cache Data Block Allocation .......... 3-37 3.3.2.4 First-Level Cache Behavior on Writes ............ 3-38 3.3.2.5 Cache Disable Register ....................... 3-38 3.3.2.6 Memory System Error Register ................. 3-41 3.3.2.7 First-Level Cache Error Detection ............... 3-43 Contents-v 3.3.3 Second-Level Cache ............................ 3-43 3.3.3.1 Second-Level Cache Organization ............... 3-44 3.3.3.2 Second-Level Cache Address Translation .......... 3-46 3.3.3.3 Second-Level Cache Data Block Allocation ......... 3-47 3.3.3.4 Second-Level Cache Behavior on Writes .......... 3-48 3.3.3.5 Cache Control Register ....................... 3-48 3.3.3.6 Second-Level Cache Error Detection ............. 3-50 3.3.3.7 Second-Level Cache as Fast Memory ............. 3-51 3.4 Main Memory System ............................ 3-52 3.4.1 Main Memory Organization ...................... 3-55 3.4.2 Main Memory Addressing ....................... 3-55 3.4.3 Main Memory Behavior on Writes ................. 3-56 3.4.4 Main Memory Error Status Register ............... 3-56 3.4.5 Main Memory Control and Diagnostic Status Register .. 3-60 3.4.6 Main Memory Error Detection and Correction ........ 3-62 3.5 Console Serial Line ...................... ....... 3-64 3.5.1 Console Registers .............................. 3-64 3.5.1.1 Console Receiver Control/Status Register ......... 3-65 3.5.1.2 Console Receiver Data Buffer ................... 3-66 3.5.1.3 Console Transmitter Control/Status Register ....... 3-67 3.5.1.4 Console Transmitter Data Buffer . ....... 3-69 3.5.2 Break Response ............................... 3-69 3.5.3 Baud Rate ................................... 3-70 3.5.4 Console Interrupt Specifications ................... 3-70 3.6 Time-of-Year Clock and Timers ..................... 3-71 3.6.1 Time-of-Year Clock ............................. 3-71 3.6.2 Interval Timer ................................ 3-72 3.6.3 Programmable Timers .......................... 3-72 3.6.3.1 Timer Control Registers ....................... 3-73 3.6.3.2 Timer Interval Registers ...................... 3-75 3.6.3.3 Timer Next Interval Registers .................. 3-75 3.6.3.4 Timer Interrupt Vector Registers ................ 3-76 3.7 Boot and Diagnostic Facility ....................... 3-76 3.7.1 Boot and Diagnostic Register ..................... 3-77 3.7.2 Diagnostic LED Register ........................ 3-79 Contents-vi 3.7.3 ROM Memory ................................. 3-79 3.7.3.1 ROM Socket ................................ 3-79 3.7.3.2 ROM Address Space .......................... 3-80 3.7.3.3 Resident Firmware Operation .................. 3-80 3.7.4 Battery Backed-Up RAM ........................ 3-81 3.7.5 KA650 Initialization ............................ 3-81 3.7.5.1 Power-Up Initialization ....................... 3-82 3.7.5.2 Hardware Reset ............................. 3-82 3.7.5.3 110 Bus Initialization ......................... 3-82 3.7.5.4 110 Bus Reset Register ........................ 3-82 3.7.5.5 Processor Initialization ....................... 3-82 3.S Q22-bus Interface ................................ 3-83 3.S.1 Q22-bus to Main Memory Address Translation ....... 3-84 3.S.1.1 Q22-bus Map Registers ....................... 3-85 3.S.1.2 Accessing the Q22-bus Map Registers ............ 3-87 3.S.1.3 Q22-bus Map Cache .......................... 3-88 3.S.2 CDAL Bus to Q22-bus Address Translation .......... 3-90 3.S.3 Interprocessor Communication Register ............. 3-90 3.S.4 Q22-bus Interrupt Handling ..................... 3-92 3.S.5 Configuring the Q22-bus Map .................... 3-92 3.S.5.1 Q22-bus Map Base Address Register ............. 3-93 3.S.6 System Configuration Register .................... 3-93 3.8.7 DMA System Error Register ..................... 3-95 3.S.S Q22-bus Error Address Register .................. 3-9S 3.S.9 DMA Error Address Register ..................... 3-99 3.S.1O Error Handling ............................... 3-99 4 KASSO Firmware 4.1 KA650 Firmware Features. 4-1 4.1.1 Halt Entry, Exit, and Dispatch .................... 4-2 4.1.1.1 Halt Entry G Saving Processor State .............. 4-2 4.1.1.2 Halt Exit - Restoring Processor state. 4-3 4.1.1.3 Halt Dispatch. 4-4 4.1.1.4 External Halts. 4-5 Contents-vii 4.1.2 Power-Up .................................... 4-5 4.1.2.1 Initial Power-Up Test ......................... 4-6 4.1.2.2 Locating a Console Device ..................... 4-6 4.1.3 Mode Switch Set to Test ......................... 4-7 4.1.4 Mode Switch Set to Query ....................... 4-8 4.1.5 Mode Switch Set to Normal ...................... 4-9 4.1.6 LED Codes ................................... 4-10 4.2 Console Service. 4-11 4.2.1 Console Control Characters. 4-11 4.2.2 Console Command Syntax. 4-13 4.2.3 Console Command Keywords. .. .. .. .. 4-14 4.2.4 Console Command Qualifiers. .. .. .. .. 4-15 4.2.5 Command Address Specifiers. 4-15 4.2.6
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