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Xtensa Instruction Set Architecture (ISA) Reference Manual Iii Contents Xtensa® Instruction Set Architecture (ISA) Reference Manual For All Xtensa Processor Cores Tensilica, Inc. 3255-6 Scott Blvd. Santa Clara, CA 95054 (408) 986-8000 fax (408) 986-8919 www.tensilica.com © 2010 Tensilica, Inc. Printed in the United States of America All Rights Reserved This publication is provided “AS IS.” Tensilica, Inc. (hereafter “Tensilica”) does not make any warranty of any kind, either ex- pressed or implied, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Information in this document is provided solely to enable system and software developers to use Tensilica processors. Unless specifically set forth herein, there are no express or implied patent, copyright or any other intellectual property rights or licens- es granted hereunder to design or fabricate Tensilica integrated circuits or integrated circuits based on the information in this document. Tensilica does not warrant that the contents of this publication, whether individually or as one or more groups, meets your requirements or that the publication is error-free. This publication could include technical inaccuracies or typo- graphical errors. Changes may be made to the information herein, and these changes may be incorporated in new editions of this publication. Tensilica and Xtensa are registered trademarks of Tensilica, Inc. The following terms are trademarks of Tensilica, Inc.: FLIX, OSKit, Sea of Processors, TurboXim, Vectra, Xenergy, Xplorer, and XPRES. All other trademarks and registered trademarks are the property of their respective companies. Issue Date: 4/2010 RC-2010.1 Release PD-09-0801-10-01 Tensilica, Inc. 3255-6 Scott Blvd. Santa Clara, CA 95054 (408) 986-8000 fax (408) 986-8919 www.tensilica.com Contents Contents 1. Introduction ...................................................................................................................1 1.1 What Problem is Tensilica Solving?.............................................................................1 1.1.1 Adding Architectural Enhancements ..................................................................1 1.1.2 Creating Custom Processor Configurations ........................................................4 1.1.3 Mapping the Architecture into Hardware.............................................................4 1.1.4 Development and Verification Tools ...................................................................5 1.2 The Xtensa Instruction Set Architecture.......................................................................5 1.2.1 Configurability .................................................................................................7 1.2.2 Extensibility.....................................................................................................8 1.2.2.1 State Extensions .....................................................................................9 1.2.2.2 Register File Extensions ..........................................................................9 1.2.2.3 Instruction Extensions..............................................................................9 1.2.2.4 Coprocessor Extensions ..........................................................................9 1.2.3 Time-to-Market ................................................................................................9 1.2.4 Code Density ................................................................................................10 1.2.5 Low Implementation Cost ...............................................................................10 1.2.6 Low-Power.................................................................................................... 11 1.2.7 Performance ................................................................................................. 11 1.2.8 Pipelines.......................................................................................................12 1.3 The Xtensa Processor Generator..............................................................................13 1.3.1 Processor Configuration .................................................................................13 1.3.2 System-Specific Instructions—The TIE Language .............................................13 2. Notation.......................................................................................................................17 2.1 Bit and Byte Order ..................................................................................................17 2.2 Expressions ...........................................................................................................19 2.3 Unsigned Semantics ...............................................................................................20 2.4 Case .....................................................................................................................20 2.5 Statements.............................................................................................................21 2.6 Instruction Fields.....................................................................................................21 3. Core Architecture .........................................................................................................23 3.1 Overview of the Core Architecture ............................................................................23 3.2 Processor-Configuration Parameters.........................................................................23 3.3 Registers ...............................................................................................................24 3.3.1 General (AR) Registers...................................................................................24 3.3.2 Shifts and the Shift Amount Register (SAR) .......................................................25 3.3.3 Reading and Writing the Special Registers .......................................................26 3.4 Data Formats and Alignment ....................................................................................26 3.5 Memory .................................................................................................................27 3.5.1 Memory Addressing .......................................................................................27 3.5.2 Addressing Modes .........................................................................................28 3.5.3 Program Counter ...........................................................................................29 3.5.4 Instruction Fetch............................................................................................29 3.5.4.1 Little-Endian Fetch Semantics ................................................................29 Xtensa Instruction Set Architecture (ISA) Reference Manual iii Contents 3.5.4.2 Big-Endian Fetch Semantics...................................................................31 3.6 Reset.....................................................................................................................32 3.7 Exceptions and Interrupts ........................................................................................32 3.8 Instruction Summary ...............................................................................................33 3.8.1 Load Instructions ...........................................................................................33 3.8.2 Store Instructions...........................................................................................36 3.8.3 Memory Access Ordering ...............................................................................39 3.8.4 Jump and Call Instructions..............................................................................40 3.8.5 Conditional Branch Instructions .......................................................................40 3.8.6 Move Instructions ..........................................................................................42 3.8.7 Arithmetic Instructions ....................................................................................43 3.8.8 Bitwise Logical Instructions .............................................................................44 3.8.9 Shift Instructions ............................................................................................44 3.8.10 Processor Control Instructions.......................................................................45 4. Architectural Options....................................................................................................47 4.1 Overview of Options................................................................................................47 4.2 Core Architecture....................................................................................................50 4.3 Options for Additional Instructions.............................................................................53 4.3.1 Code Density Option......................................................................................53 4.3.1.1 Code Density Option Architectural Additions ............................................ 53 4.3.1.2 Branches..............................................................................................54 4.3.2 Loop Option ..................................................................................................54 4.3.2.1 Loop Option Architectural Additions.........................................................55 4.3.2.2 Restrictions on Loops ............................................................................55
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