Systems I: Computer Organization and Architecture

Lecture 8: Registers and Counters

Registers • A register is a group of flip-flops. – Each flip-flop stores one bit of data; n flip-flops are required to store n bits of data. – There are several different types of registers available commercially. – The simplest design is a register consisting only of flip- flops, with no other gates in the circuit. • Loading the register – transfer of new data into the register. • The flip-flops share a common clock pulse (frequently using a buffer to reduce power requirements). • Output could be sampled at any time. • Clearing the flip-flop (placing zeroes in all its bit) can be done through a special terminal on the flip-flop.

1 4-bit Register

I0 D Q A0 Clock C

I1 D Q A1 C

I D Q 2 A2 C

D Q A I3 3 C

Clear

Registers With Parallel Load

• The clock usually provides a steady stream of pulses which are applied to all flip-flops in the system. • A separate control system is needed to determine when to load a particular register. • The Register with Parallel Load has a separate load input. – When it is cleared, the register receives it output as input. – When it is set, it received the load input.

2 4-bit Register With Parallel Load

Load D Q A0 I0 C

D Q A1 C I1

D Q A2 I2 C

D Q A3 I3 C

Clock

Shift Registers

• A shift register is a register which can shift its data in one or both directions. • The simplest shift register simply connects the flip-flops to their respective neighbor with the clock controlling the operation. • If we wish to shift on some clock pulses but not others, we can inhibit the clock pulses on which we do not to shift.

3 4-Bit Shift Register

Serial Serial Output Input D Q D Q D Q D Q C C C C

Clock

Serial Transfer

• A digital system is operating in a serial mode when information is transferred and manipulated one bit at a time, with bits transferred out of the source register into the destination register. • This is different from parallel transfer where all the bits of a register are transferred at once. • Serial transfer of information from register A to register B is done with shift registers, where the serial output from register A serves as the serial input for register B.

4 Serial Transfer From Register A to Register B

SI Shift SO SI Shift SO Register A Register B CLK CLK

Clock Shift control

Clock

Shift control

CLK T1 T2 T3 T4

Serial Transfer – State Table

Timing Pulse Shift Register A Shift Register B Initial value 1 0 1 1 0 0 1 0

After T1 1 1 0 1 1 0 0 1

After T2 1 1 1 0 1 1 0 0

After T3 0 1 1 1 0 1 1 0

After T4 1 0 1 1 1 0 1 1

5 Serial Addition

• While operations are usually parallel because it is faster, serial operations require less equipment. • Serial addition can demonstrate this point, allowing us to perform addition with a single full adder and our two addends stored in a pair of shift registers, with the carry-out going into a D-type flip-flop (and going back in as the carry-in). • Initially, register A and the carry flip-flop are cleared to 0. • The augend is initially placed in register B and serial addition is used to place it into register A. • The sum is placed in shift register A, replacing the augend.

Serial Adder

Shift SI Shift SO control x CLK Register A S y FA z C

SI Serial SO input Shift Q Register B D

C

Clear

6 Redesigning the Serial Adder

• We will use a pair of shift registers whose outputs will be x and y respectively. These are corresponding bits of the addends. • S is the sum bit produced and a flip-flop will hold the carry bit as the flip-flop’s state Q. • We will implement it using a JK flip-flop

State Table for the Serial Adder

Present Next Flip-flop State Inputs State Output Inputs

Q(t) X Y Q(t+1) S JQ KQ 0 0 0 0 0 0 X 0 0 1 0 1 0 X 0 1 0 0 1 0 X 0 1 1 1 0 1 X 1 0 0 0 1 X 1 1 0 1 1 0 X 0 1 1 0 1 0 X 0 1 1 1 1 1 X 0

7 Karnaugh Map for JQ

xy Q 00 01 11 10

0 1

1 X X X X

JQ = xy

Karnaugh Map for KQ

xy Q 00 01 11 10

0 X X X X

1 1

JQ = x’y’ = (x + y)’

8 Karnaugh Map for S

xy Q 00 01 11 10

0 1 1

1 1 1

S = x Å y Å Q

Serial Adder

Shift SI SO = x control Shift CLK Register A

SI Serial SO = y input Shift Register B

J

C K

Clear

9 Bi-directional Shift Registers

• A shift register that can shift in one direction is called a unidirectional shift register. • A shift register that can shift in either direction is called a bi-directional shift register. • Some shift register also allow for the simple transfer of data.

General Shift Register • The most general shift register have all of these capabilities: – An input for clock pulses to synchronize all operations. – A shift-right operation and serial line input line associated with the shift-right. – A shift-left operation and serial line input line associated with the shift-left. – A parallel load operation and n input lines associated with the parallel transfer. – n parallel output lines. – A control state that leaves the information in the register unchanged even though the clock pulses are applied.

10 Function Table For General Shift Register

S1 S0 Register operation 0 0 No change

0 1 Shift Right (down) 1 0 Shift Left (up)

1 1 Parallel load

Bidirectional Shift Register With Parallel Load

S0 S0 S1 4X1 S1 0 MUX Serial Input 1 D Q A 2 0 I0 3 C

S0 S 4X1 1 MUX D Q 0 A1 1 C 2 I1 3

S 0 4X1 S1 D Q 0 MUX A2 1 C 2 I2 3

S 0 4X1 D Q A3 S1 0 MUX C 1 Serial Input 2 I3 3 Clock

11 Counters

• A register that goes through a prescribed sequences of states upon the application of an input pulse is called a counter. • The input pulse may be a clock pulse or may have some other origin. • A counter that goes through a binary sequence is called a binary counter. • An n-bit binary counter uses n flip-flops and can count from 0 to 2n-1.

Ripple Counters

• Counters are either ripple counters or synchronous counters. • In synchronous counters, all flip-flops receive the common clock pulse; therefore they change at the same time. • In ripple counters, the output of one flip-flop is used as a source for triggering others.

12 4-Bit Ripple Counter Using T-Type Flip-flop

A3 A2 A1 A0

R R R R T C T C T C T C

Logic-1 Reset

Count

4-Bit Ripple Counter Using JK-Type Flip-flop

A3 A2 A1 A0

R R R R J C K J C K J C K J C K

Logic-1 Reset

Count

13 4-Bit Ripple Counter Using D-Type Flip-flop

A3 A2 A1 A0

R R R R D C D C D C D C

Reset

Count

Binary Count Sequence

A 3 A 2 A 1 A 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0

14 BCD Ripple Counter

• A binary-coded decimal ripple counter will return to 0 after it reaches 9, this necessarily changes the logic

Q 8 Q 4 Q 2 Q 1

J C K J C K J C K J C K

Logic-1

Count

Three-Decade BCD Counter

Q 8 Q 4 Q 2 Q 1 Q 8 Q 4 Q 2 Q 1 Q 8 Q 4 Q 2 Q 1

BCD BCD BCD Count pulse Counter Counter Counter

102 digit 101 digit 100 digit

15 Binary Counters

• A counter is a register that goes through a predetermined sequence of states as input pulses are applied. • Almost all digital equipment will contain counters; they are used for counting the occurrences of a particular event and are useful in generating timing signals. • An n-bit counter uses n flip-flops and are have any value in the range 0 to 2n-1. • We notice in our sequences that the lowest significance bit is complemented with every count and the other bits are complemented from one count to the next when all the lower bits are set.

4-bit Synchronous Binary Counter

J Q A0 Count C Enable K

J Q A1 C K

J Q A2 C K

J Q A3 C Output K carry Clock

16 Up-Down Binary Counter

• A count-down binary counter will go through binary states in reverse order. • E.g., a 4-bit count-down binary counter will start at 0000, go to 1111, then 1110, and so on down to 0000. • As in regular counters, the least significant bit is always complemented. But higher bits are complemented only if the lower bits are all 0. • We can design a counter that can go in either direction, depending on the control inputs.

4-Bit Up-Down Binary Counter

Up A T 0 Down C

A T 1 C

A T 2 C

A T 3 C

Clock

17 BCD Counter

• BCD counters only go through states 0000 to 0001 up to 1001. • The pattern is as regular as binary counter, so we must go through the design process.

State Table for BCD Counter

Present State Next State Output Flip-flop Inputs

Q 8 Q 4 Q 2 Q 1 Q 8 Q 4 Q 2 Q 1 y TQ 8 TQ 4 TQ 2 TQ 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 0 1 0 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 1 1 0 1 0 X X X X 0 X X X X 1 0 1 1 X X X X 0 X X X X 1 1 0 0 X X X X 0 X X X X 1 1 0 1 X X X X 0 X X X X 1 1 1 0 X X X X 0 X X X X 1 1 1 1 X X X X 0 X X X X

18 Karnaugh Map For TQ8 Q2Q1

Q8Q4 00 01 11 10

00

01 1

11 X X X X

10 1 X X

TQ8 = Q8Q1 + Q4Q2Q1

Karnaugh Map For TQ4 Q2Q1 Q8Q4 00 01 11 10

00 1

01 1

11 X X X X

10 X X

TQ4 = Q2Q1

19 Karnaugh Map For TQ2 Q2Q1 Q8Q4 00 01 11 10

00 1 1

01 1 1

11 X X X X

10 X X

TQ2 = Q8’Q1

Karnaugh Map For TQ1 Q2Q1 Q8Q4 00 01 11 10

00 1 1 1 1

01 1 1 1 1

11 X X X X

10 1 1 X X

TQ1 = 1

20 4-Bit Counter With Parallel Load & Synchronous Clear • Counters often need to be preset with a pre- specified value before counting begins. • We also need the capability of clearing all bits simultaneously.

Function Table For 4-Bit Parallel Load Counter

Clock Clear Load Count Operation

• 0 0 0 No change

• 0 0 1 Increment count

• 0 1 X Load inputs I0 through I3 • 1 X X Clear outputs

21 4-bit counter with parallel Load load & synchronous clear

Count J Q A I 0 0 C K

I1 J Q A1 C K

J Q A I2 2 C K

J Q A I3 3 C K Clock Clear

Counters With Unused States

• An n-bit counter has 2n states, but there are occasions when we wish to use less than the total number of states available. • The unused states may be treated as “don’t- care” conditions (or assigned to specific next states). • Because outside interference may land the counter in these states, we must ensure that the counter can find its way back to a valid state.

22 State Table For Counter With Unused States Present State Next State Flip-flop Inputs

A B C A B C JA KA JB KB JC KC 0 0 0 0 0 1 0 X 0 X 1 X

0 0 1 0 1 0 0 X 1 X X 1

0 1 0 1 0 0 1 X X 1 0 X

0 1 1 1 0 0 X X X X X X

1 0 0 1 0 1 X 0 0 X 1 X

1 0 1 1 1 0 X 0 1 X X 1

1 1 0 0 0 0 X 1 X 1 0 X

1 1 1 0 0 0 X X X X X X

Karnaugh Maps for JA and KA BC 00 01 11 10 A 0 X 1

JA = B 1 X X X X

BC 00 01 11 10 A 0 X X X X

KA = B 1 X 1

23 Karnaugh Maps for JB and KB BC 00 01 11 10 A 0 1 X X

JB = C 1 1 X X

BC 00 01 11 10 A 0 X X X 1

KB = 1 1 X X X 1

Karnaugh Maps for JC and KC BC 00 01 11 10 A 0 1 X X

JC = B’ 1 1 X X

BC 00 01 11 10 A 0 X 1 X X

KC = 1 1 X 1 X X

24 State Diagram For Counter With Unused States

000 110

001 110

010 101

100 110

Logic Diagram For Counter With Unused States

A B C

C C C J K J K J K

Clock

Logic 1

25 Ring Counter

• Computers need timing signals that indicate the sequence in which certain operations will take place. • These can be generated by ring counters, circular shift registers with only one flip-flop set at any time. • The alternative to a 4-bit ring counter is a 2-bit counter that goes through 4 distinct states and uses a decoder.

Ring Counter Vs. Counter and Decoder

Shift T0 T1 T2 T3 right T0 T1 T2 T3 Ring counter (initial value = 1000) 2 x 4 decoder

Count enable 2-bit counter

Counter and decoder

26 Sequence of Timing Signals From the Ring Counter

CLK

T0

T1

T2

T3

Switch-tail Ring Counters

• Switch-tail ring counter can double the number of states that a ring counter can provide.

A B C E D D D D C C C C A’ B’ C’ E’

CLK

4-stage switch-tail ring counter

27 State Table For Switch-tail Counter

Flip-flop Outputs

Seq. Num. A B C E AND gate required for output 1 0 0 0 0 A’E’ 2 1 0 0 0 AB’ 3 1 1 0 0 BC’ 4 1 1 1 0 CE’ 5 1 1 1 1 AE 6 0 1 1 1 A’B 7 0 0 1 1 B’C 8 0 0 0 1 C’E

Johnson Counters

A B C E D D D D C C C C A’ B’ C’ E’

CLK

Seq. # 1 2 3 4 5 6 7 8

28