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Basics of CORDIC Goal Enhancement References

CORDIC - Basic Algorithm and Enhancements

K.Sridharan, IIT Madras

February 25, 2010 OR

x0 = cos φ[x − y tan φ] y 0 = cos φ[y + x tan φ]

Basics of CORDIC Goal Enhancement References Example Conventional CORDIC architecture

The CORDIC algorithm provides an iterative method of performing vector rotations by arbitrary angles using only shifts and adds.

Vector rotation transform: For rotating in a Cartesian plane by angle φ.

x0 = x cos φ − y sin φ y 0 = y cos φ + x sin φ Basics of CORDIC Goal Enhancement References Example Conventional CORDIC architecture

The CORDIC algorithm provides an iterative method of performing vector rotations by arbitrary angles using only shifts and adds.

Vector rotation transform: For rotating in a Cartesian plane by angle φ.

x0 = x cos φ − y sin φ y 0 = y cos φ + x sin φ

OR

x0 = cos φ[x − y tan φ] y 0 = cos φ[y + x tan φ] Basics of CORDIC Goal Enhancement References Example Conventional CORDIC architecture

If rotation angles are selected such that tan φ = ±2−i , then

−i Xi+1 = Ki (Xi − Yi · di · 2 ) −i Yi+1 = Ki (Yi + Xi · di · 2 ) −1 −i Zi+1 = Zi − di · tan (2 ) where

−1 −i 1 Ki = cos(tan (2 )) = √ (1) 1 + 2−2i

The scale factor Ki can be accumulated and the vector is scaled by

Y p −2i An = 1 + 2 n Basics of CORDIC Goal Enhancement References Example Conventional CORDIC architecture Polar (R, θ) to Rectangular (X,Y) transformation:

+Y

Rotation by 65◦

θ = 65◦ +X Basics of CORDIC Goal Enhancement References Example Conventional CORDIC architecture Polar (R, θ) to Rectangular (X,Y) transformation:

+Y Initialize

X0 = R

Y0 = 0

Z0 = θ

+X Basics of CORDIC Goal Enhancement References Example Conventional CORDIC architecture Polar (R, θ) to Rectangular (X,Y) transformation:

Rotate by tan−1(20) = 45◦ +Y

X1 = X0 − Y0

Y1 = Y0 + X0 45◦ −1 0 Z1 = Z0 − tan (2 ) +X Basics of CORDIC Goal Enhancement References Example Conventional CORDIC architecture Polar (R, θ) to Rectangular (X,Y) transformation:

Rotate by tan−1(2−1) = 26.5◦ +Y Y 26.5◦ X = X − 1 2 1 2 X Y = Y + 1 2 1 2 −1 −1 +X Z2 = Z1 − tan (2 ) Basics of CORDIC Goal Enhancement References Example Conventional CORDIC architecture Polar (R, θ) to Rectangular (X,Y) transformation:

Rotate by tan−1(2−2) = 14◦ +Y

14◦ Y X = X + 2 3 2 4 X Y = Y − 2 3 2 4 +X −1 −2 = Z2 + tan (2 ) Basics of CORDIC Goal Enhancement References Example Conventional CORDIC architecture

X0 0 0 MUX −Xi+1 X −X0 MUX 1 register 0 out 1 sel + MUX X0[MSB] sel / scalar Xi+1 1 barrel sel mode shifter +/− sel1 sub sel

0 Y0 MUX register 1 + sel adder/ Yout reset¯ barrel subtractor scaler Zi[MSB] shifter +/− 180 0 sub 0 Yi[MSB] MUX sel MUX 1 −180 1 sel sel mode + Z Z0[MSB] subtractor 0 − 0 0 MUX register MUX 1 + sub 1 sel Zi+1 sel sel adder/ 0 Zout counter subtractor MUX |Z | < 90 ROM +/− 1 0 sel0 3 comparator − Basic CORDIC subtractor Zi+1[MSB] + mode 180 sel 0 −180 MUX 1 Basics of CORDIC Goal Enhancement References Example Conventional CORDIC architecture

X0 0 0 MUX −Xi+1 X −X0 MUX 1 register 0 out 1 sel + MUX X0[MSB] sel adder/ scalar Xi+1 1 barrel subtractor sel mode shifter +/− sel1 sub sel

0 Y0 MUX register 1 + sel adder/ Yout reset¯ barrel subtractor scaler Zi[MSB] shifter +/− 180 0 sub 0 Yi[MSB] MUX sel MUX 1 −180 1 sel sel mode + Z Z0[MSB] subtractor 0 − 0 0 MUX register MUX 1 + sub 1 sel Zi+1 sel sel adder/ 0 Zout counter subtractor MUX |Z | < 90 ROM +/− 1 0 sel0 3 comparator − Basic CORDIC subtractor Zi+1[MSB] + mode 180 sel 0 −180 MUX 1 Basics of CORDIC Goal Enhancement References Bottlenecks for area

Reduce area consumption without affecting the performance in terms of accuracy and number of iterations. Basics of CORDIC Goal Enhancement References Bottlenecks for area

ROM : The size of the ROM is 2dlog2(no. of iterations)e. Barrel shifters. Range is limited to |Z| <= 99◦. Multiplexers (both at input and output) are required to extend the range. Basics of CORDIC Goal Enhancement References Features Iterative equations Convergence Architecture

1 Completely eliminates barrel-shifters. 2 Represents all the angles in [−180◦, 180◦] using combinations of two signed elementary angles, tan−12−1 and tan−12−3.

OR

−1 −1 −1 −3 Z = k0 · tan (2 ) + k1 tan (2 ) Basics of CORDIC Goal Enhancement References Features Iterative equations Convergence Architecture

Either

sgn(k0) −1 X = K1 · (X − (−1) · Y .2 ) sgn(k0) −1 Y = K1 · (Y + (−1) · X .2 )

Or

X = X − (−1)sgn(k1) · Y · 2−3 Y = Y + (−1)sgn(k1) · X · 2−3 Basics of CORDIC Goal Enhancement References Features Iterative equations Convergence Architecture

Either

sgn(k0) −1 X = K1 · (X − (−1) · Y .2 ) sgn(k0) −1 Y = K1 · (Y + (−1) · X .2 )

Or

X = X − (−1)sgn(k1) · Y · 2−3 Y = Y + (−1)sgn(k1) · X · 2−3 Basics of CORDIC Goal Enhancement References Features Iterative equations Convergence Architecture

max(|k0| + |k1|) = 13 for 170◦ = 4 · tan−1(2−1) + 9 · tan−1(2−3) and 177◦ = 8 · tan−1(2−1) − 5 · tan−1(2−3) Found using C program. Basics of CORDIC Goal Enhancement References Features Iterative equations Convergence Architecture

max(|k0| + |k1|) = 13 for 170◦ = 4 · tan−1(2−1) + 9 · tan−1(2−3) and 177◦ = 8 · tan−1(2−1) − 5 · tan−1(2−3) Found using C program. Basics of CORDIC Goal Enhancement References Features Iterative equations Convergence Architecture

9 8 5 4 3 0 sgn(k1) |k1| sgn(k0) |k0| Zin ROM 360 X 10 10 sgn(k ) 4 4 0|k | |k | sgn(k1) 1 0 m state stop−bit machine

Y 2 + 0 sel accumulator scaler 0M3 X Yi MUX +/− sub MUX 8 1M0 1 sel

0 sel MUX 1M2

X sub 2 + 0 sel accumulator scaler 0 sel Y X MUX +/− MUX 8 1M1 1M4 Basics of CORDIC Goal Enhancement References

1 J. Volder, The CORDIC trigonometric computing technique, IRE Transactions on Electronic Computers, Vol. EC-8, 1959, pp. 330-334. 2 J.S. Walther, A unified algorithm for elementary functions, Proceedings of 38th Spring Joint Computer Conference, 1971, pp. 379-385 3 R. Andraka, A survey of CORDIC algorithms for FPGA-based computers, Proceedings of ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998, pp. 191-200 4 Leena Vachhani, K. Sridharan, P.K. Meher, Efficient CORDIC algorithms and architectures for low area and high throughput implementation, IEEE Transactions on Circuits and Systems - Part II:Express Briefs, Vol. 56, No. 1, January 2009, pp. 61-65