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Designing Digital Sequential Logic Circuits © N Erik Jonsson School of Engineering and The University of Texas at Dallas Computer Science Take-Home Exercise • Assume you want the counter below to count mod-6 backward. That is, it would count 0-5-4-3-2-1-0, etc. Assume it is reset on start- up, and design the wiring to make the counter count properly. • Major hint that was supplied: Remember the K-map method will work for ANY counter. Note: x is the most significant bit, z the least significant. z y x 1 Lecture #9: Designing Digital Sequential Logic Circuits © N. B. Dodge 9/15 Erik Jonsson School of Engineering and The University of Texas at Dallas Computer Science Designing Sequential Logic • Last lecture demonstrated the design of two simple counters (a third counter was a homework problem). • Today’s exercise: Three additional designs: – A modulo-10 binary counter – A timer or signal generator – A “sequential” multiplexer • Note that all the designs utilize counters. 5 Lecture #9: Designing Digital Sequential Logic Circuits © N. B. Dodge 9/15 Erik Jonsson School of Engineering and The University of Texas at Dallas Computer Science Design 1: A Decimal Counter • A “decimal counter” is one that counts modulo ten. • This is a realistic design, since in many electronic devices or appliances, it is often necessary to count in tens. • We will design only a single 0-9 counter, recognizing that we can count to 99 or 999 by simply adding more counter digits. • We will need a 4-bit counter (counting up to 9—1001—requires 4 bits). • The counter must: – Count from zero to nine and reset on the tenth clock pulse. – Count synchronously (as usual), that is, in parallel, not ripple. – Have the four counter bits available as outputs, so that they might be decoded to indicate various counts, from 0 to 9. 6 Lecture #9: Designing Digital Sequential Logic Circuits © N. B. Dodge 9/15 Erik Jonsson School of Engineering and The University of Texas at Dallas Computer Science First Step: A Four-Bit (Modulo 16) Counter • In general, the best way to design any modulo-m counter (m not a power of 2) is to start with the smallest 2n counter that will count up to m. • In our case, we need a 4-bit counter (as mentioned on the previous page), as it takes 4 bits to count to 9. • Thus, we will start with a four-bit, modulo-16 counter. Once we have it, we can modify it to count modulo 10. • So as our first step, we will design that modulo-16 counter. It turns out that this design will also help us in the other two design exercises in this lecture. 7 Lecture #9: Designing Digital Sequential Logic Circuits © N. B. Dodge 9/15 Erik Jonsson School of Engineering and The University of Texas at Dallas Computer Science Modulo-16 Counter 1 LSB 2nd LSB 2nd MSB MSB Reset Clock • We are building a parallel or synchronous counter. Therefore, the clock is connected to all four stages of the counter as shown above. • We remember that for any 2n counter, the lowest stage is always connected to logic 1. Now we only have to consider the other three stages. • We will use the “truth table method” to find T for the last three stages of the counter. 8 Lecture #9: Designing Digital Sequential Logic Circuits © N. B. Dodge 9/15 Erik Jonsson School of Engineering and The University of Texas at Dallas Computer Science Truth-Table/K-Map Approach to Counter Design • Using this approach, we will make a truth table for the T inputs to each counter flip-flop versus the count. • We remember that for a T-FF, if the T input is 1, the counter stage will change states on the clock pulse. • However, if the T input is 0, when the input clock ticks, the flip-flop will not change states. • We normally make a composite truth table for all necessary stages (in this case, three), but then consider the counter stages, or flip-flops, one at a time to define the T for each count. Then we transfer this information to the Karnaugh map. 9 Lecture #9: Designing Digital Sequential Logic Circuits © N. B. Dodge 9/15 Erik Jonsson School of Engineering and The University of Texas at Dallas Computer Science Truth Table for Bit y T-Input Count T-Input y yNEXT • For a 4-bit counter, the truth tables wxyz will have 16 possibilities (i.e., the 16 0 0 0 0 0 0 0 counts of the counter). 0 0 0 1 1 0 1 • To eliminate calling the counter bits 0 0 1 0 0 1 1 “LSB, second LSB,” etc., we call the 0 0 1 1 1 1 0 counter outputs w, x, y, and z (where 0 1 0 0 0 0 0 w = MSB). 0 1 0 1 1 0 1 • Omitting z as noted, we examine the 0 1 1 0 0 1 1 Q output of y (shaded green), along 0 1 1 1 1 1 0 with its next output state (brackets). 1 0 0 0 0 0 0 These are then listed as “y” and 1 0 0 1 1 0 1 yNEXT” as before. 1 0 1 0 0 1 1 • As in the previous lecture, comparing 1 0 1 1 1 1 0 the y values tell us what the T-input 1 1 0 0 0 0 0 should be. If y = yNEXT, T = 0, but if 1 1 0 1 1 0 1 y ≠ yNEXT, T = 1. 1 1 1 0 0 1 1 1 1 1 1Etc. 1 1 0 10 Lecture #9: Designing Digital Sequential Logic Circuits © N. B. Dodge 9/15 Erik Jonsson School of Engineering and The University of Texas at Dallas Computer Science Karnaugh Map for Bit y T-Input • As usual, we plot the 1’s from the truth table on a Karnaugh map, just as we did for the modulo-8 and yz modulo-6 counters in the last lecture. 00 01 11 10 • From the K-Map, a simplifying prime 1 1 implicant is identified. 00 • Clearly, the implicant does not 01 1 1 depend on w, x, or y. wx 11 1 1 • Therefore we can define the Boolean expression or term for the T-input to 10 1 1 the counter bit y as: Ty = z • Note that this is just the T input we get using our “rule.” 11 Lecture #9: Designing Digital Sequential Logic Circuits © N. B. Dodge 9/15 Erik Jonsson School of Engineering and The University of Texas at Dallas Computer Science Bit y T Input Connected Tzy = 1 z y x w Reset Clock • Our timer counter circuit now looks as shown above, with the new w-x-y-z labels, and with the y-input connected. 12 Lecture #9: Designing Digital Sequential Logic Circuits © N. B. Dodge 9/15 Erik Jonsson School of Engineering and The University of Texas at Dallas Computer Science Truth Table for Bit x T-Input • The truth table is made up for Count T-Input x xNEXT w x y z bit x as we did for bit y, 0 0 0 0 0 0 0 comparing the value of x for 0 0 0 1 0 0 0 each count to the value of x in 0 0 1 0 0 0 0 0 0 1 1 1 0 1 the next count. 0 1 0 0 0 1 1 • These are then plotted in the 0 1 0 1 0 1 1 0 1 1 0 0 1 1 right two columns. 0 1 1 1 1 1 0 • As before, When x and x 1 0 0 0 0 0 0 NEXT 1 0 0 1 0 0 0 are equal, T is 0. When they 1 0 1 0 0 0 0 are different, T is 1. 1 0 1 1 1 0 1 1 1 0 0 0 1 1 • Note that there are fewer 1’s 1 1 0 1 0 1 1 on the table in the T-input 1 1 1 0 0 1 1 1 1 1 1 1 1 0 column because the 2nd MSB, Etc. x, will toggle fewer times. 13 Lecture #9: Designing Digital Sequential Logic Circuits © N. B. Dodge 9/15 Erik Jonsson School of Engineering and The University of Texas at Dallas Computer Science Karnaugh Map for Bit x T-Input • The bit x T-input K-map is shown. yz • As before, there is an obvious 00 01 11 10 simplifying Boolean expression for this T-input. 00 1 • We can see that outputs w and 01 1 wx x do not affect the switching of 11 1 2nd MSB. 10 1 • Given the Karnaugh map shown, what is the Boolean expression for Tx. Tx = yz 14 Lecture #9: Designing Digital Sequential Logic Circuits © N. B. Dodge 9/15 Erik Jonsson School of Engineering and The University of Texas at Dallas Computer Science Bit x T-Input Connected Tx = yz 1 z Tzy = y x w Reset Clock • Note that the inputs for x, y, and z are exactly the same result that we got for our three T inputs on our modulo-8 counter, just as we would expect. • We now follow our “longer procedure” to define the bit w T-input. 15 Lecture #9: Designing Digital Sequential Logic Circuits © N. B. Dodge 9/15 Erik Jonsson School of Engineering and The University of Texas at Dallas Computer Science Bit w T-Input Truth Table Count T-Input w wNEXT wxyz • We proceed in our analysis as 0 0 0 0 0 0 0 before.
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