ENGR 303 – Introduction to Logic Design Lecture 20

Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College Outline for Todays Lecture

• Computer microarchitecture overview • Single Cycle Computer • Arithmetic Logic Unit (ALU)

ENGR 303 <2> Microarchitecture

• Computer architecture consists of a high level description of the hardware and instructions • Instruction set architecture (ISA) is the collection of instructions that specifies the operations of the hardware • For this course we will study a Single Cycle Computer1 which represents the basic microarchitecture and ISA of a computer CPU 1 Logic and Computer Design Fundamentals, Fifth Edition-2015, Chapter 8, pgs 433- 466, by Morris Mano, Charles Kime, and Tom Martin ENGR 303 <3> Single Cycle Computer

• A Single Cycle Computer , as its name implies, completes an instruction cycle in one clock cycle • An instruction cycle is the process by which a computer retrieves (fetch) a program instruction from memory, determines the actions (decode) to be taken, and carriers out the actions (execute) fetch -> decode -> execute

ENGR 303 <4> Block Diagram for Single-Cycle Computer

A set of registers

Program Address and data counter buses

Control interface

Arithmetic Logic Unit memory Figure 8-15, Mano1 ENGR 303 <5> Data & Control Paths

• A Single Cycle Computer architecture is divided into a data and control paths • The datapath has three components – Set of registers – Microoperations performed on the data stored in the registers, and – Control interface • The control path provides the signals that control operations performance in the datapath …based on the program instructions

ENGR 303 <6> Datapath • The datapath employs a set of registers that hold data with a Arithmetic Logic Unit (ALU) that performs operations on the data • Basic operations include add, subtract, increment, transfer…as well as logic functions • The results of the operation are stored back into a destination register • In the Single Cycle Computer the data transfer from the source register, through the ALU, to the destination register is done in one clock cycle ENGR 303 <7> Block Diagram of Datapath

A – address bus B – data bus Register File C – carry flag (Four n-bit registers) D – result bus F – external data G – operation H – shifted data N – negative flag V – overflow flag Function Unit (ALU & Shifter) Z – zero flag

Figure 8-1, Mano1 ENGR 303 <8> Example R1 <- R2+ R3 1. A select, to place contents of R2 onto A bus 2. B select, to place contents of R3 input MUX B and then onto B bus 3. G select, to declare the arithmetic operation A + B 4. MF select, place ALU output on MUX F out 5. MD select, to place MUX F out onto D bus 6. Destination select, to select R1 7. Load enable, enable R1 to load the result

ENGR 303 <9> Arithmetic Logic Unit (ALU) • The ALU is a combinatorial adder circuit that performs basic arithmetic operations on A & B • A number of selection lines (S0, S1) determine the operation

Figure 8-3, Table 8-1, Mano1 ENGR 303 <10> ALU Design

Yi = BiS0 + BiS1

Table 8-1, Figure 8-4 Mano1 ENGR 303 <11> ALU Arithmetic Circuit

Yi = BiS0 + BiS1

Figure 8-5 Mano1 ENGR 303 <12> ALU Logic Circuit • Logic to support bitwise operations; AND, OR, XOR, NOT

Figure 8-6 Mano1 ENGR 303 <13> One Stage of ALU

• ALU formed by arithmetic and logic circuits

Figure 8-5

Figure 8-6

S2 = 0 -> arithmetic operation Figure 8-7 Mano1 S2 = 1 -> logic operation ENGR 303 <14> ALU Function Select Table • The resulting function select (FS) operations

FS(3:0) = S2 , S1, S0, Cin

Table 8-2, Table 8-1, Mano1 ENGR 303 <15> Lab 10 – ALU Design • Implement the ALU sub-elements of the Function unit • Demonstrate ALU on DE2 board – Input B: Toggle Switches 15 thru 8 – Input A: Toggle Switches 7 thru 0

– Output G: Red LEDs 7 thru 0

– These next 3 are the OpSelect group: – S1: Key Switch 3 – S0: Key Switch 2 – Cin: Key Switch 1

– Cout: Red LED 17 – V: Red LED 16 ENGR 303 <16> The Function Unit

G Select = FS(3:0) = S2 , S1, S0, Cin H Select = FS(1:0) = S1, S0 MF Select = S2 & S1

Figure 8-1, Mano1 ENGR 303 <17> The Shifter • The shifter is the second element of the Functional unit and necessary for multiple operations • A combinational shifter can transfer data from the source register to destination register on one clock • A combinational shifter can be implemented with multiplexers

ENGR 303 <18> The Shifter Circuit

H Select S = 00 -> B passes unchanged S = 01 -> right shift Figure 8-8, Mano1 S = 10 -> left shift ENGR 303 S = 11 -> don’t care <19> Lab 11 – Functional Unit Design • Implement the basic sub-elements of the function unit – 8-bit 2 to1 Mux – ALU Stage – Shifter – Zero Detect Module • Demonstrate Functional Unit on DE2 board – Shown conditional output bits (V, C, N, Z) for fixed A & B value with a couple FS settings

ENGR 303 <20>