NRAM: High Performance, Highly Reliable Emerging Memory Sheyang Ning1,2, Tomoko Ogura Iwasaki1, Darlene Viviani2, Henry Huang2, Monte Manning2, Thomas Rueckes2, Ken Takeuchi1

1Chuo University 2 Nantero Inc. Flash Memory Summit 2016 Santa Clara, CA 1 Outline l Introduction of NRAM l Single NRAM cell and cell array measurement setup l NRAM characteristics l DC-IV curve l Set and reset program characteristics l Large on/off ratio l High temperature program l High endurance l Conclusion

Flash Memory Summit 2016 Santa Clara, CA 2 Introduction of NRAM

Performance

DRAM Nano-RAM, Carbon nanotube NRAM based resistive memory

NAND flash

Flash Memory Summit 2016 Santa Clara, CA 3 Compare with Conventional Memories

= good = bad DRAM NAND flash NRAM Performance 20 ns pulse [1] Scalability Single cell 15 nm [2] Endurance Single cell 1012 [3] Non-volatile 1000 years@ 85ºC [2]

[1]. S. Ning et al., IEEE Symp. on VLSI Technology, Jun. 2014, pp. 96–97. [2]. Nantero Presentation for ITRS ERD/ERM, International Technology Roadmap for Flash Memory Summit 2016 Semiconductors (ITRS), 2013. Santa Clara, CA [3]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837–2844, Sept. 2015. 4 Compare with Emerging Memories

ReRAM [1] PRAM [2] NRAM [3]

Al O Carbon Material x y Ge2Sb2Te5 nanotube (CNT) Resistive Tunneling switching on Filament Phase current size change read between CNTs Endurance 108 109 1012 Current High High Low

[1]. S. Ning et al., Solid-State Electronics, vol. 103, pp. 64–72, Jan., 2015. [2]. H. Y. Cheng et al., IEEE Int. Electron Devices Meeting, 2013, pp. 30.6.1–30.6.4. [3]. S. Ning et al., Symp. on VLSI Tech., 2014, pp. 96–97. Flash Memory Summit 2016 [4]. S. Ning et al., Ext. Abstr. Solid State Devices and Materials (SSDM), Oct. 2015, pp. 1198-1199. Santa Clara, CA 5 Physical Mechanism

≈ R cell 800 kΩ

Small distance

R cell ≈1 GΩ

Large distance

Flash Memory Summit 2016 [1]. S. Ning et al., in VLSI Symp. Tech. Dig., Jun. 2014, pp. 120–121. Santa Clara, CA [2]. Nantero presentation, Int. Tech. Roadmap for Semiconductors (ITRS), 2013. 6 Physical Mechanism

Set: attraction force Reset: repulsive force

+

− Electrical Heat caused induction phonon vibration

Flash Memory Summit 2016 [1]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837–2844, Sept. 2015. Santa Clara, CA 7 Outline

l Introduction of NRAM l Single NRAM cell and cell array measurement setup l NRAM characteristics l DC-IV curve l Set and reset program characteristics l Large on/off ratio l High temperature program l High endurance l Conclusion Flash Memory Summit 2016 Santa Clara, CA 8 Single NRAM Cell and Cell Array Test

140 nm NRAM single cell 116 nm, 4 Mbits NRAM cell array

V d BL0 SL0 BLN SLN …… NRAM WL cell

NRAM cell V g BL SL Set voltage +V 0 V Oscilloscope Set NRAM testchip Reset voltage 0 V +VReset

[1]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837–2844, Sept. 2015. Flash Memory Summit 2016 [2]. G. Rosendale et al., Proceedings of the European Solid-State Circuits Research Conference Santa Clara, CA (ESSCIRC), Sept. 2010, pp. 478–481. 9 Outline

l Introduction of NRAM l Single NRAM cell and cell array measurement setup l NRAM characteristics l DC-IV curve l Set and reset program characteristics l Large on/off ratio l High temperature program l High endurance l Conclusion

Flash Memory Summit 2016 Santa Clara, CA 10 DC-IV Curve Single cell bi-polar program 100 Current vibration due to long term voltage stress on CNTs 10 1 Same cell, reset curve

A) 15

µ −1

( 10 Trigger A) d Reset 10 I Set voltage −2 µ 10 ( 5 d

−3 Butterfly I 10 curve 0 10−4 0 1 2 3 -3 -2 -1 0 1 2 3 Vd (V) Vd (V) Flash Memory Summit 2016 [1]. S. Ning et al., IEEE Symp. on VLSI Technology, Jun. 2014, pp. 96–97. Santa Clara, CA 11 Low Program Current

Single cell DC I = 5 µA, Single cell AC Ipeak < 20 µA compliance 20 30 µA, and 100 µA (V) Voltage

10−2 µ A) 0

10−4 100 µA Reset -20 30 µA 0.57pJ 5 µA Current ( -40 10−6 0 50 100 150 Time (ns) −8 40 10 (V) Voltage

Current (A) Current Set 0.72pJ Reset µ A) 20 10−10 Set 0 −12 10 Current ( -20 Voltage 0 50 100 150 Time (ns) Flash Memory Summit 2016 [1]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837–2844, Sept. 2015. Santa Clara, CA [2]. S. Ning et al., IEEE Symp. on VLSI Technology, Jun. 2014, pp. 96–97. 12

Santa Clara, CA Clara, Santa Summit 2016 Memory Flash l

voltage and current is driven by Reset both Cell array measurement, measurement, Cell array BL = 0 V Reset Characteristic Reset [1]. S. Ning SL= WL= V program et et al ., Ext. V gate Abstr . Solidand(SSDM), Materials Devices State

Reset BER (a.u.) 2 1 0 0.6 0.8

1 1 0.8 Oct. 2015, Oct.pp. 2015, 1198-1199. SL from 0 to 1 WL=0.4 0.6 0.4 a.u .,

a.u 13 .

Set and Reset Voltages l Use incremental pulse programing on single cell l Three randomly chosen NRAM cells Reset voltage Set voltage (absolute value) Reset Set 1 100% 100% cell 1 cell 2 80% 80% cell 3 0.81 cell 1 60% cell 2 60% 0.60.8 cell 3 40% 40% 0.6 0.4 20% 20% Program voltages (a.u.) 0.4 6 7 8 9 10 11 12 Program voltages (a.u.)Program 10 10 10 10 10 10 10 0.2 0% 0% Cumulative program Cumulative success Write cycles program Cumulative success Set voltage (V) 106 107 108 109 101010111012 Reset voltage (V) Write cycles Flash Memory Summit 2016 [1]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837–2844, Sept. 2015. Santa Clara, CA 14 Large On/Off Ratio Read at 1 V l Single cell measurement 109 > 100 times on/off ratio Resistance ) 108 ≈ 1.3×107 Ω

Possible for multi-level cell (MLC) Ω 107 106 105 Resistance ( Resistance ≈ 105 Ω 104 0 50 100 150 200 Read cycles

Flash Memory Summit 2016 [1]. S. Ning et al., IEEE Symp. on VLSI Technology, Jun. 2014, pp. 96–97. Santa Clara, CA 15 High Temperature Program l Single cell measurement, stable program voltage at different temperatures

25℃ 25℃ 85℃ 85℃ 125℃ 125℃

Reset Set Set failure rate (a.u., log scale) (a.u., rate Set failure Reset failure rate (a.u., log scale) log (a.u., rate failure Reset 0 0.5 1 0 0.5 1 Reset voltage (a. u.) Set voltage (a.u.) Flash Memory Summit 2016 Santa Clara, CA [1]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837–2844, Sept. 2015. 16 High Endurance Single cell Cell array 8 10 5 Reset BER 107 4 Set BER ) HRS ≥ 1.25MΩ Ω 3 106 2 105

Resistance Resistance ( 1 Program BER (a.u.) BER Program LRS ≤ 200kΩ 104 0 106 107 108 109 1010 10111012 103 104 105 106 107 108 Write cycles Write cycles

Flash Memory Summit 2016 [1]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837–2844, Sept. 2015. Santa Clara, CA [2]. S. Ning et al., Ext. Abstr. Solid State Devices and Materials (SSDM), Oct. 2015, pp. 1198-1199. 17 High Endurance l Cell array does not wear-out after 108 write cycles 3 Set BER after 103 write cycles Reset BER after 10 write cycles 8 Set BER after 108 write cycles Reset BER after 10 write cycles Set voltage Reset voltage 1 1 1 1 SLReset voltage Set .) 0.8 0.9 0.8 BL voltage (

.) 0.9 a.u

a.u 0.6 0.8 0.6

BER BER ( 0.8 0.4 0.4

BER ( BER 0.7 ( a.u Reset

0.7 a.u Set 0.2 0.6 0.2 .) .) 0 0.5 0 0.6 1 2 3 4 5 1 2 3 4 5 Verify-set pulses Verify-reset pulses

Flash Memory Summit 2016 [1]. S. Ning et al., Japanese Journal of Applied Physics (JJAP), vol. 55, no. 4S, 2016. Santa Clara, CA [2]. S. Ning et al., Ext. Abstr. Solid State Devices and Materials (SSDM), Oct. 2015, pp. 1198-1199. 18 Outline

l Introduction of NRAM l Single NRAM cell and cell array measurement setup l NRAM characteristics l DC-IV curve l Set and reset program characteristics l Large on/off ratio l High temperature program l High endurance l Conclusion

Flash Memory Summit 2016 Santa Clara, CA 19 Conclusion

l NRAM is an emerging nonvolatile memory cell which has performance between DRAM and NAND flash. l Compared with other emerging nonvolatile memories, NRAM has competitive characteristics, including, lower program current, large on/off ratio, large endurance, high temperature stability and long retention time.

Flash Memory Summit 2016 Santa Clara, CA 20