MRAM Technology and Market Trends

Total Page:16

File Type:pdf, Size:1020Kb

MRAM Technology and Market Trends MRAM Technology and Market Trends Simone Bertolazzi, Ph.D. Technology and Market Analyst, Yole Développement 1 Yole’s Global Activity 2 Yole Développement - Fields of Expertise Life Sciences Semiconductor Semiconductor & Healthcare & Software & Software o Microfluidics o Package, Assembly & Substrates o BioMEMS & Medical Microsystems o Semiconductor Manufacturing o Inkjet and accurate dispensing o Memory o Solid-State Medical Imaging & BioPhotonics o Software & Computing o BioTechnologies Life Photonics, Sciences & Sensing Healthcare & Display Power Photonics, & Wireless Sensing & Display o RF Devices & Technologies Power & Wireless o Solid-State Lighting o Compound Semiconductors & Emerging Materials o Display o Power Electronics o MEMS, Sensors & Actuators o Batteries & Energy Management o Imaging o Photonics & Optoelectronics 3 About Yole’s Memory Team Walt Coon Mike Howard Simone Bertolazzi, PhD Ivan Donaldson Emilie Jolivet VP of NAND VP of DRAM Technology & Market Analyst VP of Yole Finance Division Director and Memory Research and Memory Research Memory Semiconductor & Software Experience: Experience: Experience: Experience: Experience: 20 years in Memory 15 years in Memory 8 years in Emerging 14 years in Semiconductor 9 years in Equipment, Semiconductors and Devices Industry Strategy, Business Manufacturing, Processing Development, and IR At Yole: At Yole: At Yole: At Yole: At Yole: NAND DRAM Emerging Memory Manages all services Embedded Technologies, and relationships 3DIC & Manufacturing for global financial clients 4 Memory Technologies Focus of Yole’s NAND and DRAM Market Monitors (published every quarter) Focus of MRAM Technology and Business 2019 and Emerging Non-Volatile Memory Report (updated every year) 5 Outline o Overview of the Memory Market Established and Emerging Memory o (STT-)MRAM Technology - Overview Comparison with Other Memory Technologies o (STT-)MRAM Market and Ecosystem Applications & Players’ Dynamics Market Projections and Outlook 6 Stand-Alone Memory Market - Overview • NAND and DRAM account for ≈97% of the overall stand-alone memory market. • Combined NAND and DRAM revenue was ≈ $160 billion in 2018, up 26% from 2017. 2018 Memory Market - Breakdown by Technology 180 70% 64% 160 60% Growth (%) of Revenue 140 50% 120 40% 100 30% 80 26% Revenue in $B Revenue 20% 60 10% 40 1% 20 -1% 0% 0 -10% Total Stand-Alone Market in 2018 ≈ $165 billions 2015 2016 2017 2018 2019 DRAM NAND Source: “Status of the Memory Industry” Report (May 2019), NAND and DRAM Memory Research Service by Yole 7 Emerging NVM Market - Overview • Flash NAND and DRAM will maintain their leading position over the next five years thanks to new technical solutions enabling further scalability. • Emerging NVM is gaining significant momentum, but will remain below 3% of the total stand-alone memory market. ~0.2% Yole Développement © 2019 ≤ 3% ~$165B ~$150B ~$190B 2018 2020 2023 Total Memory Market CAGR2018-2023 ~3% Established Memories (Stand-Alone) Emerging NVM (Stand-Alone) Source: “Emerging NVM” and “Status of the Memory Industry” Reports by Yole 8 Emerging NVM Applications Stand-Alone Embedded Industry & NVM in MCU, transportation, Enterprise Mass storage Cache in mobile Cache in high- NVM for artificial Client SCM SoC and consumer SCM memory devices end processors intelligence ASIC/ASSP electronics IoT Journal Industrial automation Workstation Smartphones NAND & tablets CPU In-memory memory Smart card computing Databases Last-Level Cache (SRAM and eDRAM) Smart meters Notebook General purpose Persistent memory (NVDIMM) Source: “Emerging NVM” Report by Yole Automotive Automotive Increasing density Increasing density 9 Stand-Alone vs Embedded NVM • Stand-alone memory will be the dominant market and is driven primarily by Storage Class Memory (SCM) enterprise and client applications (3D XPoint). • Embedded applications are gaining momentum and will be reaching 16% of the emerging NVM market by 2023 Yole Développement © 2019 2% 2% 16% ~$280 ~$2.4 ~$7.2 2018 2020 2023 84% 98% 98% Emerging Memory Market CAGR2018-2023 ~104% Stand-Alone Emerging NVM Embedded Emerging NVM Source: “Status of the Memory Industry” and “Emerging NVM” Reports by Yole 10 Opportunities for New Memories Low density Medium density High density 10,000 Yole Développement © 2019 1,000 Ind., transp., and CE Embedded NVM Stand-alone NVM 100 Cache in high-end processors (eDRAM) Mainstream memory Embedded NVM in MCUs, SoCs... Enterprise storage SCM M 10 Bubble size corresponds to the total accessible Price per Gb ($/Gb) Gb per Price Cache in mobile devices market (TAM) size in 2018 1 Enterprise/Client SCM S Emerging NVM DRAM scalability improvement 0.1 Sources: “Emerging NVM” and “Status of the Memory Industry” NAND (May 2019) Reports by Yole 0.01 1 Mb 10 Mb 100 Mb 1Gb 10Gb 100Gb 1 Tb Chip Density 11 Memory Technology Comparison 2018 stand-alone commercial products performance PCM Flash Flash STT-MRAM RRAM DRAM 3D XPoint NAND NOR Non-volatile YES YES YES NO YES YES YES Byte addressable YES YES YES YES YES (but not for erase) Endurance High (>109) Medium (107) Low (106) High (1015) Low (105) Low (105) (# cycles) Maximum density 256Mb 128Gb 4Mb 16Gb 1Tb 2Gb for products in 2018 (1Gb ready) Cell size Medium Small Medium Small Medium Very small (4/96L) (cell size in F2) (6-30) (4/2L) (6-30) (6-8) (6-30) Speed Fast Fast Medium Fast Slow Slow write (Latency) (~10 ns) (10-100ns) (~100 ns) (~10 ns) (100,000ns) (100,000ns) Switching Power Medium/Low Medium Medium Low High High 2018 price High Low High Low Very low Medium ($10/Gb) ($/Gb) ($10-100/Gb) (≤ $0.5/Gb) ($100 - 1000/Gb) ($0.97 Gb) ($0.03/Gb) Samsung, Micron, Micron, Winbond, Samsung, Micron, SK Key suppliers Everspin, Avalanche Micron/Intel Adesto, Fujitsu Toshiba, WDC, SK Macronix, Cypress- hynix, Nanya hynix, Intel Infineon, GigaDevice 12 Memory Technology Comparison 2018 stand-alone commercial products performance Pricing position in 2018 ($/Gb) Price 1000 5: best value 5 100 0: worst value Data Storage Yole Développement © 2019 4 10 1 3 0.1 2 0.01 NAND PCM DRAM NOR STT-MRAM RRAM 1 Speed 0 Density Density position in 2018 (Gb) 10000 1000 100 Yole Développement © 2019 NAND 10 PCM 1 DRAM 0.1 NOR 0.01 Working Memory STT-MRAM 0.001 NAND PCM DRAM NOR STT-MRAM RRAM RRAM Endurance 13 Stand-Alone STT-MRAM Roadmap Chip density and technology node scaling - Comparison with DRAM • STT-MRAM will target enterprise storage (SCM) applications for a long time before trying to substitute DRAM. Stand-alone memory density roadmap (Gb) Technology-node scaling (nm) 2018 2019 2020 2021 2022 2023 2024 2018 2019 2020 2021 2022 2023 2024 100 45 40 35 10 30 25 20 Density (Gb/die)Density 1 15 echnology Node(nm) echnology T 10 5 0.1 0 DRAM STT-MRAM DRAM STT-MRAM 14 Embedded Memory Technologies Comparison of embedded technologies (based on technical literature data) 5: best value Standby Power SRAM 0: worst value 5 eDRAM 4 Among established eFlash 3 and emerging Endurance Cell Size STT-MRAM embedded memory 2 PCM technologies, STT- MRAM is promising 1 RRAM as it offers a 0 combination of persistence, low- power consumption, high speed and high Read Speed Write Energy endurance Write Speed 15 Embedded MRAM is Taking Off! Embedded Memory Technology Highlights 30 • eFlash scaling is reaching its end: 28nm/22nm will be likely the last technology nodes. • SRAM scaling is also slowing down. The cell footprint 20 (# of F2) degrades at advanced FinFET nodes • STT-MRAM offers non-volatility together with low power Code/Data Storage (eFlash-like) consumption, which is ideal for low-power MCUs, Working Memory (slow SRAM-like) wearables and IoTs. Technology (nm) Node Technology 10 LL Cache Memory (replace eDRAM/SRAM) • STT-MRAM offer a significant density gain over SRAM. At advanced nodes (≤1xnm) more than ×3 gain. Thanks to strong support of top foundry/IDM players and equipment suppliers, embedded STT-MRAM is poised to 0 become the next embedded NVM solution for nodes ≤28nm. 2018 2019 2020 2021 2022 2023 2024 SRAM eFlash eMRAM 16 (STT-)MRAM Applications Stand-alone Embedded Industry, Code/Data Storage “Working” Memory Cache Memory transportation, Enterprise Storage Persistent Memory (Slow SRAM) (SRAM, eDRAM) and other (eFlash) NVSRAM MCU, ASSP, ASIC, SoC CMOS Image Sensors Industrial Storage Accelerators Image memory buffer NVDIMM CPU automation Network Interface Cards Persistent Memory for Servers Transport Aerospace 2023+ IoT / Wearables Display Driver ICs Medical Tcon, memory buffers Gaming Mobile AP General Purpose Network & Infrastructure Solid State Drives 2023+ Write caching, journaling, logs, data buffering and Edge AI accelerator chips In memory computing streams Automotive Required Speed/Density Required Speed/Density 17 The MRAM Ecosystem is Growing An increasing number of players are involved in the MRAM arena MRAM IP and Design Players in mass production or close to mass production Embedded MRAM manufacturers 40nm, up to 128Mb 40nm, 28nm (256M, 1Gb) Toggle Manufacturing Expected: 28nm, 22nm Stand-alone MRAM manufacturers 18 Embedded MRAM Business Key partnerships and developments for leading players. Foundry / IDM To be announced (STT-)MRAM Players - Partners CMOS bulk FD-SOI 22nm FD-SOI 28nm CMOS bulk CMOS 22nm Technology planar 22nm planar planar 28/22nm planar FinFET 28/22nm Process (in mass (sampling) (sampling) (in development) (sampling) production) Expected Short- eFlash eFlash “Slow” SRAM eFlash “Slow” SRAM “Slow” SRAM Term Application “Slow” SRAM “Slow” SRAM 19 Embedded MRAM Business Challenges and developments by equipment suppliers
Recommended publications
  • Chapter 3 Semiconductor Memories
    Chapter 3 Semiconductor Memories Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction Random Access Memories Content Addressable Memories Read Only Memories Flash Memories Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2 Overview of Memory Types Semiconductor Memories Read/Write Memory or Random Access Memory (RAM) Read Only Memory (ROM) Random Access Non-Random Access Memory (RAM) Memory (RAM) •Mask (Fuse) ROM •Programmable ROM (PROM) •Erasable PROM (EPROM) •Static RAM (SRAM) •FIFO/LIFO •Electrically EPROM (EEPROM) •Dynamic RAM (DRAM) •Shift Register •Flash Memory •Register File •Content Addressable •Ferroelectric RAM (FRAM) Memory (CAM) •Magnetic RAM (MRAM) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3 Memory Elements – Memory Architecture Memory elements may be divided into the following categories Random access memory Serial access memory Content addressable memory Memory architecture 2m+k bits row decoder row decoder 2n-k words row decoder row decoder column decoder k column mux, n-bit address sense amp, 2m-bit data I/Os write buffers Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4 1-D Memory Architecture S0 S0 Word0 Word0 S1 S1 Word1 Word1 S2 S2 Word2 Word2 A0 S3 S3 A1 Decoder Ak-1 Sn-2 Storage Sn-2 Wordn-2 element Wordn-2 Sn-1 Sn-1 Wordn-1 Wordn-1 m-bit m-bit Input/Output Input/Output n select signals are reduced n select signals: S0-Sn-1 to k address signals: A0-Ak-1 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5 Memory Architecture S0 Word0 Wordi-1 S1 A0 A1 Ak-1 Row Decoder Sn-1 Wordni-1 A 0 Column Decoder Aj-1 Sense Amplifier Read/Write Circuit m-bit Input/Output Advanced Reliable Systems (ARES) Lab.
    [Show full text]
  • Section 10 Flash Technology
    10 FLASH TECHNOLOGY Overview Flash memory technology is a mix of EPROM and EEPROM technologies. The term “flash” was chosen because a large chunk of memory could be erased at one time. The name, therefore, distinguishes flash devices from EEPROMs, where each byte is erased individually. Flash memory technology is today a mature technology. Flash memory is a strong com- petitor to other memories such as EPROMs, EEPROMs, and to some DRAM applications. Figure 10-1 shows the density comparison of a flash versus other memories. 64M 16M 4M DRAM/EPROM 1M SRAM/EEPROM Density 256K Flash 64K 1980 1982 1984 1986 1988 1990 1992 1994 1996 Year Source: Intel/ICE, "Memory 1996" 18613A Figure 10-1. Flash Density Versus Other Memory How the Device Works The elementary flash cell consists of one transistor with a floating gate, similar to an EPROM cell. However, technology and geometry differences between flash devices and EPROMs exist. In particular, the gate oxide between the silicon and the floating gate is thinner for flash technology. It is similar to the tunnel oxide of an EEPROM. Source and INTEGRATED CIRCUIT ENGINEERING CORPORATION 10-1 Flash Technology drain diffusions are also different. Figure 10-2 shows a comparison between a flash cell and an EPROM cell with the same technology complexity. Due to thinner gate oxide, the flash device will be more difficult to process. CMOS Flash Cell CMOS EPROM Cell Mag. 10,000x Mag. 10,000x Flash Memory Cell – Larger transistor – Thinner floating gate – Thinner oxide (100-200Å) Photos by ICE 17561A Figure 10-2.
    [Show full text]
  • Nanotechnology ? Nram (Nano Random Access
    International Journal Of Engineering Research and Technology (IJERT) IFET-2014 Conference Proceedings INTERFACE ECE T14 INTRACT – INNOVATE - INSPIRE NANOTECHNOLOGY – NRAM (NANO RANDOM ACCESS MEMORY) RANJITHA. T, SANDHYA. R GOVERNMENT COLLEGE OF TECHNOLOGY, COIMBATORE 13. containing elements, nanotubes, are so small, NRAM technology will Abstract— NRAM (Nano Random Access Memory), is one of achieve very high memory densities: at least 10-100 times our current the important applications of nanotechnology. This paper has best. NRAM will operate electromechanically rather than just been prepared to cull out answers for the following crucial electrically, setting it apart from other memory technologies as a questions: nonvolatile form of memory, meaning data will be retained even What is NRAM? when the power is turned off. The creators of the technology claim it What is the need of it? has the advantages of all the best memory technologies with none of How can it be made possible? the disadvantages, setting it up to be the universal medium for What is the principle and technology involved in NRAM? memory in the future. What are the advantages and features of NRAM? The world is longing for all the things it can use within its TECHNOLOGY palm. As a result nanotechnology is taking its head in the world. Nantero's technology is based on a well-known effect in carbon Much of the electronic gadgets are reduced in size and increased nanotubes where crossed nanotubes on a flat surface can either be in efficiency by the nanotechnology. The memory storage devices touching or slightly separated in the vertical direction (normal to the are somewhat large in size due to the materials used for their substrate) due to Van der Waal's interactions.
    [Show full text]
  • MSP430 Flash Memory Characteristics (Rev. B)
    Application Report SLAA334B–September 2006–Revised August 2018 MSP430 Flash Memory Characteristics ........................................................................................................................ MSP430 Applications ABSTRACT Flash memory is a widely used, reliable, and flexible nonvolatile memory to store software code and data in a microcontroller. Failing to handle the flash according to data-sheet specifications can result in unreliable operation of the application. This application report explains the physics behind these specifications and also gives recommendations for the correct management of flash memory on MSP430™ microcontrollers (MCUs). All examples are based on the flash memory used in the MSP430F1xx, MSP430F2xx, and MSP430F4xx microcontroller families. Contents 1 Flash Memory ................................................................................................................ 2 2 Simplified Flash Memory Cell .............................................................................................. 2 3 Flash Memory Parameters ................................................................................................. 3 3.1 Data Retention ...................................................................................................... 3 3.2 Flash Endurance.................................................................................................... 5 3.3 Cumulative Program Time......................................................................................... 5 4
    [Show full text]
  • The Rise of the Flash Memory Market: Its Impact on Firm
    The Rise of the Flash Web version: Memory Market: Its Impact July 2007 on Firm Behavior and Author: Global Semiconductor Falan Yinug1 Trade Patterns Abstract This article addresses three questions about the flash memory market. First, will the growth of the flash memory market be a short- or long-term phenomenon? Second, will the growth of the flash memory market prompt changes in firm behavior and industry structure? Third, what are the implications for global semiconductor trade patterns of flash memory market growth? The analysis concludes that flash memory market growth is a long-term phenomenon to which producers have responded in four distinct ways. It also concludes that the rise in flash memory demand has intensified current semiconductor trade patterns but has not shifted them fundamentally. 1 Falan Yinug ([email protected]) is a International Trade Analyst from the Office of Industries. His words are strictly his own and do not represent the opinions of the US International Trade Commission or of any of its Commissioners. 1 Introduction The past few years have witnessed rapid growth in a particular segment of the 2 semiconductor market known as flash memory. In each of the past five years, for example, flash memory market growth has either outpaced or equaled that 3 of the total integrated circuit (IC) market (McClean et al 2004-2007, section 5). One observer expects flash memory to have the third-strongest market growth rate over the next six years among all IC product categories (McClean et al 2007, 5-6). As a result, the flash memory share of the total IC market has increased from 5.5 percent in 2002, to 8.1 percent in 2005.
    [Show full text]
  • Charles Lindsey the Mechanical Differential Analyser Built by Metropolitan Vickers in 1935, to the Order of Prof
    Issue Number 51 Summer 2010 Computer Conservation Society Aims and objectives The Computer Conservation Society (CCS) is a co-operative venture between the British Computer Society (BCS), the Science Museum of London and the Museum of Science and Industry (MOSI) in Manchester. The CCS was constituted in September 1989 as a Specialist Group of the British Computer Society. It is thus covered by the Royal Charter and charitable status of the BCS. The aims of the CCS are: To promote the conservation of historic computers and to identify existing computers which may need to be archived in the future, To develop awareness of the importance of historic computers, To develop expertise in the conservation and restoration of historic computers, To represent the interests of Computer Conservation Society members with other bodies, To promote the study of historic computers, their use and the history of the computer industry, To publish information of relevance to these objectives for the information of Computer Conservation Society members and the wider public. Membership is open to anyone interested in computer conservation and the history of computing. The CCS is funded and supported by voluntary subscriptions from members, a grant from the BCS, fees from corporate membership, donations, and by the free use of the facilities of both museums. Some charges may be made for publications and attendance at seminars and conferences. There are a number of active Projects on specific computer restorations and early computer technologies and software.
    [Show full text]
  • A Hybrid Swapping Scheme Based on Per-Process Reclaim for Performance Improvement of Android Smartphones (August 2018)
    Received August 19, 2018, accepted September 14, 2018, date of publication October 1, 2018, date of current version October 25, 2018. Digital Object Identifier 10.1109/ACCESS.2018.2872794 A Hybrid Swapping Scheme Based On Per-Process Reclaim for Performance Improvement of Android Smartphones (August 2018) JUNYEONG HAN 1, SUNGEUN KIM1, SUNGYOUNG LEE1, JAEHWAN LEE2, AND SUNG JO KIM2 1LG Electronics, Seoul 07336, South Korea 2School of Software, Chung-Ang University, Seoul 06974, South Korea Corresponding author: Sung Jo Kim ([email protected]) This work was supported in part by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education under Grant 2016R1D1A1B03931004 and in part by the Chung-Ang University Research Scholarship Grants in 2015. ABSTRACT As a way to increase the actual main memory capacity of Android smartphones, most of them make use of zRAM swapping, but it has limitation in increasing its capacity since it utilizes main memory. Unfortunately, they cannot use secondary storage as a swap space due to the long response time and wear-out problem. In this paper, we propose a hybrid swapping scheme based on per-process reclaim that supports both secondary-storage swapping and zRAM swapping. It attempts to swap out all the pages in the working set of a process to a zRAM swap space rather than killing the process selected by a low-memory killer, and to swap out the least recently used pages into a secondary storage swap space. The main reason being is that frequently swap- in/out pages use the zRAM swap space while less frequently swap-in/out pages use the secondary storage swap space, in order to reduce the page operation cost.
    [Show full text]
  • AN568: EEPROM Emulation for Flash Microcontrollers
    AN568 EEPROM EMULATION FOR FLASH MICROCONTROLLERS 1. Introduction Non-volatile data storage is an important feature of many embedded systems. Dedicated, byte-writeable EEPROM devices are commonly used in such systems to store calibration constants and other parameters that may need to be updated periodically. These devices are typically accessed by an MCU in the system using a serial bus. This solution requires PCB real estate as well as I/O pins and serial bus resources on the MCU. Some cost efficiencies can be realized by using a small amount of the MCU’s flash memory for the EEPROM storage. This note describes firmware designed to emulate EEPROM storage on Silicon Laboratories’ flash-based C8051Fxxx MCUs. Figure 1 shows a map of the example firmware. The highlighted functions are the interface for the main application code. 2. Key Features Compile-Time Configurable Size: Between 4 and 255 bytes Portable: Works across C8051Fxxx device families and popular 8051 compilers Fault Tolerant: Resistant to corruption from power supply events and errant code Small Code Footprint: Less than 1 kB for interface functions + minimum two pages of Flash for data storage User Code Fxxx_EEPROM_Interface.c EEPROM_WriteBlock() EEPROM_ReadBlock() copySector() findCurrentSector() getBaseAddress() findNextSector() Fxxx_Flash_Interface.c FLASH_WriteErase() FLASH_BlankCheck() FLASH_Read() Figure 1. EEPROM Emulation Firmware Rev. 0.1 12/10 Copyright © 2010 by Silicon Laboratories AN568 AN568 3. Basic Operation A very simple example project and wrapper code is included with the source firmware. The example demonstrates how to set up a project with the appropriate files within the Silicon Labs IDE and how to call the EEPROM access functions from user code.
    [Show full text]
  • Analyzing the Performance of Intel Optane DC Persistent Memory in Storage Over App Direct Mode
    Front cover Analyzing the Performance of Intel Optane DC Persistent Memory in Storage over App Direct Mode Introduces DCPMM Storage over Evaluates workload latency and App Direct Mode bandwidth performance Establishes performance Illustrates scaling performance for expectations for DCPMM DCPMM populations capacities Travis Liao Tristian "Truth" Brown Jamie Chou Abstract Intel Optane DC Persistent Memory is the latest memory technology for Lenovo® ThinkSystem™ servers. This technology deviates from contemporary flash storage offerings and utilizes the ground-breaking 3D XPoint non-volatile memory technology to deliver a new level of versatile performance in a compact memory module form factor. As server storage technology continues to advance from devices behind RAID controllers to offerings closer to the processor, it is important to understand the technological differences and suitable use cases. This paper provides a look into the performance of Intel Optane DC Persistent Memory Modules configured in Storage over App Direct Mode operation. At Lenovo Press, we bring together experts to produce technical publications around topics of importance to you, providing information and best practices for using Lenovo products and solutions to solve IT challenges. See a list of our most recent publications at the Lenovo Press web site: http://lenovopress.com Do you have the latest version? We update our papers from time to time, so check whether you have the latest version of this document by clicking the Check for Updates button on the front page of the PDF. Pressing this button will take you to a web page that will tell you if you are reading the latest version of the document and give you a link to the latest if needed.
    [Show full text]
  • Data Remanence in Flash Memory Devices
    Data Remanence in Flash Memory Devices Sergei Skorobogatov University of Cambridge, Computer Laboratory, 15 JJ Thomson Avenue, Cambridge CB3 0FD, United Kingdom [email protected] Abstract. Data remanence is the residual physical representation of data that has been erased or overwritten. In non-volatile programmable devices, such as UV EPROM, EEPROM or Flash, bits are stored as charge in the floating gate of a transistor. After each erase operation, some of this charge remains. Security protection in microcontrollers and smartcards with EEPROM/Flash memories is based on the assumption that information from the memory disappears completely after erasing. While microcontroller manufacturers successfully hardened already their designs against a range of attacks, they still have a common problem with data remanence in floating-gate transistors. Even after an erase operation, the transistor does not return fully to its initial state, thereby allowing the attacker to distinguish between previously programmed and not programmed transistors, and thus restore information from erased memory. The research in this direction is summarised here and it is shown how much information can be extracted from some microcontrollers after their memory has been ‘erased’. 1 Introduction Data remanence as a problem was first discovered in magnetic media [1,2]. Even if the information is overwritten several times on disks and tapes, it can still be possible to extract the initial data. This led to the development of special methods for reliably removing confidential information from magnetic media. Semiconductor memory in security modules was found to have similar prob- lems with reliable data deletion [3,4]. Data remanence affects not only SRAM, but also memory types like DRAM, UV EPROM, EEPROM and Flash [5].
    [Show full text]
  • Low-Cost Integration of Serial Eeproms and Flash Memory Devices
    White Paper Low-Cost Integration of Serial EEPROMs and Flash Memory Devices Introduction In many applications, non-volatile memory needs are addressed by general-purpose serial-interface electrically erasable programmable read-only memories (EEPROMs) or flash memory devices, especially since they offer low pin-count, small packages, low voltage operation, and low power consumption. Nevertheless, designers still face the challenge of reducing board space and total system cost. Many of the uses for these memory devices are related to system configuration, manufacturing, and security. The functionality provided by serial EEPROMs and some flash devices in these applications can be integrated into a MAX® II CPLD, which offers an 8-Kbit flash storage block called the user flash memory (UFM). The UFM allows users to integrate existing serial EEPROMs on a board, reducing total system cost, minimizing board space, and offering higher reliability and better manufacturability. Serial EEPROM and Flash Memory Device Challenges As electronic systems continue to shrink, the demand for smaller board sizes increases. The packaging of a product is defined by board size and is driven by the number of components. Board components are a direct function of the end-product cost: the more components on a board, the more expensive the end product. Assembly costs, shipping costs, programming costs, and additional support circuitry for serial EEPROMs and flash devices add to total board cost, increasing the cost of the end product. Power consumption and reliability are other challenges design engineers face; the fewer devices resident on the board, the lower the power consumption. The potential for improved reliability of the end product also increases.
    [Show full text]
  • Initial Experience with 3D Xpoint Main Memory
    Initial Experience with 3D XPoint Main Memory Jihang Liu Shimin Chen* State Key Laboratory of Computer Architecture State Key Laboratory of Computer Architecture Institute of Computing Technology, CAS Institute of Computing Technology, CAS University of Chinese Academy of Sciences University of Chinese Academy of Sciences [email protected] [email protected] Abstract—3D XPoint will likely be the first commercially available main memory NVM solution targeting mainstream computer systems. Previous database studies on NVM memory evaluate their proposed techniques mainly on simulated or emulated NVM hardware. In this paper, we report our initial experience experimenting with the real 3D XPoint main memory hardware. I. INTRODUCTION A new generation of Non-Volatile Memory (NVM) tech- nologies, including PCM [1], STT-RAM [2], and Memris- tor [3], are expected to address the DRAM scaling problem and become the next generation main memory technology Fig. 1. AEP machine. in future computer systems [4]–[7]. NVM has become a hot topic in database research in recent years. However, previous First, there are two CPUs in the machine. From the studies evaluate their proposed techniques mainly on simulated /proc/cpuinfo, the CPU model is listed as “Genuine In- or emulated hardware. In this paper, we report our initial tel(R) CPU 0000%@”. Our guess is that the CPU is a test experience with real NVM main memory hardware. model and/or not yet recognized by the Linux kernel. The 3D XPoint is an NVM technology jointly developed by CPU supports the new clwb instruction [9]. Given a memory Intel and Micron [8]. Intel first announced the technology address, clwb writes back to memory the associated cache in 2015.
    [Show full text]