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Chapter 3 Semiconductor Memories
Chapter 3 Semiconductor Memories Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction Random Access Memories Content Addressable Memories Read Only Memories Flash Memories Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2 Overview of Memory Types Semiconductor Memories Read/Write Memory or Random Access Memory (RAM) Read Only Memory (ROM) Random Access Non-Random Access Memory (RAM) Memory (RAM) •Mask (Fuse) ROM •Programmable ROM (PROM) •Erasable PROM (EPROM) •Static RAM (SRAM) •FIFO/LIFO •Electrically EPROM (EEPROM) •Dynamic RAM (DRAM) •Shift Register •Flash Memory •Register File •Content Addressable •Ferroelectric RAM (FRAM) Memory (CAM) •Magnetic RAM (MRAM) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3 Memory Elements – Memory Architecture Memory elements may be divided into the following categories Random access memory Serial access memory Content addressable memory Memory architecture 2m+k bits row decoder row decoder 2n-k words row decoder row decoder column decoder k column mux, n-bit address sense amp, 2m-bit data I/Os write buffers Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4 1-D Memory Architecture S0 S0 Word0 Word0 S1 S1 Word1 Word1 S2 S2 Word2 Word2 A0 S3 S3 A1 Decoder Ak-1 Sn-2 Storage Sn-2 Wordn-2 element Wordn-2 Sn-1 Sn-1 Wordn-1 Wordn-1 m-bit m-bit Input/Output Input/Output n select signals are reduced n select signals: S0-Sn-1 to k address signals: A0-Ak-1 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5 Memory Architecture S0 Word0 Wordi-1 S1 A0 A1 Ak-1 Row Decoder Sn-1 Wordni-1 A 0 Column Decoder Aj-1 Sense Amplifier Read/Write Circuit m-bit Input/Output Advanced Reliable Systems (ARES) Lab. -
Section 10 Flash Technology
10 FLASH TECHNOLOGY Overview Flash memory technology is a mix of EPROM and EEPROM technologies. The term “flash” was chosen because a large chunk of memory could be erased at one time. The name, therefore, distinguishes flash devices from EEPROMs, where each byte is erased individually. Flash memory technology is today a mature technology. Flash memory is a strong com- petitor to other memories such as EPROMs, EEPROMs, and to some DRAM applications. Figure 10-1 shows the density comparison of a flash versus other memories. 64M 16M 4M DRAM/EPROM 1M SRAM/EEPROM Density 256K Flash 64K 1980 1982 1984 1986 1988 1990 1992 1994 1996 Year Source: Intel/ICE, "Memory 1996" 18613A Figure 10-1. Flash Density Versus Other Memory How the Device Works The elementary flash cell consists of one transistor with a floating gate, similar to an EPROM cell. However, technology and geometry differences between flash devices and EPROMs exist. In particular, the gate oxide between the silicon and the floating gate is thinner for flash technology. It is similar to the tunnel oxide of an EEPROM. Source and INTEGRATED CIRCUIT ENGINEERING CORPORATION 10-1 Flash Technology drain diffusions are also different. Figure 10-2 shows a comparison between a flash cell and an EPROM cell with the same technology complexity. Due to thinner gate oxide, the flash device will be more difficult to process. CMOS Flash Cell CMOS EPROM Cell Mag. 10,000x Mag. 10,000x Flash Memory Cell – Larger transistor – Thinner floating gate – Thinner oxide (100-200Å) Photos by ICE 17561A Figure 10-2. -
Nanotechnology ? Nram (Nano Random Access
International Journal Of Engineering Research and Technology (IJERT) IFET-2014 Conference Proceedings INTERFACE ECE T14 INTRACT – INNOVATE - INSPIRE NANOTECHNOLOGY – NRAM (NANO RANDOM ACCESS MEMORY) RANJITHA. T, SANDHYA. R GOVERNMENT COLLEGE OF TECHNOLOGY, COIMBATORE 13. containing elements, nanotubes, are so small, NRAM technology will Abstract— NRAM (Nano Random Access Memory), is one of achieve very high memory densities: at least 10-100 times our current the important applications of nanotechnology. This paper has best. NRAM will operate electromechanically rather than just been prepared to cull out answers for the following crucial electrically, setting it apart from other memory technologies as a questions: nonvolatile form of memory, meaning data will be retained even What is NRAM? when the power is turned off. The creators of the technology claim it What is the need of it? has the advantages of all the best memory technologies with none of How can it be made possible? the disadvantages, setting it up to be the universal medium for What is the principle and technology involved in NRAM? memory in the future. What are the advantages and features of NRAM? The world is longing for all the things it can use within its TECHNOLOGY palm. As a result nanotechnology is taking its head in the world. Nantero's technology is based on a well-known effect in carbon Much of the electronic gadgets are reduced in size and increased nanotubes where crossed nanotubes on a flat surface can either be in efficiency by the nanotechnology. The memory storage devices touching or slightly separated in the vertical direction (normal to the are somewhat large in size due to the materials used for their substrate) due to Van der Waal's interactions. -
MSP430 Flash Memory Characteristics (Rev. B)
Application Report SLAA334B–September 2006–Revised August 2018 MSP430 Flash Memory Characteristics ........................................................................................................................ MSP430 Applications ABSTRACT Flash memory is a widely used, reliable, and flexible nonvolatile memory to store software code and data in a microcontroller. Failing to handle the flash according to data-sheet specifications can result in unreliable operation of the application. This application report explains the physics behind these specifications and also gives recommendations for the correct management of flash memory on MSP430™ microcontrollers (MCUs). All examples are based on the flash memory used in the MSP430F1xx, MSP430F2xx, and MSP430F4xx microcontroller families. Contents 1 Flash Memory ................................................................................................................ 2 2 Simplified Flash Memory Cell .............................................................................................. 2 3 Flash Memory Parameters ................................................................................................. 3 3.1 Data Retention ...................................................................................................... 3 3.2 Flash Endurance.................................................................................................... 5 3.3 Cumulative Program Time......................................................................................... 5 4 -
Tape Goes High Speed Tests Confirm Advantages of Combining Tape, Flash and Software- Defined Storage in a Single, Low-Cost Solution
IBM Systems November 2016 Technical White Paper Tape goes high speed Tests confirm advantages of combining tape, flash and software- defined storage in a single, low-cost solution Forward-thinking IT architects have extolled for years the benefits of Highlights building an overall storage solution using only flash and tape storage media. Place active data on flash to accelerate storage performance and • Gain high performance, high capacity efficiency; move less-active data to tape to lower overall storage costs. and low-c ost storage all in one solution This storage architecture has informally been named “flape.” But until • Leverage the cost and capacity recently, implementing effective flape solutions has proved problematic. advantages of tape to build powerful analytics systems Software-defined storage (SDS) technologies, however, have changed the • Lower storage costs without losing flape equation. SDS capabilities such as those provided by members of capabilities or performance the IBM® Spectrum Storage™ family open up exciting new possibilities, enabling the deployment of easily managed high-performance, low-cost storage solutions using SDS components integrated with IBM tape and flash systems. A proof of concept of this innovative new flash, SDS and tape-based storage architecture was recently performed in the Ennovar Solution Reference Architecture laboratory at Wichita State University. Using IBM Spectrum Scale™ and IBM Spectrum Archive™ SDS components, an IBM DCS3860 solid-state drive (SSD) array and IBM tape systems with analytics application workloads provided by the National Institute for Aviation Research (NIAR), the Ennovar team demonstrated the advantages of the flape architecture while increasing analytics performance by an average of more than three times. -
The Rise of the Flash Memory Market: Its Impact on Firm
The Rise of the Flash Web version: Memory Market: Its Impact July 2007 on Firm Behavior and Author: Global Semiconductor Falan Yinug1 Trade Patterns Abstract This article addresses three questions about the flash memory market. First, will the growth of the flash memory market be a short- or long-term phenomenon? Second, will the growth of the flash memory market prompt changes in firm behavior and industry structure? Third, what are the implications for global semiconductor trade patterns of flash memory market growth? The analysis concludes that flash memory market growth is a long-term phenomenon to which producers have responded in four distinct ways. It also concludes that the rise in flash memory demand has intensified current semiconductor trade patterns but has not shifted them fundamentally. 1 Falan Yinug ([email protected]) is a International Trade Analyst from the Office of Industries. His words are strictly his own and do not represent the opinions of the US International Trade Commission or of any of its Commissioners. 1 Introduction The past few years have witnessed rapid growth in a particular segment of the 2 semiconductor market known as flash memory. In each of the past five years, for example, flash memory market growth has either outpaced or equaled that 3 of the total integrated circuit (IC) market (McClean et al 2004-2007, section 5). One observer expects flash memory to have the third-strongest market growth rate over the next six years among all IC product categories (McClean et al 2007, 5-6). As a result, the flash memory share of the total IC market has increased from 5.5 percent in 2002, to 8.1 percent in 2005. -
An Electronic Digital Computor Using Cold Cathode Counting Tubes for Storage
An Electronic Digital Computor Using Cold Cathode Counting Tubes for Storage By R. C. M. Barnes, B.Sc., E. H. Cooke-Yarborough, M.A., A.M.I.E.E., and D. G. A. Thomas, M.A. Electronic Engineering - August 1951. A small sequence-controlled computor is described; it has storage capacity for up to 90 numbers each of eight decimal digits. Cold cathode counting tubes (Dekatrons) are used as storage elements. Parallel operation is employed, and the speed of operation is comparable with that of a desk calculating machine. Apart from speed, however, the computor provides most of the facilities found in larger, faster digital computors. Information is fed into the machine from perforated paper tapes and a teleprinter or tape perforator records the results. SEVERAL large-scale computors have been described in recent years, including the ENIAC with hard valve circuits, the EDSAC with mercury delay storage, the University of Manchester computor with cathode-ray storage and the Birkbeck College computor with magnetic storage. These computors are intended primarily to carry out enormous computations, too lengthy to perform by other means. In addition smaller scale relay computors have been built for general work. The machine described here is not intended to deal with the long calculations for which the large computors have been designed. It is intended rather to do the work of a few operators with desk calculating machines where the work to be done is of a routine or repetitive nature, As a result, simplicity and reliability have been regarded as of more importance than speed of operation and the machine performs the operations of addition, subtraction, multiplication and division little faster than a desk calculator. -
A Hybrid Swapping Scheme Based on Per-Process Reclaim for Performance Improvement of Android Smartphones (August 2018)
Received August 19, 2018, accepted September 14, 2018, date of publication October 1, 2018, date of current version October 25, 2018. Digital Object Identifier 10.1109/ACCESS.2018.2872794 A Hybrid Swapping Scheme Based On Per-Process Reclaim for Performance Improvement of Android Smartphones (August 2018) JUNYEONG HAN 1, SUNGEUN KIM1, SUNGYOUNG LEE1, JAEHWAN LEE2, AND SUNG JO KIM2 1LG Electronics, Seoul 07336, South Korea 2School of Software, Chung-Ang University, Seoul 06974, South Korea Corresponding author: Sung Jo Kim ([email protected]) This work was supported in part by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education under Grant 2016R1D1A1B03931004 and in part by the Chung-Ang University Research Scholarship Grants in 2015. ABSTRACT As a way to increase the actual main memory capacity of Android smartphones, most of them make use of zRAM swapping, but it has limitation in increasing its capacity since it utilizes main memory. Unfortunately, they cannot use secondary storage as a swap space due to the long response time and wear-out problem. In this paper, we propose a hybrid swapping scheme based on per-process reclaim that supports both secondary-storage swapping and zRAM swapping. It attempts to swap out all the pages in the working set of a process to a zRAM swap space rather than killing the process selected by a low-memory killer, and to swap out the least recently used pages into a secondary storage swap space. The main reason being is that frequently swap- in/out pages use the zRAM swap space while less frequently swap-in/out pages use the secondary storage swap space, in order to reduce the page operation cost. -
LTO Tape Technologies: Economic Value Analysis
White Paper Analyzing the Economic Value of LTO Tape for Long-term Data Retention By Jason Buffington, Senior Analyst – Data Protection, and Adam DeMattia, Research Analyst February 2016 This ESG White Paper was commissioned by the LTO Program and is distributed under license from ESG. © 2016 by The Enterprise Strategy Group, Inc. All Rights Reserved. White Paper: Analyzing the Economic Value of LTO Tape for Long-term Data Retention 2 Contents Introduction .................................................................................................................................................. 3 Executive Summary .................................................................................................................................................. 3 Market Overview ...................................................................................................................................................... 3 Excerpts of the ESG Lab Review on LTO Tape Technology ....................................................................................... 4 LTO Tape Technologies: Economic Value Analysis ....................................................................................... 5 Methodology ............................................................................................................................................................ 5 Economic Value Model Overview ............................................................................................................................. 5 Cost -
A Hybrid Computer for X-Ray Crystallography
A HYBRID COMPUTER FOR X-RAY CRYSTALLOGRAPHY BY S. HARIGOVINDAN ( Depaetment of Physics, Indian lnstitute of Science, Bangalore-12) Received November 19, 1965 (Communicated by Dr. R. S. Krishnan, F.A.SC.) ABSTRACT A hybrid computer for structure factor calculations in X-ray crystallo- graphy is described. The computer can calculate three-dimensional struc- ture factors of up to 24 atoms in a single run and can generate the scatter functions of well over 100 atoms using Vand et al., of Forsyth and Wells approximations. The computer is essentially a digital computer with analog function generators, thus combining to advantage the economic data storage of digital systems and simple computing circuitry of analog systems. The digital part serially selects the data, computes and feeds the arguments into specially developed high precision digital-analog func- tion generators, the outputs of which being d.c. voltages, are further processed by analog circuits and fina]ly the sequential adder, which employs a novel digital voltmeter circuit, converts them back into digital form and accumulates them in a dekatron counter which displays the final result. The computer is also capable of carrying out 1-, 2-, or 3-dimensional Fourier summation, although in this case, the lack of sufficient storage space for the large number of coeflicients involved, is a scrious limitation at present. INTRODUCTION IN X-ray crystal structure determination, two types of computations, namely those of electron density and structure factor, are repeatedly required, and small-scale special purpose computers for these computations are extremely useful in speeding up the structure determination. A hyb¡ computer, developed and constructed by the author (1964), mainly for the second type of computations, is described in this paper. -
The Harwell Dekatron Computer Kevin Murrell
The Harwell Dekatron Computer Kevin Murrell To cite this version: Kevin Murrell. The Harwell Dekatron Computer. International Conference on History of Comput- ing (HC), Jun 2013, London, United Kingdom. pp.309-313, 10.1007/978-3-642-41650-7_28. hal- 01455261 HAL Id: hal-01455261 https://hal.inria.fr/hal-01455261 Submitted on 3 Feb 2017 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Distributed under a Creative Commons Attribution| 4.0 International License The Harwell Dekatron Computer Kevin Murrell Computer Conservation Society and The National Museum of Computing, UK [email protected] Abstract: The Harwell Dekatron Computer is a very early digital computer designed and built by the British Atomic Energy Research Establishment in 1952. The computer used British Post Office relays for control and sequencing, and Dekatron counting tubes for storage. After several years’ service, it was passed to a college where it was used to teach computer programming, before being lost to various storage centres. In 2008 the machine was re-discovered and the decision was made to restore the computer to working order. This paper describes the machine and the choices and decisions made during the restoration process. -
Dell EMC ML3 Tape Library User's Guide
Dell EMC ML3 Tape Library User's Guide Information in this document is subject to change without notice. Copyright © 2020 Dell Inc. or its subsidiaries. All rights reserved. Dell, EMC, and other trademarks are trademarks of Dell Inc. or its subsidiaries. Other trademarks may be trademarks of their respective owners. Printed September 2020. ii Dell EMC ML3 Tape Library: User's Guide Read this FIRST Regulatory information • The library must be installed in a restricted area. • Only personnel with technical and product safety training should have access to the library. • The library must be properly installed in an office or industrial environment with shielded cables and adequate grounding of SAS interface and input power to comply with regulations and standards. • Models: 3555-L3A, 3555-E3A The system complies to all applicable safety standards to allow for shipments worldwide including the America's, European Union Member States, Middle East, and Asia. Minimum firmware levels for common library features Table 1. Minimum firmware levels for common library features Feature Minimum Firmware Levels Required LTO8 (HH/FH) Tape Drives Library Firmware must be at 1.1.1.0 or greater to support the LTO8 tape drives. Ensure that any host applications and device drivers are at the minimum level that is required to support LTO8 tape drives. Certain non-IBM LTO8 media requires minimum drive firmware J4D4. Contact your media supplier for details. LTO6 (HH/FH) and LTO7 (HH/FH) Tape Drives Library Firmware must be at 1.1.0.1-A00 or greater to support the LTO6 and LTO7 tape drives. Ensure that any host applications and device drivers are at the minimum level that is required to support LTO6 and LTO7 tape drives.