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Chapter 3 Semiconductor Memories

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Chapter 3 Semiconductor Memories Chapter 3 Semiconductor Memories Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction Random Access Memories Content Addressable Memories Read Only Memories Flash Memories Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2 Overview of Memory Types Semiconductor Memories Read/Write Memory or Random Access Memory (RAM) Read Only Memory (ROM) Random Access Non-Random Access Memory (RAM) Memory (RAM) •Mask (Fuse) ROM •Programmable ROM (PROM) •Erasable PROM (EPROM) •Static RAM (SRAM) •FIFO/LIFO •Electrically EPROM (EEPROM) •Dynamic RAM (DRAM) •Shift Register •Flash Memory •Register File •Content Addressable •Ferroelectric RAM (FRAM) Memory (CAM) •Magnetic RAM (MRAM) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3 Memory Elements – Memory Architecture Memory elements may be divided into the following categories Random access memory Serial access memory Content addressable memory Memory architecture 2m+k bits row decoder row decoder 2n-k words row decoder row decoder column decoder k column mux, n-bit address sense amp, 2m-bit data I/Os write buffers Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4 1-D Memory Architecture S0 S0 Word0 Word0 S1 S1 Word1 Word1 S2 S2 Word2 Word2 A0 S3 S3 A1 Decoder Ak-1 Sn-2 Storage Sn-2 Wordn-2 element Wordn-2 Sn-1 Sn-1 Wordn-1 Wordn-1 m-bit m-bit Input/Output Input/Output n select signals are reduced n select signals: S0-Sn-1 to k address signals: A0-Ak-1 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5 Memory Architecture S0 Word0 Wordi-1 S1 A0 A1 Ak-1 Row Decoder Sn-1 Wordni-1 A 0 Column Decoder Aj-1 Sense Amplifier Read/Write Circuit m-bit Input/Output Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6 Hierarchical Memory Architecture Row Column Block Input/Output Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7 SRAM Block Diagram [A. Pavlov and M. Sachdev, “Power-Aware SRAM Design and Test”, 2008, Springer.] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8 Conceptual 2-D Memory Organization Address Memory Cell Row Decoder Column decoder Data I/Os Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9 Memory Elements – RAM Generic RAM circuit Bit line conditioning Clocks RAM Cell n-1:k Sense Amp, Column Write k-1:0 Mux, Write Buffers Clocks Address write data read data Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10 RAM – SRAM Cells 6-T SRAM cell word line bit - bit 4-T SRAM cell word line bit - bit Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11 RAM – DRAM Cells 4-T dynamic RAM (DRAM) cell word line bit - bit 3-T DRAM cell Read Write Write Read data data Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12 RAM – DRAM Cells 1-T DRAM cell word line word line Vdd or bit bit Vdd/2 Layout of 1-T DRAM (right) Vdd word line bit Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13 RAM – DRAM Retention Time Write and hold operations in a DRAM cell WL=1 WL=0 on + off + Cs Vs + Cs Vs Input Vdd - - - Write Operation Hold Vs Vmax VDD Vtn Qmax Cs (VDD Vtn ) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14 RAM – DRAM Retention Time Charge leakage in a DRAM Cell Vs(t) WL=0 Vmax IL Minimum logic 1 V1 voltage off + C V (t) s - s t th dQ I ( s ) L dt dV I C ( s ) L s dt V I C ( s ) L s t Cs t h| t | ( )Vs I L Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15 RAM – DRAM Refresh Operation As an example, if IL=1nA, Cs=50fF, and the difference of Vs is 1V, the hold time is 501015 t 1 0.5s h 1109 Memory units must be able to hold data so long as the power is applied. To overcome the charge leakage problem, DRAM arrays employ a refresh operation where the data is periodically read from every cell, amplified, and rewritten. The refresh cycle must be performed on every cell in the array with a minimum refresh frequency of about 1 f refresh 2th Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16 RAM – DRAM Read Operation WL=1 IL on + C C V V bit + s - s f Vbit - Vf Qs CsV s Qs CsV f CbitV f Cs V f ( )Vs Cs Cbit This shows that Vf<Vs for a store logic 1. In practice, Vf is usually reduced to a few tenths of a volt, so that the design of the sense amplifier becomes a critical factor Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17 RAM – SRAM Read Operation Vdd precharge precharge precharge bit, -bit word line word data -bit bit data Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18 RAM – SRAM Read Operation Vdd-Vtn precharge precharge precharge Vdd bit, -bit word line word data -bit bit data Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19 RAM – SRAM Read Operation bit, -bit word data -bit bit load V2 sense + sense - pass V1 sense common pulldown Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20 RAM – Write Operation N 5 N6 write data word write N3 N4 word bit, -bit -bit bit N N write 1 2 cell, -cell write data Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21 RAM – Write Operation -bit bit Pbit 5V -cell cell 0V -write Nbit write ND PD write-data Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22 RAM – Read Stability [A. Pavlov and M. Sachdev, “Power-Aware SRAM Design and Test”, 2008, Springer.] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23 RAM – Write Stability [A. Pavlov and M. Sachdev, “Power-Aware SRAM Design and Test”, 2008, Springer.] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24 RAM – Row Decoder word<3> word<0> word<2> word<1> word<1> word<2> word<0> word<3> a<1> a<0> a<1> a<0> Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25 RAM – Row Decoder word a1 a0 a0 a1 a2 a3 Complementary AND gate Pseudo-nMOS gate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26 RAM – Row Decoder Symbolic layout of row decoder output Vss Vdd Vss Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27 RAM – Row Decoder Symbolic layout of row decoder Vdd output Vss a3 -a3 a2 -a2 a1 -a1 a0 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28 RAM – Row Decoder Predecode circuit word<7> word<6> word<5> word<4> word<3> word<2> word<1> word<0> a2 a1 a0 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29 RAM – Row Decoder Actual implementation a0 a4 a3 a2 a1 word -a0 clk Pseudo-nMOS example a0 word a1 a2 en Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30 RAM – Column Decoder bit<7> bit<6> bit<5> bit<4> selected-data bit<3> bit<2> bit<1> bit<0> to sense amps and write ckts -bit<7> -bit<6> -bit<5> -bit<4> -selected-data -bit<3> -bit<2> -bit<1> -bit<0> a0-a0 a1 -a1 a2 -a2 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31 RAM – Multi-port RAM write read0 read1 -rbit1 -rbit0 -rwr_datarwr_data rbit0 rbit1 write read0 read1 -rbit1 -rwr_datarwr_data rbit0 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32 RAM – Expandable Reg. File Cell wr-b addr<3:0> rd-a addr<3:0> rd-b addr<3:0> write-data read-data 0 read-data 1 write-data write-enable(row) read0 read1 Write-enable (column) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33 Specific Memory – FIFO Two port RAM Write-Data Read-Data Write-Address Read-Address Write-Clock Read-Clock Full Empty FIFO Write (Read) address control design WP (RP) 0 0 1 1 Write (Read) rst 1 clk incrementer Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34 Specific Memory – LIFO LIFO (Stack) Require: Single port RAM One address counter Empty/Full detector Algorithm: Write: write current address Address=Address+1 Read: Address=Address-1 read current address Address Empty: Address=0 Full : Address=FFF… Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35 Specific Memory – LIFO LIFO address control design 0 -1 0 decrementer 1 0 1 1 rst 1 Write clk incrementer Empty Read Write Full Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 36 Specific Memory – SIPO SIPO cell design Read Parallel-data Sh-In Sh-Out Clk -Clk SIPO Read Sh-In Clk Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37 Specific Memory – Tapped Delay Line delay<5> delay<4> delay<3> delay<2> delay<1> delay<0> 0 0 0 0 0 0 din 1 1 1 1 1 1 dout Clk 32-stage SR 16-stage SR 8-stage SR 4-stage SR 2-stage SR 1-stage SR Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 38 Read-Only Memories Read-Only Memories are nonvolatile Retain their contents when power is removed Mask-programmed ROMs use one transistor per bit Presence or absence determines 1 or 0 Advanced Reliable Systems (ARES) Lab.
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