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Chapter 3 Semiconductor Memories

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Chapter 3

Semiconductor Memories

Jin-Fu Li

Department of Electrical Engineering
National Central University
Jungli, Taiwan

Outline

 Introduction  Random Access Memories  Content Addressable Memories  Read Only Memories  Flash Memories

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

Overview of Memory Types

Semiconductor Memories

Read/Write Memory or Random Access Memory (RAM)
Read Only Memory (ROM)
Random Access Memory (RAM)
Non-Random Access Memory (RAM)

•Mask (Fuse) ROM •Programmable ROM (PROM)
•Erasable PROM (EPROM) •Electrically EPROM (EEPROM)
•Flash Memory •Ferroelectric RAM (FRAM) •Magnetic RAM (MRAM)
•FIFO/LIFO •Shift Register •Content Addressable Memory (CAM)
•Static RAM (SRAM) •Dynamic RAM (DRAM) •Register File

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

Memory Elements – Memory Architecture

 Memory elements may be divided into the following categories

Random access memory Serial access memory Content addressable memory

 Memory architecture

2m+k bits

row decoder row decoder

2n-k words

row decoder row decoder

column decoder

k

column mux, sense amp, write buffers

n-bit address
2m-bit data I/Os

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

1-D Memory Architecture

S0
S0

S1 S2 S3

Word0
Word0

S1 S2 S3

Word1 Word2
Word1 Word2

A0 A1

Ak-1
Sn-2

Sn-1
Sn-2 Sn-1

Storage element
Wordn-2 Wordn-1
Wordn-2 Wordn-1

m-bit m-bit

Input/Output
Input/Output

n select signals are reduced to k address signals: A0-Ak-1 n select signals: S0-Sn-1

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

Memory Architecture

S0

Word0
Wordi-1

S1
A0 A1

Ak-1
Sn-1
Wordni-1

A0 Aj-1

Column Decoder Sense Amplifier Read/Write Circuit

m-bit Input/Output

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Advanced Reliable Systems (ARES) Lab.

Hierarchical Memory Architecture

Input/Output

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Advanced Reliable Systems (ARES) Lab.

SRAM Block Diagram

[A. Pavlov and M. Sachdev, “Power-Aware SRAM Design and Test”, 2008, Springer.]

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Advanced Reliable Systems (ARES) Lab.

Conceptual 2-D Memory Organization

Address
Memory Cell

Column decoder
Data I/Os

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

Memory Elements – RAM

Generic RAM circuit

Clocks

Bit line conditioning

RAM Cell n-1:k

Write

Sense Amp, Column Mux, Write Buffers

k-1:0
Clocks
Address

  • write data
  • read data

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

RAM – SRAM Cells

6-T SRAM cell

word line

  • bit
  • - bit

4-T SRAM cell

word line

  • bit
  • - bit

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

RAM – DRAM Cells

4-T dynamic RAM (DRAM) cell

word line

  • bit
  • - bit

3-T DRAM cell

Read Write

Read data
Write data

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

RAM – DRAM Cells

1-T DRAM cell

  • word line
  • word line

Vdd or

  • bit
  • bit

Vdd/2

Layout of 1-T DRAM (right)

Vdd word line

bit

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Advanced Reliable Systems (ARES) Lab.

RAM – DRAM Retention Time

Write and hold operations in a DRAM cell

WL=1
WL=0

+-

on

+-

off

  • Cs
  • Vs

+-

  • Cs
  • Vs

Input Vdd

  • Write Operation
  • Hold

Vs Vmax VDD Vtn Qmax Cs (VDD Vtn )

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

RAM – DRAM Retention Time

Charge leakage in a DRAM Cell

Vs(t)

Vmax V1

WL=0

IL

Minimum logic 1 voltage

+-

off

Cs

Vs(t)

t

th

dQs

IL  ( )

dt dVs dt

IL  Cs ( )
Vs
IL  Cs ( )

t

Cs

th| t | ( )Vs

IL

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

RAM – DRAM Refresh Operation

As an example, if IL=1nA, Cs=50fF, and the difference of Vs is 1V, the hold time is

501015

  • th
  • 1 0.5s

1109

Memory units must be able to hold data so long as the power is applied. To overcome the charge leakage problem, DRAM arrays

employ a refresh operation where the data is periodically read from every cell, amplified, and rewritten.

The refresh cycle must be performed on every cell in the array with a minimum refresh frequency of about

1

f refres h
2th

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Advanced Reliable Systems (ARES) Lab.

RAM – DRAM Read Operation

WL=1

IL

+-

on

  • Cbit
  • Cs
  • Vs
  • Vf

+-

Vbit
Vf

Qs CsV s Qs CsVf CbitVf

Cs
Cs Cbit
Vf  (
)Vs

This shows that Vf<Vs for a store logic 1. In practice, Vf is usually reduced to a few tenths of a volt, so that the design of the sense amplifier becomes a critical factor

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

RAM – SRAM Read Operation

Vdd precharge

precharge bit, -bit precharge word line word

data
- bit bit

data

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

RAM – SRAM Read Operation

Vdd-Vtn precharge

precharge bit, -bit precharge word line

Vdd

word data
- bit bit

data

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

RAM – SRAM Read Operation

bit, -bit word data

  • - bit
  • bit

load

V2

pass

sense - sense +

V1

pulldown

sense common

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

RAM – Write Operation

N5
N6

write data word

write

word

  • N3
  • N4

bit, -bit

  • - bit
  • bit

  • N1
  • N2

write cell, -cell write data

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

RAM – Write Operation

  • - bit
  • bit

Pbit

-cell

cell 0V
5V

- write write

Nbit

  • ND
  • PD

write-data

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Advanced Reliable Systems (ARES) Lab.

RAM – Read Stability

[A. Pavlov and M. Sachdev, “Power-Aware SRAM Design and Test”, 2008, Springer.]

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Advanced Reliable Systems (ARES) Lab.

RAM – Write Stability

[A. Pavlov and M. Sachdev, “Power-Aware SRAM Design and Test”, 2008, Springer.]

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

RAM – Row Decoder

word<3> word<2> word<1> word<0> word<0> word<1> word<2> word<3>

  • a<0>
  • a<0>

  • a<1>
  • a<1>

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

RAM – Row Decoder

word a1

  • a0
  • a0
  • a1
  • a2
  • a3

Complementary AND gate
Pseudo-nMOS gate

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

RAM – Row Decoder

Symbolic layout of row decoder

output

  • Vss
  • Vdd

Vss

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

RAM – Row Decoder

Symbolic layout of row decoder

Vdd output

Vss

  • a3
  • -a3
  • a2
  • -a2
  • a1
  • -a1
  • a0

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

RAM – Row Decoder

Predecode circuit

word<7> word<6> word<5> word<4> word<3> word<2> word<1> word<0>

  • a2
  • a1
  • a0

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

RAM – Row Decoder

Actual implementation

a0 a4 a3 a2 word a1

-a0 clk

Pseudo-nMOS example

  • a0
  • word

  • a1
  • a2
  • en

  • Jin-Fu Li, EE, NCU
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Advanced Reliable Systems (ARES) Lab.

Recommended publications
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  • Data Remanence in Flash Memory Devices

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    Data Remanence in Flash Memory Devices Sergei Skorobogatov University of Cambridge, Computer Laboratory, 15 JJ Thomson Avenue, Cambridge CB3 0FD, United Kingdom [email protected] Abstract. Data remanence is the residual physical representation of data that has been erased or overwritten. In non-volatile programmable devices, such as UV EPROM, EEPROM or Flash, bits are stored as charge in the floating gate of a transistor. After each erase operation, some of this charge remains. Security protection in microcontrollers and smartcards with EEPROM/Flash memories is based on the assumption that information from the memory disappears completely after erasing. While microcontroller manufacturers successfully hardened already their designs against a range of attacks, they still have a common problem with data remanence in floating-gate transistors. Even after an erase operation, the transistor does not return fully to its initial state, thereby allowing the attacker to distinguish between previously programmed and not programmed transistors, and thus restore information from erased memory. The research in this direction is summarised here and it is shown how much information can be extracted from some microcontrollers after their memory has been ‘erased’. 1 Introduction Data remanence as a problem was first discovered in magnetic media [1,2]. Even if the information is overwritten several times on disks and tapes, it can still be possible to extract the initial data. This led to the development of special methods for reliably removing confidential information from magnetic media. Semiconductor memory in security modules was found to have similar prob- lems with reliable data deletion [3,4]. Data remanence affects not only SRAM, but also memory types like DRAM, UV EPROM, EEPROM and Flash [5].