Chapter 3 Semiconductor Memories
Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction Random Access Memories Content Addressable Memories Read Only Memories Flash Memories
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2 Overview of Memory Types
Semiconductor Memories
Read/Write Memory or Random Access Memory (RAM) Read Only Memory (ROM)
Random Access Non-Random Access Memory (RAM) Memory (RAM) •Mask (Fuse) ROM •Programmable ROM (PROM) •Erasable PROM (EPROM) •Static RAM (SRAM) •FIFO/LIFO •Electrically EPROM (EEPROM) •Dynamic RAM (DRAM) •Shift Register •Flash Memory •Register File •Content Addressable •Ferroelectric RAM (FRAM) Memory (CAM) •Magnetic RAM (MRAM)
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3 Memory Elements – Memory Architecture Memory elements may be divided into the following categories Random access memory Serial access memory Content addressable memory Memory architecture 2m+k bits row decoder row decoder 2n-k words row decoder row decoder
column decoder k column mux, n-bit address sense amp, 2m-bit data I/Os write buffers
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4 1-D Memory Architecture
S0 S0 Word0 Word0 S1 S1 Word1 Word1
S2 S2 Word2 Word2 A0 S3 S3 A1 Decoder Ak-1
Sn-2 Storage Sn-2 Wordn-2 element Wordn-2
Sn-1 Sn-1 Wordn-1 Wordn-1
m-bit m-bit Input/Output Input/Output n select signals are reduced n select signals: S0-Sn-1 to k address signals: A0-Ak-1
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5 Memory Architecture
S0 Word0 Wordi-1 S1
A0
A1
Ak-1 Row Decoder
Sn-1 Wordni-1
A 0 Column Decoder Aj-1
Sense Amplifier Read/Write Circuit
m-bit Input/Output
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6 Hierarchical Memory Architecture Row Column Block
Input/Output
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7 SRAM Block Diagram
[A. Pavlov and M. Sachdev, “Power-Aware SRAM Design and Test”, 2008, Springer.]
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8 Conceptual 2-D Memory Organization
Address Memory Cell Row Decoder
Column decoder Data I/Os
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9 Memory Elements – RAM
Generic RAM circuit
Bit line conditioning Clocks
RAM Cell
n-1:k
Sense Amp, Column Write k-1:0 Mux, Write Buffers Clocks
Address write data read data
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10 RAM – SRAM Cells
6-T SRAM cell
word line
bit - bit 4-T SRAM cell
word line
bit - bit
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11 RAM – DRAM Cells
4-T dynamic RAM (DRAM) cell
word line
bit - bit 3-T DRAM cell
Read Write
Write Read data data
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12 RAM – DRAM Cells
1-T DRAM cell
word line word line
Vdd or bit bit Vdd/2
Layout of 1-T DRAM (right) Vdd word line
bit
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13 RAM – DRAM Retention Time
Write and hold operations in a DRAM cell
WL=1 WL=0
on + off + Cs Vs + Cs Vs Input Vdd - - -
Write Operation Hold
s V maxV DDV tnV
maxQ sC DD(V tnV )
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14 RAM – DRAM Retention Time
Charge leakage in a DRAM Cell
Vs(t) WL=0 Vmax
IL Minimum logic 1 V1 voltage off + C V (t) s - s dQ s t I ( ) t L dt h dV I C ( s) L s dt V I C ( s) L s t
C s t h| t | ( )V s I L Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15 RAM – DRAM Refresh Operation
As an example, if IL=1nA, Cs=50fF, and the difference of Vs is 1V, the hold time is 501015 t 1 0.5s h 1109 Memory units must be able to hold data so long as the power is applied. To overcome the charge leakage problem, DRAM arrays employ a refresh operation where the data is periodically read from every cell, amplified, and rewritten.
The refresh cycle must be performed on every cell in the array with a minimum refresh frequency of about
1 f refresh 2th
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16 RAM – DRAM Read Operation
WL=1
IL on + C C V V bit + s - s f Vbit - Vf
Q C V s s s Q s C sV f C bitV f
C s V f ( )V s C s C bit
This shows that Vf Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17 RAM – SRAM Read Operation Vdd precharge precharge precharge bit, -bit word line word data -bit bit data Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18 RAM – SRAM Read Operation Vdd-Vtn precharge precharge precharge Vdd bit, -bit word line word data -bit bit data Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19 RAM – SRAM Read Operation bit, -bit word data -bit bit load V2 sense + sense - pass V1 sense common pulldown Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20 RAM – Write Operation N 5 N6 write data word write N3 N4 word bit, -bit -bit bit N N write 1 2 cell, -cell write data Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21 RAM – Write Operation -bit bit Pbit 5V -cell cell 0V -write Nbit write ND PD write-data Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22 RAM – Read Stability [A. Pavlov and M. Sachdev, “Power-Aware SRAM Design and Test”, 2008, Springer.] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23 RAM – Write Stability [A. Pavlov and M. Sachdev, “Power-Aware SRAM Design and Test”, 2008, Springer.] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24 RAM – Row Decoder word<3> word<0> word<2> word<1> word<1> word<2> word<0> word<3> a<1> a<0> a<1> a<0> Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25 RAM – Row Decoder word a1 a0 a0 a1 a2 a3 Complementary AND gate Pseudo-nMOS gate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26 RAM – Row Decoder Symbolic layout of row decoder output Vss Vdd Vss Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27 RAM – Row Decoder Symbolic layout of row decoder Vdd output Vss a3 -a3 a2 -a2 a1 -a1 a0 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28 RAM – Row Decoder Predecode circuit word<7> word<6> word<5> word<4> word<3> word<2> word<1> word<0> a2 a1 a0 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29 RAM – Row Decoder Actual implementation a0 a4 a3 a2 a1 word -a0 clk Pseudo-nMOS example a0 word a1 a2 en Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30 RAM – Column Decoder bit<7> bit<6> bit<5> bit<4> selected-data bit<3> bit<2> bit<1> bit<0> to sense amps and write ckts -bit<7> -bit<6> -bit<5> -bit<4> -selected-data -bit<3> -bit<2> -bit<1> -bit<0> a0-a0 a1 -a1 a2 -a2 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31 RAM – Multi-port RAM write read0 read1 -rbit1 -rbit0 -rwr_datarwr_data rbit0 rbit1 write read0 read1 -rbit1 -rwr_datarwr_data rbit0 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32 RAM – Expandable Reg. File Cell wr-b addr<3:0> rd-a addr<3:0> rd-b addr<3:0> write-data read-data 0 read-data 1 write-data write-enable(row) read0 read1 Write-enable (column) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33 Specific Memory – FIFO Two port RAM Write-Data Read-Data Write-Address Read-Address Write-Clock Read-Clock Full Empty FIFO Write (Read) address control design WP (RP) 0 0 1 1 Write (Read) rst 1 clk incrementer Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34 Specific Memory – LIFO LIFO (Stack) Require: Single port RAM One address counter Empty/Full detector Algorithm: Write: write current address Address=Address+1 Read: Address=Address-1 read current address Address Empty: Address=0 Full : Address=FFF… Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35 Specific Memory – LIFO LIFO address control design 0 -1 0 decrementer 1 0 1 1 rst 1 Write clk incrementer Empty Read Write Full Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 36 Specific Memory – SIPO SIPO cell design Read Parallel-data Sh-In Sh-Out Clk -Clk SIPO Read Sh-In Clk Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37 Specific Memory – Tapped Delay Line delay<5> delay<4> delay<3> delay<2> delay<1> delay<0> 0 0 0 0 0 0 din 1 1 1 1 1 1 dout Clk 32-stage SR 16-stage SR 8-stage SR 4-stage SR 2-stage SR 1-stage SR Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 38 Read-Only Memories Read-Only Memories are nonvolatile Retain their contents when power is removed Mask-programmed ROMs use one transistor per bit Presence or absence determines 1 or 0 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 39 Non-volatile Memory – ROM 4x4 NOR-type ROM Vdd WL0 GND WL1 WL2 GND WL3 BL0 BL1 BL2 BL3 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 40 Non-volatile Memory – ROM 4x4 NAND-type ROM Vdd BL0 BL1 BL2 BL3 WL0 WL1 WL2 WL3 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 41 ROM Example 4-word x 6-bit ROM Represented with dot diagram Word 0: 010101 Dots indicate 1’s in ROM Word 1: 011001 weak Word 2: 100101 A1 A0 pseudo-nMOS pullups Word 3: 101010 2:4 DEC ROM Array Y5 Y4 Y3 Y2 Y1 Y0 Looks like 6 4-input pseudo-nMOS NORs Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 42 ROM Array Layout Unit cell is 12 x 8 (about 1/10 size of SRAM) Unit Cell Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 43 Row Decoders ROM row decoders must pitch-match with ROM Only a single track per word! Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 44 Complete ROM Layout Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 45 Building Logic with ROMs Use ROM as lookup table containing truth table n inputs, k outputs requires 2n words x k bits Changing function is easy – reprogram ROM Finite State Machine n inputs, k outputs, s bits of state Build with 2n+s x (k+s) bit ROM and (k+s) bit reg inputs n ROM Array 2 n inputs wordlines outputs DEC n ROM k k s s state k outputs Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 46 Specific Memory – CAM Content addressable memories (CAMs) play an important role in digital systems and applications such as communication, networking, data compression, etc. Each storage element of a CAM has the hardware capability to store and compare its contents with the data broadcasted by the control unit CAM types dynamic or static binary or ternary Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 47 Difference Between RAM and CAM Address RAM Data R/W Hit Data CAM Cmd Address Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 48 CAM – Applications CAM architecture CAM Memory Array Data Match NxM-bit words Cache architecture CAM RAM Match 0 Word 0 Match 1 Word 1 CAM Memory Array Match 2 Match 3 Word 2 Data In NxM-bit words Word 3 Match 4 Word 4 Match 5 Word 5 Data I/Os Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 49 CAM – Architecture Comparand Register Mask Register Address Hit Input Memory Array Address Valid Bit Valid Responder Output Address Decoder I/O Register Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 50 CAM – Basic Components Comparand Register It contains the data to be compared with the content of the memory array Mask Register It is used to mask off portions of the data word(s) which do not participate in the operations Memory Array It provides storage and search (compare) medium for data Responder It indicates success or failure of a compare operation Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 51 CAM – Binary Cell NOR-type BCAM cell NAND-type BCAM cell -bit bit -bit bit WL WL -d d -d d M2 M1 M2 M1 Match M3 M3 Match Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 52 CAM – Ternary Cell A ternary CAM (TCAM) cell stores one of the following values 0, 1, and X (don’t care) A typical TCAM cell structure Let (QL,QR)=(CL,CR)=(0,1), (1,0), and (0,0) denote the ternary data 0, 1, and X WL Vss QL QR ML CR CL Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 53 CAM – Ternary Cell NOR-type TCAM cell NAND-type TCAM cell Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 54 CAM – Word Structure bit[0] bit[0] bit[w-1] bit[w-1] W i 10 Vdd P M i 1010 comparison logic Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 55 CAM – Organization CAM circuit Match Data In Read Data (Test) Normal RAM Read/Write Circuitry Hit Match0 Match1 Match2 Match3 precharge Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 56 Non-volatile Memory – Flash Memory Flash memory A nonvolatile, in-system-updateable, high-density memory technology that is per-bit programmable and per-block or per- chip erasable In-system updateable A memory whose contents can be easily modified by the system processor Block size The number of cells that are erased at the same time Cycling The process of programming and erasing a flash memory cell Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 57 Flash Memory – Definition Erase To change a flash memory cell value from 0 to 1 Program To change a flash memory cell value from 1 to 0 Endurance The capability of maintaining the stored information after erase/program/read cycling Retention The capability of keeping the stored information in time Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 58 Basics How can a memory cell commute from one state to the others independently of external condition? One solution is to have a transistor with a threshold voltage that can change repetitively from a high to a low state The high state corresponding to the binary value “1” The low state corresponding to the binary value “0” Threshold voltage of a MOS transistor VT K Q'/Cox K is a constant depending on the gate and substrate material, doping, and gate oxide thickness Q’ is the charge in the gate oxide Cox is the gate oxide capacitance Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 59 Floating Gate Transistor Floating gate (FG) transistor Control Gate CFC Floating Gate CFS CFB CFD Source Drain Substrate Energy band diagram of an FG transistor Substrate Floating Control Gate Gate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 60 Flash Memory – Threshold Voltage When the voltages (VCG & VD) are applied to the control gate and the drain, the voltage at the floating gate (VFG) by capacitive coupling is expressed as Q C C V FG FC V FD V FG C C CG C D total total total Ctotal CFC CFS CFB CFD The minimum control gate voltage required to turn on the control gate is Ctotal QFG CFD VT (CG) VT (FG) VD CFC CFC CFC where VT(FG) is the threshold voltage to turn on the floating gate transistor The difference of threshold voltages between two memory data states (“0” and “1” ) can be expressed as QFG VT (CG) CFC Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 61 Flash Memory – Structures [R. Micheloni, L. Crippa, and A. Marelli, “Inside NAND Flash Memories”, 2010, Springer.] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 62 Flash Memory – Structures Bit line Basic Bit line Basic unit unit Select WL 1 gate (drain) WL 2 WL 1 WL 2 WL 3 WL 3 WL 4 WL N WL N Select gate (source) Source line NOR structure NAND structure Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 63 Flash Memory – Program Operation Program operation of the Intel’s ETOX flash cells (NOR structure) Apply 6V between drain and source Generates hot electrons that are swept across the channel from source to drain Apply 12 V between source and control gate The high voltage on the control gate overcomes the oxide energy barrier, and attracts the electrons across the thin oxide, where they accumulate on the floating gate Called channel hot-electron injection (HEI) +12V Control Gate GND Floating Gate +6V Source Drain Substrate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 64 Flash Memory – Erase Operation Erase operation of the Intel’s ETOX flash cells (NOR structure) Floating the drain, grounding the control gate, and applying 12V to the source A high electric field pulls electrons off the floating gate Called Fowler-Nordheim (FN) tunneling GND Control Gate +12V Floating Gate Source Drain Substrate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 65 Flash Memory – Erase Operation Threshold voltage depends on oxide thickness Flash memory cells in the array may have slightly different gate oxide thickness, and the erase mechanism is not self-limiting After an erase pulse we may have “typical bits” and “fast erasing bits” VT typical bit fast erasing bit 0 log t Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 66 Flash Memory – Read Operation Read operation of the Intel’s ETOX flash cells (NOR structure) Apply 5V on the control gate and drain, and source is grounded In an erased cell, the VC>VT The drain to source current is detected by the sense amplifier In a programmed cell, the VC Source Drain Substrate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 67 Flash Memory – Array [R. Micheloni, L. Crippa, and A. Marelli, “Inside NAND Flash Memories”, 2010, Springer.] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 68 Flash Memory – Dual-Plane NAND Flash [R. Micheloni, L. Crippa, and A. Marelli, “Inside NAND Flash Memories”, 2010, Springer.] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 69 Flash Memory – NAND Flash Organization [C.-W. Chou and J.-F. Li, IEEE VLSI-DAT 2011.] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 70