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Semiconductor Memories SEMICONDUCTOR MEMORIES Digital Integrated Circuits Memory © Prentice Hall 1995 Chapter Overview • Memory Classification • Memory Architectures • The Memory Core • Periphery • Reliability Digital Integrated Circuits Memory © Prentice Hall 1995 Semiconductor Memory Classification RWM NVRWM ROM Random Non-Random EPROM Mask-Programmed Access Access 2 E PROM Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM Digital Integrated Circuits Memory © Prentice Hall 1995 Memory Architecture: Decoders M bits M bits S S0 0 Word 0 Word 0 S1 Word 1 A0 Word 1 S2 Storage Storage s Word 2 Word 2 d Cell A1 Cell r r o e d W o c N AK-1 e S D N-2 Word N-2 Word N-2 SN_1 Word N-1 Word N-1 Input-Output Input-Output (M bits) (M bits) N words => N select signals Decoder reduces # of select signals Too many select signals K = log2N Digital Integrated Circuits Memory © Prentice Hall 1995 Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH 2L-K Bit Line Storage Cell AK r e d Word Line AK+1 o c e D AL-1 w o R M.2K Sense Amplifiers / Drivers Amplify swing to rail-to-rail amplitude A 0 Column Decoder Selects appropriate AK-1 word Input-Output (M bits) Digital Integrated Circuits Memory © Prentice Hall 1995 Hierarchical Memory Architecture Row Address Column Address Block Address Global Data Bus Control Block Selector Global Circuitry Amplifier/Driver I/O Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings Digital Integrated Circuits Memory © Prentice Hall 1995 Memory Timing: Definitions Read Cycle READ Read Access Read Access Write Cycle WRITE Write Access Data Valid DATA Data Written Digital Integrated Circuits Memory © Prentice Hall 1995 Memory Timing: Approaches MSB LSB Address Row Address Bus Column Address RAS Address Address Bus Address transition CAS initiates memory operation RAS-CAS timing DRAM Timing SRAM Timing Multiplexed Adressing Self-timed Digital Integrated Circuits Memory © Prentice Hall 1995 MOS NOR ROM VDD Pull-up devices WL[0] GND WL[1] WL[2] GND WL[3] BL[0] BL[1] BL[2] BL[3] Digital Integrated Circuits Memory © Prentice Hall 1995 MOS NOR ROM Layout Metal1 on top of diffusion WL[0] GND (diffusion) WL[1] Polysilicon Basic cell 10 l x 7 l Metal1 WL[2] 2 l WL[3] Only 1 layer (contact mask) is used to program memory array Programming of the memory can be delayed to one of last process steps Digital Integrated Circuits Memory © Prentice Hall 1995 MOS NOR ROM Layout BL[0] BL[1] BL[2] BL[3] Threshold raising implant WL[0] GND (diffusion) Basic Cell 8.5 l x 7 l Metal1 over diffusion WL[1] Polysilicon WL[2] WL[3] Threshold raising implants disable transistors Digital Integrated Circuits Memory © Prentice Hall 1995 MOS NAND ROM VDD Pull-up devices BL[0] BL[1] BL[2] BL[3] WL[0] WL[1] WL[2] WL[3] All word lines high by default with exception of selected row Digital Integrated Circuits Memory © Prentice Hall 1995 MOS NAND ROM Layout Diffusion Polysilicon Basic cell 5 l x 6 l Threshold lowering implant No contact to VDD or GND necessary; drastically reduced cell size Loss in performance compared to NOR ROM Digital Integrated Circuits Memory © Prentice Hall 1995 Equivalent Transient Model for MOS NOR ROM VDD BL rword Model for NOR ROM WL Cbit cword Word line parasitics Resistance/cell: (7/2) x 10 W/q = 35 W Wire capacitance/cell: (7l ´ 2l) (0.6)2 0.058 + 2 ´ (7l ´ 0.6) ´ 0.043 = 0.65 fF Gate Capacitance/cell: (4l ´ 2l) (0.6)2 1.76 = 5.1 fF. Bit line parasitics: Resistance/cell: (8.5/4) x 0.07 W/q = 0.15 W (which is negligible) Wire capacitance/cell: (8.5l ´ 4l) (0.6)2 0.031 + 2 ´ (8.5l ´ 0.6) ´ 0.044 = 0.83 fF Drain capacitance/cell: ((3l ´ 4l) (0.6)2 ´ 0.3 + 2 ´ 3l ´ 0.6 ´ 0.8) ´ 0.375 + 4l ´ 0.6 ´ 0.43 = 2.6 fF Digital Integrated Circuits Memory © Prentice Hall 1995 Equivalent Transient Model for MOS NAND ROM VDD BL CL rbit Model for NAND ROM rword c WL bit cword Word line parasitics: Resistance/cell: (6/2) x 10 W/q = 30 W Wire capacitance/cell: (6l ´ 2l) (0.6)2 0.058 + 2 ´ (6l ´ 0.6) ´ 0.043 = 0.56 fF Gate Capacitance/cell: (3l ´ 2l) (0.6)2 1.76 = 3.8 fF. Bit line parasitics: Resistance/cell: ~ 10 kW, the average transistor resistance over the range of interest. Wire capacitance/cell: Included in diffusion capacitance Source/Drain capacitance/cell: ((3l ´ 3l) (0.6)2 ´ 0.3 + 2 ´ 3l ´ 0.6 ´ 0.8) ´ 0.375 + (3l ´ 2l) (0.6)2 ´ 1.76 = 5.2 fF Digital Integrated Circuits Memory © Prentice Hall 1995 Propagation Delay of NOR ROM Word line delay Consider the 512´512 case. The delay of the distributed rc-line containing M cells can be approximated using the expressions derived in Chapter 8. 2 2 tword = 0.38 (rword ´ cword) M = 0.38 (35 W ´ (0.65 + 5.1) fF) 512 = 20 nsec Bit line delay Assume a (2.4/1.2) pull-down device and a (8/1.2) pull-up transistor. The bit line switches between 5 V and 2.5 V. Cbit = 512 ´ (2.6 + 0.8) fF = 1.7 pF -6 2 2 IavHL = 1/2 (2.4/0.9) (19.6 10 )((4.25) /2 + (4.25 ´ 3.75 - (3.75) /2)) - 1/2 (8/0.9) (5.3 10-6) (4.25 ´ 1.25 - (1.25)2/2) = 0.36 mA tHL = (1.7 pF ´ 1.25 V) / 0.36 mA = 5.9 nsec The low-to-high response time can be computed using a similar approach. tLH = (1.7 pF ´ 1.25 V) / 0.36 mA = 5.9 nsec Digital Integrated Circuits Memory © Prentice Hall 1995 Decreasing Word Line Delay Driver WL Polysilicon word line Metal word line (a) Driving the word line from both sides Metal bypass WL K cells Polysilicon word line (b) Using a metal bypass (c) Use silicides Digital Integrated Circuits Memory © Prentice Hall 1995 Precharged MOS NOR ROM VDD fpre Precharge devices WL[0] GND WL[1] WL[2] GND WL[3] BL[0] BL[1] BL[2] BL[3] PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design. Digital Integrated Circuits Memory © Prentice Hall 1995 Floating-gate transistor (FAMOS) Floating gate Gate D Source Drain tox G tox S n+ p n+ Substrate (a) Device cross-section (b) Schematic symbol Digital Integrated Circuits Memory © Prentice Hall 1995 Floating-Gate Transistor Programming 20 V 0 V 5 V 20 V 0 V 5 V 10 V® 5 V -5 V -2.5 V S D S D S D Avalanche injection. Removing programming voltage Programming results in leaves charge trapped. higher VT. Digital Integrated Circuits Memory © Prentice Hall 1995 FLOTOX EEPROM Floating gate Gate I Source Drain 20-30 nm -10 V VGD 10 V + + n Substrate n p 10 nm (a) Flotox transistor (b) Fowler-Nordheim I-V characteristic BL WL VDD (c) EEPROM cell during a read operation Digital Integrated Circuits Memory © Prentice Hall 1995 Flash EEPROM Control gate Floating gate erasure Thin tunneling oxide n+ source n+ drain programming p-substrate Digital Integrated Circuits Memory © Prentice Hall 1995 Cross-sections of NVM cells Flash EPROM Courtesy Intel Digital Integrated Circuits Memory © Prentice Hall 1995 Characteristics of State-of-the-art NVM Digital Integrated Circuits Memory © Prentice Hall 1995 Read-Write Memories (RAM) • STATIC (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential • DYNAMIC (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended Digital Integrated Circuits Memory © Prentice Hall 1995 6-transistor CMOS SRAM Cell WL VDD M2 M4 Q Q M6 M5 M1 M3 BL BL Digital Integrated Circuits Memory © Prentice Hall 1995 CMOS SRAM Analysis (Write) WL VDD M4 Q = 0 M6 M5 Q = 1 M1 VDD BL = 1 BL = 0 2 2 VDD V VDD V k æ(V – V )----------- – -----------DD ö = k æ(V – V )----------- – -----------DD ö (W/L) ³ 0.33 (W/L) n, M6èDD Tn 2 8 ø p, M4 èDD Tp 2 8 ø n,M6 p,M4 k V 2 V 2 n, M5 VDD DD DD VDD --------------æ-----------– V æ-----------öö = k æ(V – V )----------- – -----------ö 2 è2 Tnè2 øø n, M1èDD Tn 2 8 ø (W/L)n,M5 ³ 10 (W/L)n,M1 Digital Integrated Circuits Memory © Prentice Hall 1995 CMOS SRAM Analysis (Read) WL VDD M4 BL BL Q = 0 M6 M5 Q = 1 M1 VDD VDD VDD Cbit Cbit 2 2 kn, M5 VDD VDD VDD VDD ---------------æ----------- – V æ------------öö = k æ(V – V )----------- – ------------ö 2 è2 Tnè2 øø n, M1èDD Tn 2 8 ø (W/L)n,M5 £ 10 (W/L)n,M1 (supercedes read constraint) Digital Integrated Circuits Memory © Prentice Hall 1995 6T-SRAM — Layout VDD M2 M4 Q Q M1 M3 GND M5 M6 WL BL BL Digital Integrated Circuits Memory © Prentice Hall 1995 Resistance-load SRAM Cell WL VDD RL RL Q Q M3 M4 BL M1 M2 BL Static power dissipation -- Want RL large Bit lines precharged to VDD to address tp problem Digital Integrated Circuits Memory © Prentice Hall 1995 3-Transistor DRAM Cell BL1 BL2 WWL WWL RWL RWL X X M3 VDD-VT M2 M1 V BL1 DD CS V BL2 VDD-VT D No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = VWWL-VTn Digital Integrated Circuits Memory © Prentice Hall 1995 3T-DRAM — Layout BL2 BL1 GND RWL M3 M2 WWL M1 Digital Integrated Circuits Memory © Prentice Hall 1995 1-Transistor DRAM Cell BL WL Write "1" Read "1" WL M1 C X S GND VDD-VT V BL DD VDD/2 VDD/2 CBL sensing Write: CS is charged or discharged by asserting WL and BL.
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