Lecture 27 Semiconductor Memory: DRAM and Non-Volatile Memory Administrivia

Lecture 27

Semiconductor Memory: DRAM and Non-Volatile Memory

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Administrivia

l Today: Project phase 3 announcement. l Poster Session Tu 5/8 1-4pm » Location BWRC, 2108 Allston Way l Last lecture on Th 5/3 will cover issues in IC design

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1 Lectures

Last l ROM and SRAM Today l Introducing the project phase III l DRAM and Non-volatile

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Project Phase III

A proposed SRAM cell! w/ Control Circuit

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2 Tasks

l Explain the behavior of the cell in its global contents. Provide transient simulations to illustrate. l Identify weakness of the cell in terms of signal integrity and power dissipation. Quantify your statements. l Propose an implementation that improves power dissipation.

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Report l Report » Comparison, Selection, Electrical Design » Cell Layout, Timing Waveforms in SRAM, Simulation » Power and Estimation and Proposal for SRAM power reduction l 3 slides on poster, each of which represents one of the tasks of the previous slide » Explanation of cell operation, comparison, design » Cell Operation in SRAM, Waveforms, Simulation » Proposal of improved SRAM implementation (from a power perspective)

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3 SEMICONDUCTOR MEMORIES

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3-Transistor DRAM Cell

BL1 BL2

WWL WWL

RWL RWL

X X M3 VDD-VT M2 M1 VDD BL1 CS

BL2 VDD-VT DV

No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = VWWL-VTn

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4 3T-DRAM — Layout

BL2 BL1 GND

RWL M3

WWL M1

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1-Transistor DRAM Cell

BL WL Write "1" Read "1" WL

1 M C X S GND VDD-VT

V BL DD

VDD/2 VDD/2 CBL sensing

Write: CS is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance

CS DV= VBL– VPRE = (VBIT– VPRE)------CS + CBL Voltage swing is small; typically around 250 mV.

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5 DRAM Cell Observations

1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the

word lines to a higher value than VDD.

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1-T DRAM Cell

Capacitor

Metal word line M1 word line SiO2 poly Field Oxide n+ n+ Inversion layer poly Diffused induced by bit line plate bias Polysilicon Polysilicon plate (a) Cross-section gate (b) Layout

Used Polysilicon-Diffusion Capacitance Expensive in Area

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6 SEM of poly-diffusion capacitor 1T-DRAM

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Advanced 1T DRAM Cells

Word line Capacitor dielectric layer Insulating Layer Cell plate

Cell Plate Si

Capacitor Insulator Transfer gate Isolation Refilling Poly Storage electrode

Storage Node Poly

Si Substrate 2nd Field Oxide

Trench Cell Stacked-capacitor Cell

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7 Single-to-Differential Conversion

WL BL x Diff. x

+ S.A. _ cell Vref

y y

How to make good Vref?

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Open bitline architecture

R L1 L0 R0 R1 L

VDD SE

BLL BLR

...... CS CS CS SE CS CS CS

dummy dummy cell cell

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8 DRAM Read Process with Dummy Cell

6.0

) 4.0 t l o

V BL (

V 2.0 BL 5.0 0.0 4.0 WL

0 1 2 3 4 5 ) t t (nsec) l 3.0 SE o V

(a) reading a zero ( 2.0 EQ V 6.0 1.0 0.00 1 2 3 4 5 )

t 4.0

l (c) control signals

o BL V (

V 2.0 BL

0.00 1 2 3 4 5 t (nsec) (b) reading a one

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Memory Timing: Definitions

Read Cycle

READ

Read Access Read Access Write Cycle

WRITE

Write Access Data Valid

DATA

Data Written

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9 Memory Timing: Approaches

MSB LSB

Address Row Address Bus Column Address

RAS Address Address Bus

Address transition CAS initiates memory operation

RAS-CAS timing

DRAM Timing SRAM Timing Multiplexed Adressing Self-timed

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Address Transition Detection

VDD

DELAY A0 td ATD ATD

DELAY A1 td

... DELAY

AN-1 td

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10 DRAM Timing

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Floating-gate transistor (FAMOS)

Floating gate Gate D Source Drain

tox G

tox S n+ p n+ Substrate

(a) Device cross-section (b) Schematic symbol

11 Floating-Gate Transistor Programming

20 V 0 V 5 V

20 V 0 V 5 V 10 V® 5 V -5 V -2.5 V

S D S D S D

Avalanche injection. Removing programming voltage Programming results in leaves charge trapped. higher VT.

FLOTOX EEPROM

Floating gate Gate I Source Drain

20-30 nm -10 V VGD 10 V + + n Substrate n p 10 nm (a) Flotox transistor (b) Fowler-Nordheim I-V characteristic

VDD

12 Flash EEPROM

Control gate

Floating gate

erasure Thin tunneling oxide

+ n+ source n drain programming

p-substrate

Cross-sections of NVM cells

13 Characteristics of State-of-the-art NVM

Sense Amplifiers

make DV as small C × DV as possible tp = ------Iav

large small Idea: Use Sense Amplifer

small transition s.a.

input output

14 Differential Sensing - SRAM

VDD VDD V PC V DD DD y M3 M4 y

x M1 M2 x x x BL BL EQ SE M5 SE

WLi (b) Doubled-ended Current Mirror Amplifier

VDD SRAM cell i y y Diff. x Sense x x x Amp y y D D SE

(a) SRAM sensing scheme. (c) Cross-Coupled Amplifier

Latch-Based Sense Amplifier

EQ BL BL

VDD SE

Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point.

15 Single-Ended Cascode Amplifier

VDD

Vcasc

WLC