Chapter 5 Internal Memory Computer Organization and Architecture
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Memory & Devices
Memory & Devices Memory • Random Access Memory (vs. Serial Access Memory) • Different flavors at different levels – Physical Makeup (CMOS, DRAM) – Low Level Architectures (FPM,EDO,BEDO,SDRAM, DDR) • Cache uses SRAM: Static Random Access Memory – No refresh (6 transistors/bit vs. 1 transistor • Main Memory is DRAM: Dynamic Random Access Memory – Dynamic since needs to be refreshed periodically (1% time) – Addresses divided into 2 halves (Memory as a 2D matrix): • RAS or Row Access Strobe • CAS or Column Access Strobe Random-Access Memory (RAM) Key features – RAM is packaged as a chip. – Basic storage unit is a cell (one bit per cell). – Multiple RAM chips form a memory. Static RAM (SRAM) – Each cell stores bit with a six-transistor circuit. – Retains value indefinitely, as long as it is kept powered. – Relatively insensitive to disturbances such as electrical noise. – Faster and more expensive than DRAM. Dynamic RAM (DRAM) – Each cell stores bit with a capacitor and transistor. – Value must be refreshed every 10-100 ms. – Sensitive to disturbances. – Slower and cheaper than SRAM. Semiconductor Memory Types Static RAM • Bits stored in transistor “latches” à no capacitors! – no charge leak, no refresh needed • Pro: no refresh circuits, faster • Con: more complex construction, larger per bit more expensive transistors “switch” faster than capacitors charge ! • Cache Static RAM Structure 1 “NOT ” 1 0 six transistors per bit 1 0 (“flip flop”) 0 1 0/1 = example 0 Static RAM Operation • Transistor arrangement (flip flop) has 2 stable logic states • Write 1. signal bit line: High à 1 Low à 0 2. address line active à “switch” flip flop to stable state matching bit line • Read no need 1. -
DDR and DDR2 SDRAM Controller Compiler User Guide
DDR and DDR2 SDRAM Controller Compiler User Guide 101 Innovation Drive Software Version: 9.0 San Jose, CA 95134 Document Date: March 2009 www.altera.com Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending ap- plications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. UG-DDRSDRAM-10.0 Contents Chapter 1. About This Compiler Release Information . 1–1 Device Family Support . 1–1 Features . 1–2 General Description . 1–2 Performance and Resource Utilization . 1–4 Installation and Licensing . 1–5 OpenCore Plus Evaluation . 1–6 Chapter 2. Getting Started Design Flow . 2–1 SOPC Builder Design Flow . 2–1 DDR & DDR2 SDRAM Controller Walkthrough . -
AXP Internal 2-Apr-20 1
2-Apr-20 AXP Internal 1 2-Apr-20 AXP Internal 2 2-Apr-20 AXP Internal 3 2-Apr-20 AXP Internal 4 2-Apr-20 AXP Internal 5 2-Apr-20 AXP Internal 6 Class 6 Subject: Computer Science Title of the Book: IT Planet Petabyte Chapter 2: Computer Memory GENERAL INSTRUCTIONS: • Exercises to be written in the book. • Assignment questions to be done in ruled sheets. • You Tube link is for the explanation of Primary and Secondary Memory. YouTube Link: ➢ https://youtu.be/aOgvgHiazQA INTRODUCTION: ➢ Computer can store a large amount of data safely in their memory for future use. ➢ A computer’s memory is measured either in Bits or Bytes. ➢ The memory of a computer is divided into two categories: Primary Memory, Secondary Memory. ➢ There are two types of Primary Memory: ROM and RAM. ➢ Cache Memory is used to store program and instructions that are frequently used. EXPLANATION: Computer Memory: Memory plays a very important role in a computer. It is the basic unit where data and instructions are stored temporarily. Memory usually consists of one or more chips on the mother board, or you can say it consists of electronic components that store instructions waiting to be executed by the processor, data needed by those instructions, and the results of processing the data. Memory Units: Computer memory is measured in bits and bytes. A bit is the smallest unit of information that a computer can process and store. A group of 4 bits is known as nibble, and a group of 8 bits is called byte. -
Lecture 27 Semiconductor Memory: DRAM and Non-Volatile Memory Administrivia
Lecture 27 Semiconductor Memory: DRAM and Non-Volatile Memory Digital Integrated Circuits Interconnect © Prentice Hall 2000 Administrivia l Today: Project phase 3 announcement. l Poster Session Tu 5/8 1-4pm » Location BWRC, 2108 Allston Way l Last lecture on Th 5/3 will cover issues in IC design Digital Integrated Circuits Interconnect © Prentice Hall 2000 1 Lectures Last l ROM and SRAM Today l Introducing the project phase III l DRAM and Non-volatile Digital Integrated Circuits Interconnect © Prentice Hall 2000 Project Phase III A proposed SRAM cell! w/ Control Circuit Digital Integrated Circuits Interconnect © Prentice Hall 2000 2 Tasks l Explain the behavior of the cell in its global contents. Provide transient simulations to illustrate. l Identify weakness of the cell in terms of signal integrity and power dissipation. Quantify your statements. l Propose an implementation that improves power dissipation. Digital Integrated Circuits Interconnect © Prentice Hall 2000 Report l Report » Comparison, Selection, Electrical Design » Cell Layout, Timing Waveforms in SRAM, Simulation » Power and Estimation and Proposal for SRAM power reduction l 3 slides on poster, each of which represents one of the tasks of the previous slide » Explanation of cell operation, comparison, design » Cell Operation in SRAM, Waveforms, Simulation » Proposal of improved SRAM implementation (from a power perspective) Digital Integrated Circuits Interconnect © Prentice Hall 2000 3 SEMICONDUCTOR MEMORIES Digital Integrated Circuits Interconnect © Prentice Hall 2000 3-Transistor DRAM Cell BL1 BL2 WWL WWL RWL RWL X X M3 VDD-VT M2 M1 VDD BL1 CS BL2 VDD-VT DV No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = VWWL-VTn Digital Integrated Circuits Interconnect © Prentice Hall 2000 4 3T-DRAM — Layout BL2 BL1 GND RWL M3 M2 WWL M1 Digital Integrated Circuits Interconnect © Prentice Hall 2000 1-Transistor DRAM Cell BL WL Write "1" Read "1" WL 1 M C X S GND VDD-VT V BL DD VDD/2 VDD/2 CBL sensing Write: CS is charged or discharged by asserting WL and BL. -
Nanotechnology Trends in Nonvolatile Memory Devices
IBM Research Nanotechnology Trends in Nonvolatile Memory Devices Gian-Luca Bona [email protected] IBM Research, Almaden Research Center © 2008 IBM Corporation IBM Research The Elusive Universal Memory © 2008 IBM Corporation IBM Research Incumbent Semiconductor Memories SRAM Cost NOR FLASH DRAM NAND FLASH Attributes for universal memories: –Highest performance –Lowest active and standby power –Unlimited Read/Write endurance –Non-Volatility –Compatible to existing technologies –Continuously scalable –Lowest cost per bit Performance © 2008 IBM Corporation IBM Research Incumbent Semiconductor Memories SRAM Cost NOR FLASH DRAM NAND FLASH m+1 SLm SLm-1 WLn-1 WLn WLn+1 A new class of universal storage device : – a fast solid-state, nonvolatile RAM – enables compact, robust storage systems with solid state reliability and significantly improved cost- performance Performance © 2008 IBM Corporation IBM Research Non-volatile, universal semiconductor memory SL m+1 SL m SL m-1 WL n-1 WL n WL n+1 Everyone is looking for a dense (cheap) crosspoint memory. It is relatively easy to identify materials that show bistable hysteretic behavior (easily distinguishable, stable on/off states). IBM © 2006 IBM Corporation IBM Research The Memory Landscape © 2008 IBM Corporation IBM Research IBM Research Histogram of Memory Papers Papers presented at Symposium on VLSI Technology and IEDM; Ref.: G. Burr et al., IBM Journal of R&D, Vol.52, No.4/5, July 2008 © 2008 IBM Corporation IBM Research IBM Research Emerging Memory Technologies Memory technology remains an -
Solving High-Speed Memory Interface Challenges with Low-Cost Fpgas
SOLVING HIGH-SPEED MEMORY INTERFACE CHALLENGES WITH LOW-COST FPGAS A Lattice Semiconductor White Paper May 2005 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000 www.latticesemi.com Introduction Memory devices are ubiquitous in today’s communications systems. As system bandwidths continue to increase into the multi-gigabit range, memory technologies have been optimized for higher density and performance. In turn, memory interfaces for these new technologies pose stiff challenges for designers. Traditionally, memory controllers were embedded in processors or as ASIC macrocells in SoCs. With shorter time-to-market requirements, designers are turning to programmable logic devices such as FPGAs to manage memory interfaces. Until recently, only a few FPGAs supported the building blocks to interface reliably to high-speed, next generation devices, and typically these FPGAs were high-end, expensive devices. However, a new generation of low-cost FPGAs has emerged, providing the building blocks, high-speed FPGA fabric, clock management resources and the I/O structures needed to implement next generation DDR2, QDR2 and RLDRAM memory controllers. Memory Applications Memory devices are an integral part of a variety of systems. However, different applications have different memory requirements. For networking infrastructure applications, the memory devices required are typically high-density, high-performance, high-bandwidth memory devices with a high degree of reliability. In wireless applications, low-power memory is important, especially for handset and mobile devices, while high-performance is important for base-station applications. Broadband access applications typically require memory devices in which there is a fine balance between cost and performance. -
Semiconductor Memories
Semiconductor Memories Prof. MacDonald Types of Memories! l" Volatile Memories –" require power supply to retain information –" dynamic memories l" use charge to store information and require refreshing –" static memories l" use feedback (latch) to store information – no refresh required l" Non-Volatile Memories –" ROM (Mask) –" EEPROM –" FLASH – NAND or NOR –" MRAM Memory Hierarchy! 100pS RF 100’s of bytes L1 1nS SRAM 10’s of Kbytes 10nS L2 100’s of Kbytes SRAM L3 100’s of 100nS DRAM Mbytes 1us Disks / Flash Gbytes Memory Hierarchy! l" Large memories are slow l" Fast memories are small l" Memory hierarchy gives us illusion of large memory space with speed of small memory. –" temporal locality –" spatial locality Register Files ! l" Fastest and most robust memory array l" Largest bit cell size l" Basically an array of large latches l" No sense amps – bits provide full rail data out l" Often multi-ported (i.e. 8 read ports, 2 write ports) l" Often used with ALUs in the CPU as source/destination l" Typically less than 10,000 bits –" 32 32-bit fixed point registers –" 32 60-bit floating point registers SRAM! l" Same process as logic so often combined on one die l" Smaller bit cell than register file – more dense but slower l" Uses sense amp to detect small bit cell output l" Fastest for reads and writes after register file l" Large per bit area costs –" six transistors (single port), eight transistors (dual port) l" L1 and L2 Cache on CPU is always SRAM l" On-chip Buffers – (Ethernet buffer, LCD buffer) l" Typical sizes 16k by 32 Static Memory -
AN-371, Interfacing RC32438 with DDR SDRAM Memory
Interfacing the RC32438 with Application Note DDR SDRAM Memory AN-371 By Kasi Chopperla and Harold Gomard Notes Revision History July 3, 2003: Initial publication. October 23, 2003: Added DDR Loading section. October 29, 2003: Added Passive DDR Termination Scheme for Lightly Loaded Systems section. Introduction The RC32438 is a high performance, general-purpose, integrated processor that incorporates a 32-bit CPU core with a number of peripherals including: – A memory controller supporting DDR SDRAM – A separate memory/peripheral controller interfacing to EPROM, flash and I/O peripherals – Two Ethernet MACs – 32-bit v.2.2 compatible PCI interface – Other generic modules, such as two serial ports, I2C, SPI, interrupt controller, GPIO, and DMA. Internally, the RC32438 features a dual bus system. The CPU bus interfaces directly to the memory controller over a 32-bit bus running at CPU pipeline speed. Since it is not possible to run an external bus at the speed of the CPU, the only way to provide data fast enough to keep the CPU from starving is to use either a wider DRAM or a double data rate DRAM. As the memory technology used on PC motherboards transitions from SDRAM to DDR, the steep ramp- up in the volume of DDR memory being shipped is driving pricing to the point where DDR-based memory subsystems are primed to drop below those of traditional SDRAM modules. Anticipating this, IDT opted to incorporate a double data rate DRAM interface on its RC32438 integrated processor. DDR memory requires a VDD/2 reference voltage and combination series and parallel terminations that SDRAM does not have. -
Design and Implementation of High Speed DDR SDRAM Controller on FPGA
International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 4 Issue 07, July-2015 Design and Implementation of High Speed DDR SDRAM Controller on FPGA Veena H K Dr. A H Masthan Ali M.Tech Student, Department of ECE, Associate Professor, Department of ECE, Sambhram Institute of Technology, Bangalore, Sambhram Institute of Technology, Bangalore, Karnataka, India Karnataka, India Abstract — The dedicated memory controller is important is and column. To point to a location in the memory these three the applications in high end applications where it doesn’t are mandatory. The ACTIVE command signal along with contains microprocessors. Command signals for memory registered address bits point to the specific bank and row to be refresh, read and write operation and SDRAM initialisation has accessed. And column is given by READ/WRITE signal been provided by memory controller. Our work will focus on along with the registered address bits that shall point to a FPGA implementation of Double Data Rate (DDR) SDRAM location for burst access. The DDR SDRAM interface makes controller. The DDR SDRAM controller is located in between higher transfer rates possible compared to single data rate the DDR SDRAM and bus master. The operations of DDR (SDR) SDRAM, by more firm control of the timing of the SDRAM controller is to simplify the SDRAM command data and clock signals. Implementations frequently have to use interface to the standard system read/ write interface and also schemes such as phase-locked loops (PLL) and self- optimization of the access time of read/write cycle. The proposed design will offers effective power utilization, reduce the gate calibration to reach the required timing precision [1][2]. -
Bioshock Infinite
SOUTH AFRICA’S LEADING GAMING, COMPUTER & TECHNOLOGY MAGAZINE VOL 15 ISSUE 10 Reviews Call of Duty: Black Ops II ZombiU Hitman: Absolution PC / PLAYSTATION / XBOX / NINTENDO + MORE The best and wors t of 2012 We give awards to things – not in a traditional way… BioShock Infi nite Loo k! Up in the sky! Editor Michael “RedTide“ James [email protected] Contents Features Assistant editor 24 THE BEST AND WORST OF 2012 Geoff “GeometriX“ Burrows Regulars We like to think we’re totally non-conformist, 8 Ed’s Note maaaaan. Screw the corporations. Maaaaan, etc. So Staff writer 10 Inbox when we do a “Best of [Year X]” list, we like to do it Dane “Barkskin “ Remendes our way. Here are the best, the worst, the weirdest 14 Bytes and, most importantly, the most memorable of all our Contributing editor 41 home_coded gaming experiences in 2012. Here’s to 2013 being an Lauren “Guardi3n “ Das Neves 62 Everything else equally memorable year in gaming! Technical writer Neo “ShockG“ Sibeko Opinion 34 BIOSHOCK INFINITE International correspondent How do you take one of the most infl uential, most Miktar “Miktar” Dracon 14 I, Gamer evocative experiences of this generation and make 16 The Game Stalker it even more so? You take to the skies, of course. Contributors 18 The Indie Investigator Miktar’s played a few hours of Irrational’s BioShock Rodain “Nandrew” Joubert 20 Miktar’s Meanderings Infi nite, and it’s left him breathless – but fi lled with Walt “Shryke” Pretorius 67 Hardwired beautiful, descriptive words. Go read them. Miklós “Mikit0707 “ Szecsei 82 Game Over Pippa -
10. Implementing Double Data Rate I/O Signaling in Cyclone Devices
10. Implementing Double Data Rate I/O Signaling in Cyclone Devices C51010-1.2 Introduction Double data rate (DDR) transmission is used in many applications where fast data transmission is needed, such as memory access and first-in first-out (FIFO) memory structures. DDR uses both edges of a clock to transmit data, which facilitates data transmission at twice the rate of a single data rate (SDR) architecture using the same clock speed. This method also reduces the number of I/O pins required to transmit data. This chapter shows implementations of a double data rate I/O interface using Cyclone® devices. Cyclone devices support DDR input, DDR output, and bidirectional DDR signaling. For more information on using Cyclone devices in applications with DDR SDRAM and FCRAM memory devices, refer to “DDR Memory Support” on page 10–4. Double Data The DDR input implementation shown in Figure 10–1 uses four internal logic element (LE) registers located in the logic array block (LAB) adjacent Rate Input to the DDR input pin. The DDR data is fed to the first two of four registers. One register captures the DDR data present during the rising edge of the clock. The second register captures the DDR data present during the falling edge of the clock. Figure 10–1. Double Data Rate Input Implementation DFF DFF PRN PRN ddr DQ DQ ddr_out_h p_edge_reg ddr_h_sync_reg DFF DFF PRN PRN DQ DQ ddr_out_l NOT n_edge_reg ddr_l_sync_reg clk Altera Corporation 10–1 May 2008 Preliminary Cyclone Device Handbook, Volume 1 The third and fourth registers synchronize the two data streams to the rising edge of the clock. -
Memory We Have Already Mentioned That Digital Computer Works on Stored Programmed Concept Introduced by Von Neumann
www.getmyuni.com Memory We have already mentioned that digital computer works on stored programmed concept introduced by Von Neumann. We use memory to store the information, which includes both program and data. Due to several reasons, we have different kind of memories. We use different kind of memory at different level. The memory of computer is broadly categories into two categories: . Internal and . external Internal memory is used by CPU to perform task and external memory is used to store bulk information, which includes large software and data. Memory is used to store the information in digital form. The memory hierarchy is given by: . Register . Cache Memory . Main Memory . Magnetic Disk . Removable media (Magnetic tape) Register: This is a part of Central Processor Unit, so they reside inside the CPU. The information from main memory is brought to CPU and keep the information in register. Due to space and cost constraints, we have got a limited number of registers in a CPU. These are basically faster devices. Cache Memory: Cache memory is a storage device placed in between CPU and main memory. These are semiconductor memories. These are basically fast memory device, faster than main memory. We cannot have a big volume of cache memory due to its higher cost and some constraints of the CPU. Due to higher cost we cannot replace the whole main memory by faster memory. Generally, the most recently used information is kept in the cache memory. It is brought from the main memory and placed in the cache memory. Now days, we get CPU with internal cache.