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Semiconductor Memories Prof. MacDonald Types of Memories! l" Volatile Memories –" require power supply to retain information –" dynamic memories l" use charge to store information and require refreshing –" static memories l" use feedback (latch) to store information – no refresh required l" Non-Volatile Memories –" ROM (Mask) –" EEPROM –" FLASH – NAND or NOR –" MRAM Memory Hierarchy! 100pS RF 100’s of bytes L1 1nS SRAM 10’s of Kbytes 10nS L2 100’s of Kbytes SRAM L3 100’s of 100nS DRAM Mbytes 1us Disks / Flash Gbytes Memory Hierarchy! l" Large memories are slow l" Fast memories are small l" Memory hierarchy gives us illusion of large memory space with speed of small memory. –" temporal locality –" spatial locality Register Files ! l" Fastest and most robust memory array l" Largest bit cell size l" Basically an array of large latches l" No sense amps – bits provide full rail data out l" Often multi-ported (i.e. 8 read ports, 2 write ports) l" Often used with ALUs in the CPU as source/destination l" Typically less than 10,000 bits –" 32 32-bit fixed point registers –" 32 60-bit floating point registers SRAM! l" Same process as logic so often combined on one die l" Smaller bit cell than register file – more dense but slower l" Uses sense amp to detect small bit cell output l" Fastest for reads and writes after register file l" Large per bit area costs –" six transistors (single port), eight transistors (dual port) l" L1 and L2 Cache on CPU is always SRAM l" On-chip Buffers – (Ethernet buffer, LCD buffer) l" Typical sizes 16k by 32 Static Memory Cell! Wordline! T1! T3! True! Complement! Bit! Bit! Line! T5! T6! Line! T2! T4! Example Chip! LCD Frame Buffer SRAM SRAM cache Register file SRAM Interface !! l" Dirt simple –" clk – only required if registered inputs and/or outputs –" csn – usually negatively active chip select –" wen – usually negatively active write enable –" a – address bus – logarithmically related to number of locations –" d – data in bus – inputs used during writes –" q – data out bus – outputs used during reads l" read – csn active / wen inactive –" data in the byte located by A bus launches out Q bus l" write – csn active / wen active –" D bus value is loaded into memory location determined by A SRAM Operation !! Dual Port SRAM Operation !! l" Two complete single port interfaces –" can read two locations simultaneously –" can write two different locations simultaneously –" can not write one location with two different ports –" Typically requires 2 additional transistors per bit l" (6 to 8 for 33% increase) –" Typically requires 4 bit lines and 2 word lines l" double the global routing than single port Dual Port SRAM Interface !! l" Two merged SRAM interfaces –" clk – if registered inputs and/or outputs –" csnA / csnB – usually negatively active chip select –" wenA / wenB – usually negatively active write enable –" aA / aB – address bus – logarithmically related to number of locations –" dA / dB – data in bus – inputs used during writes –" qA / aB – data out bus – outputs used during reads Two Port Memory Cell! Word Line! Port 0! True! T1! T2! Complement! Bit! Bit! Line ! Line ! Port 0! T5! T6! Port 0! T7! T8! T3! T4! True! Word! Complement! Bit! Line ! Bit! Line ! Port 1! Line ! Port 1! Port 1! Memory Compilers! l" ASIC library providers give logic designers: –" Standard cells - ANDs, NANDs, FLIP-FLOPs, etc –" Chip IOs –" Memory compilers l" single port SRAM, l" dual port SRAM, and l" register files. l" Dial in size and generates verilog, layout, timing. l" DRAM, FLASH not supported Motherboard architecture Dynamic RAM! l" Most dense RAM (1 Gbit chips available) l" Historically, different semiconductor process so built on a separate die l" L3 Cache (old days) and computer main memory l" Requires refresh of data due to leakage l" New push to combine DRAM and logic –" embedded DRAM, eDRAM –" business case hard to close – yields drop DRAM Bit Cells (1T) DRAM used since the early 70s Destructive Read Highest density bitline wordline Cbl Cb DRAM Bit Cells (3T) DRAM used in the early 70s read Non-destructive read bitline write bitline write wordline read wordline DRAM Cross Section DRAM Array DRAM Interface Evolution! l" Asynch DRAM – up until early 90’s l" Synch DRAM – add a clock l" Double Data Rate (DDR) SDRAM l" DDR2 SDRAM – Faster l" Others –" RAMBUS – Intel supported – dead except for PS3 –" graphics versions – specifically for frame buffers –" Mobile SDRAM – low power, good for palm pilots DRAM Read Timings RAS CAS Addr RA1 CA1 RA CA Addr data 1 data 2 DRAM Read Timings (EDO) RAS CAS Addr RA1 CA1 CA Addr data 1 data 2 SDRAM l" Same array as Asynch DRAM l" Add pipelining to data to increase bandwidth l" Requires new clock signal l" Treats RAS, CAS, WE as command inputs l" Replaced by DDR for high performance apps l" Still alive for mobile applications due to power SDRAM Block SDRAM Commands Maskable ROM! l" Most dense ROM l" Tie bit high or low at mask level (metallization) l" Mistakes take weeks to fix with new silicon –" hold lots at metal layer for quick implementation SDRAM Timings command is just the value of CSN, CAS, RAS and WEN together in that cycle address is usually 9-11 bits plus 2 bits for bank address ROM/EEPROM/FLASH! l" Metal Mask ROM l" Electrically erasable programmable ROM l" FLASH is block erasable only EEPROM l" EEPROM can be byte-written but requires extra transistor l" FLASH may take over the world – replacing disk drives with FLASH drives (no moving parts – more reliable). l" Motorola is leader in combining FLASH with logic l" Intel leader in NOR Flash l" Toshiba / Samsung leaders in NAND Flash EPROM! l" Erasable Programmable ROM l" Can be erased by UV light l" Programmed by Hot Carrier Injection l" Obsolete but still mentioned –" only used in EE2369 to provide historical perspective NOR ROM Structure! NOR ROM Structure! NAND ROM Structure! Flash Cross Section! FLASH! FLASH! l" NOR Flash –" less dense (256 Mbit) but provides fast random read access –" Erase FN / Program HEI –" 100,000 write cycles –" Slow erase, fast program and read –" SRAM like interface – give an address – get a byte of data –" great for code memory ( bios, boot-up, cell phone, etc) l" NAND Flash –" More than 2X denser – up to 2Gbit –" Erase FN/ Program FN –" Fast erase, slow program and read –" 1,000,000 write cycles –" IO like interface – not as simple as NOR –" good for data storage – memory cards, IPODs, USB keydrives Flash Cross Section! NOR FLASH! NAND Flash Reading! Tunneling vs Injection! Charge Pumps! l" Flash and EEPROM architectures need unavailable higher voltage for programming (+10v) l" Charge pumps can pump a cap to get high voltage l" DC to DC (higher) converter - without inductors l" Need to consider Vmax across any gate oxide l" Generally cannot provide much power (I*V) l" Charge pumps used for a lot of other things like overdrive voltages and PLLs Basic charge pump concept! Staged Diode Charge Pump! Dickson Charge Pump! V 1 V 2 V3 V 4 Vin V out M d1 M d2 M d3 M d4 M d15 C C C C C out φ φ Improved versions! V 1 V 2 V3 V 4 M D1 M D2 M D3 M D4 M Do Vin V out M s1 M s2 M s3 M s4 M D5 C f C M M N2 M N1 N3 M N4 M M P 2 M M P 1 C P 3 P 4 C C C _1 _2 Stage 1 Stage 2 VDD N2 N3 N4 N1 P1 P3 P7 Cout P2 P4 P8 C1 C3 _1 C2 C4 _2 Clock booster! N2b N2 C1b P2 P1 Outb Out C1 N1b N1 Vo Vob 4 Phase Charge Pump! Clk2 Clk4 Cb1 Cb2 M4 M2 V out Vin M1 M3 M n M 0 C1 C2 C3 Clk1 Clk3 Clk1 CAMs! l" SRAM structure that will do a parallel compare against the contents to provide a hit signal for each row (value) l" Used by caches to find if data is in cache l" Also used for translation look-aside buffers l" Also used in switches / routers to check destination address in ethernet against list of addresses l" Ternary CAMs allow for bit masking the compare Encoders / Decoders input 0 1 2 3 4 5 6 7 3 to 8 000 1 0 0 0 0 0 0 0 line decode 001 0 1 0 0 0 0 0 0 010 0 0 1 0 0 0 0 0 011 0 0 0 1 0 0 0 0 Encoder 100 0 0 0 0 1 0 0 0 101 0 0 0 0 0 1 0 0 Decoder 110 0 0 0 0 0 0 1 0 111 0 0 0 0 0 0 0 1 Read Only Memories - ROM Address Data Out 1 2 2 3 4 5 6 7 n 000 1 0 1 0 1 0 0 0 ROM 001 0 1 0 0 0 0 0 1 010 0 0 1 0 0 1 0 0 011 0 0 1 1 0 0 0 0 m 100 0 0 1 0 0 0 1 1 101 1 1 1 0 0 1 1 1 2n addresses addressed 110 1 1 0 0 0 0 1 0 by n bit m output data bits 111 1 1 1 1 0 0 0 1 Read Only Memories - ROM n n n to 2n 2 decoder Memory array Address m input word lines data output ROM memory array weak pull down word line 2N-1 pd pd pd pd pd pd word line 2N-2 word line 2 word line 1 word line 0 programmed “one” bit lines programmed “zero” data m-1 data m-2 data 2 data1 data0 Random Access Memory (RAM) bitline bitlineN wordline 6 Transistor SRAM cell word lines n+c n Address n to 2n input decoder sram array of 6-t cells 2n c peripheral circuits – column mux, sense amps, write circuitry rnw data in m data out m SRAM Organization!! l" Blocks with unity aspect ratio l" Rows l" Columns l" IO Static Memory Cell! Wordline! T1! T3! True! Complement! Bit! Bit! Line! T5! T6! Line! T2! T4! 4D - Static Memory Cell! Wordline! True! T! C! Complement! Bit! Bit! Line! Line! Cell! SRAM Read Cross-Section! DRAMs precharge! TSA! to half Vdd so PFET enable CSA! required as well! Set! Bit ! Sense! Line ! Isolation! Amp! Isolation Circuit! Bit ! Line! Precharge ! Circuit! Precharge! Wordline! TBL! CBL! T! Cell! SRAM Isolation & Pre-charge Circuits! Sense Amp! Bit ! Bit Switch Circuit! Line ! Isolation! Pre-charge ! Circuit! Bit ! Line ! Pre-charge! Cells! SRAM Sense Amplifier Circuit! DRAMs precharge! to half Vdd so TSA! PFET enable required as well! CSA! Set! Sense! Amp! Bit
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