DOCSLIB.ORG

Semiconductor Memories

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Semiconductor Memories Semiconductor Memories Prof. MacDonald Types of Memories! l" Volatile Memories –" require power supply to retain information –" dynamic memories l" use charge to store information and require refreshing –" static memories l" use feedback (latch) to store information – no refresh required l" Non-Volatile Memories –" ROM (Mask) –" EEPROM –" FLASH – NAND or NOR –" MRAM Memory Hierarchy! 100pS RF 100’s of bytes L1 1nS SRAM 10’s of Kbytes 10nS L2 100’s of Kbytes SRAM L3 100’s of 100nS DRAM Mbytes 1us Disks / Flash Gbytes Memory Hierarchy! l" Large memories are slow l" Fast memories are small l" Memory hierarchy gives us illusion of large memory space with speed of small memory. –" temporal locality –" spatial locality Register Files ! l" Fastest and most robust memory array l" Largest bit cell size l" Basically an array of large latches l" No sense amps – bits provide full rail data out l" Often multi-ported (i.e. 8 read ports, 2 write ports) l" Often used with ALUs in the CPU as source/destination l" Typically less than 10,000 bits –" 32 32-bit fixed point registers –" 32 60-bit floating point registers SRAM! l" Same process as logic so often combined on one die l" Smaller bit cell than register file – more dense but slower l" Uses sense amp to detect small bit cell output l" Fastest for reads and writes after register file l" Large per bit area costs –" six transistors (single port), eight transistors (dual port) l" L1 and L2 Cache on CPU is always SRAM l" On-chip Buffers – (Ethernet buffer, LCD buffer) l" Typical sizes 16k by 32 Static Memory Cell! Wordline! T1! T3! True! Complement! Bit! Bit! Line! T5! T6! Line! T2! T4! Example Chip! LCD Frame Buffer SRAM SRAM cache Register file SRAM Interface !! l" Dirt simple –" clk – only required if registered inputs and/or outputs –" csn – usually negatively active chip select –" wen – usually negatively active write enable –" a – address bus – logarithmically related to number of locations –" d – data in bus – inputs used during writes –" q – data out bus – outputs used during reads l" read – csn active / wen inactive –" data in the byte located by A bus launches out Q bus l" write – csn active / wen active –" D bus value is loaded into memory location determined by A SRAM Operation !! Dual Port SRAM Operation !! l" Two complete single port interfaces –" can read two locations simultaneously –" can write two different locations simultaneously –" can not write one location with two different ports –" Typically requires 2 additional transistors per bit l" (6 to 8 for 33% increase) –" Typically requires 4 bit lines and 2 word lines l" double the global routing than single port Dual Port SRAM Interface !! l" Two merged SRAM interfaces –" clk – if registered inputs and/or outputs –" csnA / csnB – usually negatively active chip select –" wenA / wenB – usually negatively active write enable –" aA / aB – address bus – logarithmically related to number of locations –" dA / dB – data in bus – inputs used during writes –" qA / aB – data out bus – outputs used during reads Two Port Memory Cell! Word Line! Port 0! True! T1! T2! Complement! Bit! Bit! Line ! Line ! Port 0! T5! T6! Port 0! T7! T8! T3! T4! True! Word! Complement! Bit! Line ! Bit! Line ! Port 1! Line ! Port 1! Port 1! Memory Compilers! l" ASIC library providers give logic designers: –" Standard cells - ANDs, NANDs, FLIP-FLOPs, etc –" Chip IOs –" Memory compilers l" single port SRAM, l" dual port SRAM, and l" register files. l" Dial in size and generates verilog, layout, timing. l" DRAM, FLASH not supported Motherboard architecture Dynamic RAM! l" Most dense RAM (1 Gbit chips available) l" Historically, different semiconductor process so built on a separate die l" L3 Cache (old days) and computer main memory l" Requires refresh of data due to leakage l" New push to combine DRAM and logic –" embedded DRAM, eDRAM –" business case hard to close – yields drop DRAM Bit Cells (1T) DRAM used since the early 70s Destructive Read Highest density bitline wordline Cbl Cb DRAM Bit Cells (3T) DRAM used in the early 70s read Non-destructive read bitline write bitline write wordline read wordline DRAM Cross Section DRAM Array DRAM Interface Evolution! l" Asynch DRAM – up until early 90’s l" Synch DRAM – add a clock l" Double Data Rate (DDR) SDRAM l" DDR2 SDRAM – Faster l" Others –" RAMBUS – Intel supported – dead except for PS3 –" graphics versions – specifically for frame buffers –" Mobile SDRAM – low power, good for palm pilots DRAM Read Timings RAS CAS Addr RA1 CA1 RA CA Addr data 1 data 2 DRAM Read Timings (EDO) RAS CAS Addr RA1 CA1 CA Addr data 1 data 2 SDRAM l" Same array as Asynch DRAM l" Add pipelining to data to increase bandwidth l" Requires new clock signal l" Treats RAS, CAS, WE as command inputs l" Replaced by DDR for high performance apps l" Still alive for mobile applications due to power SDRAM Block SDRAM Commands Maskable ROM! l" Most dense ROM l" Tie bit high or low at mask level (metallization) l" Mistakes take weeks to fix with new silicon –" hold lots at metal layer for quick implementation SDRAM Timings command is just the value of CSN, CAS, RAS and WEN together in that cycle address is usually 9-11 bits plus 2 bits for bank address ROM/EEPROM/FLASH! l" Metal Mask ROM l" Electrically erasable programmable ROM l" FLASH is block erasable only EEPROM l" EEPROM can be byte-written but requires extra transistor l" FLASH may take over the world – replacing disk drives with FLASH drives (no moving parts – more reliable). l" Motorola is leader in combining FLASH with logic l" Intel leader in NOR Flash l" Toshiba / Samsung leaders in NAND Flash EPROM! l" Erasable Programmable ROM l" Can be erased by UV light l" Programmed by Hot Carrier Injection l" Obsolete but still mentioned –" only used in EE2369 to provide historical perspective NOR ROM Structure! NOR ROM Structure! NAND ROM Structure! Flash Cross Section! FLASH! FLASH! l" NOR Flash –" less dense (256 Mbit) but provides fast random read access –" Erase FN / Program HEI –" 100,000 write cycles –" Slow erase, fast program and read –" SRAM like interface – give an address – get a byte of data –" great for code memory ( bios, boot-up, cell phone, etc) l" NAND Flash –" More than 2X denser – up to 2Gbit –" Erase FN/ Program FN –" Fast erase, slow program and read –" 1,000,000 write cycles –" IO like interface – not as simple as NOR –" good for data storage – memory cards, IPODs, USB keydrives Flash Cross Section! NOR FLASH! NAND Flash Reading! Tunneling vs Injection! Charge Pumps! l" Flash and EEPROM architectures need unavailable higher voltage for programming (+10v) l" Charge pumps can pump a cap to get high voltage l" DC to DC (higher) converter - without inductors l" Need to consider Vmax across any gate oxide l" Generally cannot provide much power (I*V) l" Charge pumps used for a lot of other things like overdrive voltages and PLLs Basic charge pump concept! Staged Diode Charge Pump! Dickson Charge Pump! V 1 V 2 V3 V 4 Vin V out M d1 M d2 M d3 M d4 M d15 C C C C C out φ φ Improved versions! V 1 V 2 V3 V 4 M D1 M D2 M D3 M D4 M Do Vin V out M s1 M s2 M s3 M s4 M D5 C f C M M N2 M N1 N3 M N4 M M P 2 M M P 1 C P 3 P 4 C C C _1 _2 Stage 1 Stage 2 VDD N2 N3 N4 N1 P1 P3 P7 Cout P2 P4 P8 C1 C3 _1 C2 C4 _2 Clock booster! N2b N2 C1b P2 P1 Outb Out C1 N1b N1 Vo Vob 4 Phase Charge Pump! Clk2 Clk4 Cb1 Cb2 M4 M2 V out Vin M1 M3 M n M 0 C1 C2 C3 Clk1 Clk3 Clk1 CAMs! l" SRAM structure that will do a parallel compare against the contents to provide a hit signal for each row (value) l" Used by caches to find if data is in cache l" Also used for translation look-aside buffers l" Also used in switches / routers to check destination address in ethernet against list of addresses l" Ternary CAMs allow for bit masking the compare Encoders / Decoders input 0 1 2 3 4 5 6 7 3 to 8 000 1 0 0 0 0 0 0 0 line decode 001 0 1 0 0 0 0 0 0 010 0 0 1 0 0 0 0 0 011 0 0 0 1 0 0 0 0 Encoder 100 0 0 0 0 1 0 0 0 101 0 0 0 0 0 1 0 0 Decoder 110 0 0 0 0 0 0 1 0 111 0 0 0 0 0 0 0 1 Read Only Memories - ROM Address Data Out 1 2 2 3 4 5 6 7 n 000 1 0 1 0 1 0 0 0 ROM 001 0 1 0 0 0 0 0 1 010 0 0 1 0 0 1 0 0 011 0 0 1 1 0 0 0 0 m 100 0 0 1 0 0 0 1 1 101 1 1 1 0 0 1 1 1 2n addresses addressed 110 1 1 0 0 0 0 1 0 by n bit m output data bits 111 1 1 1 1 0 0 0 1 Read Only Memories - ROM n n n to 2n 2 decoder Memory array Address m input word lines data output ROM memory array weak pull down word line 2N-1 pd pd pd pd pd pd word line 2N-2 word line 2 word line 1 word line 0 programmed “one” bit lines programmed “zero” data m-1 data m-2 data 2 data1 data0 Random Access Memory (RAM) bitline bitlineN wordline 6 Transistor SRAM cell word lines n+c n Address n to 2n input decoder sram array of 6-t cells 2n c peripheral circuits – column mux, sense amps, write circuitry rnw data in m data out m SRAM Organization!! l" Blocks with unity aspect ratio l" Rows l" Columns l" IO Static Memory Cell! Wordline! T1! T3! True! Complement! Bit! Bit! Line! T5! T6! Line! T2! T4! 4D - Static Memory Cell! Wordline! True! T! C! Complement! Bit! Bit! Line! Line! Cell! SRAM Read Cross-Section! DRAMs precharge! TSA! to half Vdd so PFET enable CSA! required as well! Set! Bit ! Sense! Line ! Isolation! Amp! Isolation Circuit! Bit ! Line! Precharge ! Circuit! Precharge! Wordline! TBL! CBL! T! Cell! SRAM Isolation & Pre-charge Circuits! Sense Amp! Bit ! Bit Switch Circuit! Line ! Isolation! Pre-charge ! Circuit! Bit ! Line ! Pre-charge! Cells! SRAM Sense Amplifier Circuit! DRAMs precharge! to half Vdd so TSA! PFET enable required as well! CSA! Set! Sense! Amp! Bit
Load more

Recommended publications
  • Chapter 3 Semiconductor Memories
    Chapter 3 Semiconductor Memories Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction Random Access Memories Content Addressable Memories Read Only Memories Flash Memories Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2 Overview of Memory Types Semiconductor Memories Read/Write Memory or Random Access Memory (RAM) Read Only Memory (ROM) Random Access Non-Random Access Memory (RAM) Memory (RAM) •Mask (Fuse) ROM •Programmable ROM (PROM) •Erasable PROM (EPROM) •Static RAM (SRAM) •FIFO/LIFO •Electrically EPROM (EEPROM) •Dynamic RAM (DRAM) •Shift Register •Flash Memory •Register File •Content Addressable •Ferroelectric RAM (FRAM) Memory (CAM) •Magnetic RAM (MRAM) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3 Memory Elements – Memory Architecture Memory elements may be divided into the following categories Random access memory Serial access memory Content addressable memory Memory architecture 2m+k bits row decoder row decoder 2n-k words row decoder row decoder column decoder k column mux, n-bit address sense amp, 2m-bit data I/Os write buffers Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4 1-D Memory Architecture S0 S0 Word0 Word0 S1 S1 Word1 Word1 S2 S2 Word2 Word2 A0 S3 S3 A1 Decoder Ak-1 Sn-2 Storage Sn-2 Wordn-2 element Wordn-2 Sn-1 Sn-1 Wordn-1 Wordn-1 m-bit m-bit Input/Output Input/Output n select signals are reduced n select signals: S0-Sn-1 to k address signals: A0-Ak-1 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5 Memory Architecture S0 Word0 Wordi-1 S1 A0 A1 Ak-1 Row Decoder Sn-1 Wordni-1 A 0 Column Decoder Aj-1 Sense Amplifier Read/Write Circuit m-bit Input/Output Advanced Reliable Systems (ARES) Lab.
    [Show full text]
  • Memory & Devices
    Memory & Devices Memory • Random Access Memory (vs. Serial Access Memory) • Different flavors at different levels – Physical Makeup (CMOS, DRAM) – Low Level Architectures (FPM,EDO,BEDO,SDRAM, DDR) • Cache uses SRAM: Static Random Access Memory – No refresh (6 transistors/bit vs. 1 transistor • Main Memory is DRAM: Dynamic Random Access Memory – Dynamic since needs to be refreshed periodically (1% time) – Addresses divided into 2 halves (Memory as a 2D matrix): • RAS or Row Access Strobe • CAS or Column Access Strobe Random-Access Memory (RAM) Key features – RAM is packaged as a chip. – Basic storage unit is a cell (one bit per cell). – Multiple RAM chips form a memory. Static RAM (SRAM) – Each cell stores bit with a six-transistor circuit. – Retains value indefinitely, as long as it is kept powered. – Relatively insensitive to disturbances such as electrical noise. – Faster and more expensive than DRAM. Dynamic RAM (DRAM) – Each cell stores bit with a capacitor and transistor. – Value must be refreshed every 10-100 ms. – Sensitive to disturbances. – Slower and cheaper than SRAM. Semiconductor Memory Types Static RAM • Bits stored in transistor “latches” à no capacitors! – no charge leak, no refresh needed • Pro: no refresh circuits, faster • Con: more complex construction, larger per bit more expensive transistors “switch” faster than capacitors charge ! • Cache Static RAM Structure 1 “NOT ” 1 0 six transistors per bit 1 0 (“flip flop”) 0 1 0/1 = example 0 Static RAM Operation • Transistor arrangement (flip flop) has 2 stable logic states • Write 1. signal bit line: High à 1 Low à 0 2. address line active à “switch” flip flop to stable state matching bit line • Read no need 1.
    [Show full text]
  • File Systems and Disk Layout I/O: the Big Picture
    File Systems and Disk Layout I/O: The Big Picture Processor interrupts Cache Memory Bus I/O Bridge Main I/O Bus Memory Disk Graphics Network Controller Controller Interface Disk Disk Graphics Network 1 Rotational Media Track Sector Arm Cylinder Platter Head Access time = seek time + rotational delay + transfer time seek time = 5-15 milliseconds to move the disk arm and settle on a cylinder rotational delay = 8 milliseconds for full rotation at 7200 RPM: average delay = 4 ms transfer time = 1 millisecond for an 8KB block at 8 MB/s Bandwidth utilization is less than 50% for any noncontiguous access at a block grain. Disks and Drivers Disk hardware and driver software provide basic facilities for nonvolatile secondary storage (block devices). 1. OS views the block devices as a collection of volumes. A logical volume may be a partition ofasinglediskora concatenation of multiple physical disks (e.g., RAID). 2. OS accesses each volume as an array of fixed-size sectors. Identify sector (or block) by unique (volumeID, sector ID). Read/write operations DMA data to/from physical memory. 3. Device interrupts OS on I/O completion. ISR wakes up process, updates internal records, etc. 2 Using Disk Storage Typical operating systems use disks in three different ways: 1. System calls allow user programs to access a “raw” disk. Unix: special device file identifies volume directly. Any process that can open thedevicefilecanreadorwriteany specific sector in the disk volume. 2. OS uses disk as backing storage for virtual memory. OS manages volume transparently as an “overflow area” for VM contents that do not “fit” in physical memory.
    [Show full text]
  • Error Detection and Correction Methods for Memories Used in System-On-Chip Designs
    International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249 – 8958, Volume-8, Issue-2S2, January 2019 Error Detection and Correction Methods for Memories used in System-on-Chip Designs Gunduru Swathi Lakshmi, Neelima K, C. Subhas ABSTRACT— Memory is the basic necessity in any SoC Static Random Access Memory (SRAM): It design. Memories are classified into single port memory and consists of a latch or flipflop to store each bit of multiport memory. Multiport memory has ability to source more memory and it does not required any refresh efficient execution of operation and high speed performance operation. SRAM is mostly used in cache memory when compared to single port. Testing of semiconductor memories is increasing because of high density of current in the and in hand-held devices. It has advantages like chips. Due to increase in embedded on chip memory and memory high speed and low power consumption. It has density, the number of faults grow exponentially. Error detection drawback like complex structure and expensive. works on concept of redundancy where extra bits are added for So, it is not used for high capacity applications. original data to detect the error bits. Error correction is done in Read Only Memory (ROM): It is a non-volatile memory. two forms: one is receiver itself corrects the data and other is It can only access data but cannot modify data. It is of low receiver sends the error bits to sender through feedback. Error detection and correction can be done in two ways. One is Single cost. Some applications of ROM are scanners, ID cards, Fax bit and other is multiple bit.
    [Show full text]
  • DDR and DDR2 SDRAM Controller Compiler User Guide
    DDR and DDR2 SDRAM Controller Compiler User Guide 101 Innovation Drive Software Version: 9.0 San Jose, CA 95134 Document Date: March 2009 www.altera.com Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending ap- plications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. UG-DDRSDRAM-10.0 Contents Chapter 1. About This Compiler Release Information . 1–1 Device Family Support . 1–1 Features . 1–2 General Description . 1–2 Performance and Resource Utilization . 1–4 Installation and Licensing . 1–5 OpenCore Plus Evaluation . 1–6 Chapter 2. Getting Started Design Flow . 2–1 SOPC Builder Design Flow . 2–1 DDR & DDR2 SDRAM Controller Walkthrough .
    [Show full text]
  • AXP Internal 2-Apr-20 1
    2-Apr-20 AXP Internal 1 2-Apr-20 AXP Internal 2 2-Apr-20 AXP Internal 3 2-Apr-20 AXP Internal 4 2-Apr-20 AXP Internal 5 2-Apr-20 AXP Internal 6 Class 6 Subject: Computer Science Title of the Book: IT Planet Petabyte Chapter 2: Computer Memory GENERAL INSTRUCTIONS: • Exercises to be written in the book. • Assignment questions to be done in ruled sheets. • You Tube link is for the explanation of Primary and Secondary Memory. YouTube Link: ➢ https://youtu.be/aOgvgHiazQA INTRODUCTION: ➢ Computer can store a large amount of data safely in their memory for future use. ➢ A computer’s memory is measured either in Bits or Bytes. ➢ The memory of a computer is divided into two categories: Primary Memory, Secondary Memory. ➢ There are two types of Primary Memory: ROM and RAM. ➢ Cache Memory is used to store program and instructions that are frequently used. EXPLANATION: Computer Memory: Memory plays a very important role in a computer. It is the basic unit where data and instructions are stored temporarily. Memory usually consists of one or more chips on the mother board, or you can say it consists of electronic components that store instructions waiting to be executed by the processor, data needed by those instructions, and the results of processing the data. Memory Units: Computer memory is measured in bits and bytes. A bit is the smallest unit of information that a computer can process and store. A group of 4 bits is known as nibble, and a group of 8 bits is called byte.
    [Show full text]
  • Low Voltage, One-Time Programmable, Read-Only Memory
    Features • Fast read access time – 90ns • Dual voltage range operation – Low voltage power supply range, 3.0V to 3.6V, or – Standard power supply range, 5V 10% • Compatible with JEDEC standard Atmel® AT27C512R • Low-power CMOS operation – 20µA max standby (less than 1µA, typical) for VCC = 3.6V – 29mW max active at 5MHz for VCC = 3.6V 512K (64K x 8) • JEDEC standard package – 32-lead PLCC Low Voltage, • High-reliability CMOS technology One-time – 2,000V ESD protection Programmable, – 200mA latchup immunity • Rapid programming algorithm – 100µs/byte (typical) Read-only Memory • CMOS- and TTL-compatible inputs and outputs – JEDEC standard for LVTTL • Integrated product identification code Atmel AT27LV512A • Industrial temperature range • Green (Pb/halide-free) packaging option 1. Description The Atmel AT27LV512A is a high-performance, low-power, low-voltage, 524,288-bit, one- time programmable, read-only memory (OTP EPROM) organized as 64K by 8 bits. It requires only one supply in the range of 3.0 to 3.6V in normal read mode operation, making it ideal for fast, portable systems using battery power. The Atmel innovative design techniques provide fast speeds that rival 5V parts, while keep- ing the low power consumption of a 3.3V supply. At VCC = 3.0V, any byte can be accessed in less than 90ns. With a typical power dissipation of only 18mW at 5MHz and VCC = 3.3V, the AT27LV512A consumes less than one-fifth the power of a standard, 5V EPROM. Standby mode supply current is typically less than 1µA at 3.3V. The AT27LV512A is available in industry-standard, JEDEC-approved, one-time programmable (OTP) PLCC package.
    [Show full text]
  • Embedded DRAM
    Embedded DRAM Raviprasad Kuloor Semiconductor Research and Development Centre, Bangalore IBM Systems and Technology Group DRAM Topics Introduction to memory DRAM basics and bitcell array eDRAM operational details (case study) Noise concerns Wordline driver (WLDRV) and level translators (LT) Challenges in eDRAM Understanding Timing diagram – An example References Slide 1 Acknowledgement • John Barth, IBM SRDC for most of the slides content • Madabusi Govindarajan • Subramanian S. Iyer • Many Others Slide 2 Topics Introduction to memory DRAM basics and bitcell array eDRAM operational details (case study) Noise concerns Wordline driver (WLDRV) and level translators (LT) Challenges in eDRAM Understanding Timing diagram – An example Slide 3 Memory Classification revisited Slide 4 Motivation for a memory hierarchy – infinite memory Memory store Processor Infinitely fast Infinitely large Cycles per Instruction Number of processor clock cycles (CPI) = required per instruction CPI[ ∞ cache] Finite memory speed Memory store Processor Finite speed Infinite size CPI = CPI[∞ cache] + FCP Finite cache penalty Locality of reference – spatial and temporal Temporal If you access something now you’ll need it again soon e.g: Loops Spatial If you accessed something you’ll also need its neighbor e.g: Arrays Exploit this to divide memory into hierarchy Hit L2 L1 (Slow) Processor Miss (Fast) Hit Register Cache size impacts cycles-per-instruction Access rate reduces Slower memory is sufficient Cache size impacts cycles-per-instruction For a 5GHz
    [Show full text]
  • Solving High-Speed Memory Interface Challenges with Low-Cost Fpgas
    SOLVING HIGH-SPEED MEMORY INTERFACE CHALLENGES WITH LOW-COST FPGAS A Lattice Semiconductor White Paper May 2005 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000 www.latticesemi.com Introduction Memory devices are ubiquitous in today’s communications systems. As system bandwidths continue to increase into the multi-gigabit range, memory technologies have been optimized for higher density and performance. In turn, memory interfaces for these new technologies pose stiff challenges for designers. Traditionally, memory controllers were embedded in processors or as ASIC macrocells in SoCs. With shorter time-to-market requirements, designers are turning to programmable logic devices such as FPGAs to manage memory interfaces. Until recently, only a few FPGAs supported the building blocks to interface reliably to high-speed, next generation devices, and typically these FPGAs were high-end, expensive devices. However, a new generation of low-cost FPGAs has emerged, providing the building blocks, high-speed FPGA fabric, clock management resources and the I/O structures needed to implement next generation DDR2, QDR2 and RLDRAM memory controllers. Memory Applications Memory devices are an integral part of a variety of systems. However, different applications have different memory requirements. For networking infrastructure applications, the memory devices required are typically high-density, high-performance, high-bandwidth memory devices with a high degree of reliability. In wireless applications, low-power memory is important, especially for handset and mobile devices, while high-performance is important for base-station applications. Broadband access applications typically require memory devices in which there is a fine balance between cost and performance.
    [Show full text]
  • Via-Programmable Read-Only Memory Design for Full Code Coverage Using a Dynamic Bit-Line Shielding Technique
    Via-Programmable Read-Only Memory Design for Full Code Coverage Using A Dynamic Bit-Line Shielding Technique Meng-Fan Chang1, 2, Ding-Ming Kwai2, and Kuei-Ann Wen1 1 Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan 2 Intellectual Property Library Company, Hsinchu, Taiwan [email protected] Abstract 0-cell 1-cell 0-cell Crosstalk between bit lines leads to read-1 failure Metal-3 (BL) in a high-speed via-programmable read only memory (ROM) and limits the coverage of applicable code Via-2 (Code) patterns. Due to the fluctuations in bit-line intrinsic Metal-2 and coupling capacitances, the amount of noise coupled to a selected bit line may vary, resulting in the Via-1 reduction of sensing margin. In this paper, we propose a dynamic bit-line shielding (DBS) technique, suitable Metal-1 to be implemented in compliable ROM, to eliminate the Contact crosstalk-induced read failure and to achieve full code coverage. Experiments of the 256Kb instances with Diffusion Diffusion Diffusion and without the DBS circuit were undertaken using STI STI STI STI 0.25µm and 0.18µm standard CMOS processes. The test results demonstrate the read-1 failures and Fig. 1. Cross-sectional view of ROM array with via-2 confirm that the DBS technique can remove them codes and metal-3 bit lines. successfully, allowing the ROM to operate under a wide range of supply voltage. sectional view of the memory array with via-2 codes 1. Introduction and metal-3 bit lines. This leads to more severe bit-line crosstalk, since the contact and via at the lower levels Mask-programmable read-only memory (ROM) must be stacked and the metal islands for them to land macros are commonly embedded into system-on-chip upon contribute considerable side-wall capacitances to (SoC) designs today.
    [Show full text]
  • Refresh Operation and Semi-Conductor Rom Memories
    REFRESH OPERATION AND SEMI-CONDUCTOR ROM MEMORIES The Refresh control block periodically generates Refresh, requests, causing the access control block to start a memory cycle in the normal way. This block allows the refresh operation by activating the Refresh Grant line. The access control block arbitrates between Memory Access requests and Refresh requests, with priority to Refresh requests in the case of a tie to ensure the integrity of the stored data. As soon as the Refresh control block receives the Refresh Grant signal, it activates the Refresh line. This causes the address multiplexer to select the Refresh counter as the source and its contents are thus loaded into the row address latches of all memory chips when the RAS signal is activated. During this time the R/ W line may be low, causing an inadvertent write operation. One way to prevent this is to use the Refresh line to control the decoder block to deactivate all the chip select lines. The rest of the refresh cycle is the same as in a normal cycle. At the end, the Refresh control block increments the refresh counter in preparation for the next Refresh cycle. Even though the row address has 8 bits, the Refresh counter need only be 7 bits wide because of the cell organization inside the memory chips. In a 64k x 1 memory chip, the 256x256 cell array actually consists of two 128x256 arrays. The low order 7 bits of the row address select a row from both arrays and thus the row from both arrays is refreshed! Ideally, the refresh operation should be transparent to the CPU.
    [Show full text]
  • EEPROM Emulation
    ...the world's most energy friendly microcontrollers EEPROM Emulation AN0019 - Application Note Introduction This application note demonstrates a way to use the flash memory of the EFM32 to emulate single variable rewritable EEPROM memory through software. The example API provided enables reading and writing of single variables to non-volatile flash memory. The erase-rewrite algorithm distributes page erases and thereby doing wear leveling. This application note includes: • This PDF document • Source files (zip) • Example C-code • Multiple IDE projects 2013-09-16 - an0019_Rev1.09 1 www.silabs.com ...the world's most energy friendly microcontrollers 1 General Theory 1.1 EEPROM and Flash Based Memory EEPROM stands for Electrically Erasable Programmable Read-Only Memory and is a type of non- volatile memory that is byte erasable and therefore often used to store small amounts of data that must be saved when power is removed. The EFM32 microcontrollers do not include an embedded EEPROM module for byte erasable non-volatile storage, but all EFM32s do provide flash memory for non-volatile data storage. The main difference between flash memory and EEPROM is the erasable unit size. Flash memory is block-erasable which means that bytes cannot be erased individually, instead a block consisting of several bytes need to be erased at the same time. Through software however, it is possible to emulate individually erasable rewritable byte memory using block-erasable flash memory. To provide EEPROM functionality for the EFM32s in an application, there are at least two options available. The first one is to include an external EEPROM module when designing the hardware layout of the application.
    [Show full text]