Technology Challenges and Directions of SRAM, DRAM, and eDRAM Cell Scaling in Sub- 20nm Generations
Jai-hoon Sim
SK hynix, Icheon, Korea Outline
1. Nobody is perfect: Main memory & cache memory in the dilemma in sub-20nm era. 2. SRAM Scaling: Diet or Die. 6T SRAM cell scaling crisis & RDF problem. 3. DRAM Scaling: Divide and Rule. Unfinished 1T1C DRAM cell scaling and its technical direction. 4. eDRAM Story: Float like a DRAM & sting like a SRAM. Does logic based DRAM process work? 5. All for one. Reshaping DRAM with logic technology elements. 6. Conclusion.
L1$ L2$ SRAM Higher Speed (< few nS) Working L3$ Better Endurance eDRAM Memory (>1x1016 cycles)
Access Speed Access Stt-RAM
Main Memory DRAM
PcRAM ReRAM Lower Speed
Bigger Size Storage Class Memory NAND
Density 3 Technologies for Cache & Main Memories
SRAM • 6T cell. • Non-destructive read. • Performance driven process Speed technology. eDRAM • Always very fast. • 1T-1C cell. • Destructive read and Write-back needed. • Leakage-Performance compromised process technology. Standby • Smaller than SRAM and faster than Density Power DRAM.
DRAM • 1T-1C cell. • Destructive read and Write-back needed. • Leakage control driven process technology. • Not always fast. • Smallest cell and lowest cost per bit.
4 eDRAM Concept: Performance Gap Filler
SRAM
20-30X
Cell Size Cell eDRAM
DRAM 50-100X
Random Access Speed
• Is there any high density & high speed memory solution that could be 100% integrated into logic SoC?
5 6T-SRAM Cell Operation
VDD
WL WL DVBL
PU Read
PG SN SN WL Icell PD BL VSS BL V SN BL BL DD SN
PD Read Margin: Write PG
PG V Write Margin: SS PU Time 6 DRAM’s Charge Sharing DVBL
VS VBL Charge Sharing Write-back VPP WL CS CBL
V BL DD 1 SN C V C V C C V S DD B 2 DD S B BL
1/2VDD Initial Charge After Charge Sharing DVBL
T d 1 1 V BL SS DVBL VBL VBL VDD 1 CB / CS 2 VBBW
Time 1 1 IL t RET if cell leakage included Cell select DVBL VDD 1 CB / CS 2 CS
7 DRAM Scalability Metrics
BL Cell 1 1 IL t RET WL DVBL VDD CS 1 CB / CS 2 CS
• Cell CS.
CB • Parasitic BL CB. Sensing + • Cell leakage current. - + - • BL offset voltage.
• Cell ION current. DVBL(OFF) C Speed B • WL & BL resistance. BL
8 DRAM’s Bitline Offset Voltage
C K DC D DR DV 0.5 B B n _SA B noise DV BL(OFF) TH _SA n _SA CB n _SA R B
BL BL caused by AC effect (RC mismatches) caused by DC effect
(VTH mismatch) Data pattern dependent
Slope= K fN 2 2 2 2 2 time VTH WKF RDF GOX LER
• Bitline pitch & cell architecture are critical to DVTH_SA. • Offset voltage caused by RC effect increases as pull-down speed becomes
faster. KeDRAM ~ 10xKDRAM. [K. Itoh, VLSI memory chip design, Springer, 2001.] 9 6T-SRAM Cell
VSS VDD BLB PU CPP PD PG WL
WL PG PD PU
BL VDD VSS M1 Pitch VSS VDD BL Unit Cell
WL N-Well
WL Contact 2x CPP 2x Gate Active
BL VDD VSS
= 5x M1 Pitch 10 Contacted Poly Pitch (CPP)
CPP CPP
(CPP-LG)/2
)/2 )/2 [nm]
G
L -
(CPP-LG)/2
CT CT , (CPP Gate G Poly
LG CPP, L CPP, n+ n+
(CPP - LG)/2 = CT/2 + Spacer Design Rule F [nm]
• Gate length LG shrunk only 5nm during past 4 technology generations (65nm to 22nm). • CPP scaling is mostly driven by Spacer & CT scaling and scaled by 30% every 2 years [ same as design rule F].
11 SRAM Cell Scaling Trend
A 2
130nm Cell Size 10 (CPP- LG ) LG
L G
B /(CPP
]
2 90nm
m m
65nm –
L • As (CPP-L )/2 approaches L at G G G
C 45nm [nm/nm] Ratio ) 22nm generation, LG effect is no 32nm more negligible in cell size scaling. 22nm • LG should be shrunk by 20~30% A: no LG shrink (same as @22nm) SRAM SRAM Cell Size [ in 15nm generation to keep
B: LG shrunk by 20%
every generation current cell size scaling trend. C: LG shrunk by 30% every generation
(CPP – LG)/2 [nm] • SRAM cell size correlates well with (CPP – LG)/2 until 22nm generation. • For SRAM cell size = 0.01Xmm2, the CT/2 + Spacer = 8.0nm (equivalent to F = 5nm). 12 VTH Impact on SRAM Scaling
Icell Icell
VTH
32nm VTH
45nm Pass pMOS pMOS Vt 65nm pMOS Vt 180nm 90nm 130nm
1/ WL nMOS Vt [H. Yamauchi, J. STS, Mar. 2009.] nMOS Vt
[K. Kuhn, et al, Intel Tech. J., June 2008.] 13 DRAM’s Scaling Analysis (1): IL=0 Case
IL t RET 0.5VDD CS DVBL (1)
1 CB / CS
[V] When cell leak current = 0, eqn. (1) can be simplified as
DD_MIN V
VDD _ MIN 2DVBL(OFF) (1 CB / CS )
DVBL(OFF) : bitline offset voltage including sense amplifier device mismatch and other electrical mismatches.
CB/CS Ratio
• For decreasing CS value, CB or DVBL(OFF) should be reduced in order to keep same MAT size (# of cells per bitline kept same) under same VDD_MIN condition.
• Maximum CB/CS value could be simply determined by target VDD_MIN and DVBL(OFF) . 14 DRAM’s Scaling Direction
DVBL(OFF) IL Scaling Scaling CB scaling is strongly dependent on cell innovation but is a weak function CB of direct cell size shrink. Prohibited ① If C should be reduced w/o cell innovation, Region S DVBL(OFF) & IL should be improved:
① • Improve SA’s mismatches – DVTH & D.
• Improve DCB & DRB. ② • Junction engineering.
② Decreasing CB as CS scales downs: • New cell innovation, Buried WL.
CS • New materials for BL: Low-K Dielectric, Air Gap, etc.
15 Cell Capacitor Scaling (1)
EOT [Å]
50 SIS or MIS, Concave or Cylinder 40
30 Al2O3
20 MIM, Cylinder
10 HfO2 & Al2O3 7
MIM, Pillar 5 ZrO2 & Al2O3 4
3 High-k Ultra high-k
2000 2002 2004 2006 2008 2010 2012 2014 Year
[Source : ITRS 2000~2010] 16 Cell Capacitor Scaling (2)
Cs [A.U.] Aspect Ratio
6 100 Expected Cs 3Å
5 80 Pillar Cap.
4Å
4 60
3 40
Cylinder Cap.
2 20 A/R ▶ 1 0 70nm 60nm 50nm 40nm 30nm 20nm 10nm [DRAM Technology Node] [S. Cha, IEDM, 2011] 17 Bitline Capacitance Scaling
Reduce BL-WL cap: Buried WL
[T. Schloesser et al., IEDM 2008.]
Reduce BL length: 4F(8F2) 2F(6F2)
8F2 6F2
BL BL 18 Bitline Capacitance Scaling (3) 6F2 8F2 > 8F2
4F2 Number of Cells/BL
3D Capacitor
Ratio
S /C
B 6F2 C +
Buried WL COB
Design Rule [nm] 19 eDRAM Technology Trend
“eDRAM cell = Fast as SRAM cell but small as DRAM cell”
Technologywise: Non-self-aligned cell process. It should be logic technology based. 6-7x bigger cell size. • Logic design rule. but still 3-4x smaller than SRAM. • Logic cell passgate transistor. • Silicided cell junctions. Fast cell read/write access. • Logic transistors for bitline SA & periphery circuits. 100-1000x leakage current. • Low-K/Cu BEOL for bitline and BEOL layers. Shorter retention time. • 3D Cell capacitor module process.
Designwise: fast DRAM design with logic VDD range. • Reduce bitline length (16-64 cells/BL). Fast signal development.
• Improve low VDD margin: VDD or GND bitline sensing.
20 DRAM vs. eDRAM
DRAM eDRAM Process 3 metal DRAM process > 5 metal logic process Technology Cell Size ~ 6F2/cell ~ 30-50F2/cell GOX 5-6nm 2.5-3.5nm Bitline W M1 (Cu) – CUB; W – COB Bitline length > 512 cells/BL 16-32 cells/BL Metal Layers 1(M0) + 3 layers 5-6 layers Cell capacitor Cylinder Cylinder VPP 3.0V < 2.0V VDD 1.2-1.5V 0.9-1.0V Storage junction -- Silicided Leakage current < 1fF/cell@95C ~ 1pA/cell@115C Refresh time 64mS@95C < few mS BL sensing 1/2VDD sensing VDD or GND sensing Read Speed tRCD+tCL=23nS, tRAS+tRP=45nS 3-10nS 21 ML eDRAM Technology: CUB
BL (M1) TE Hole Open
Top Electrode (TE)
Hi-K Dielectric
Stacked Bottom Electrode (BE) Contact
Stacked Contact GC
n+ n+ STI Capacitor
[Y. Yamagata, CICC, 2006.]
eDRAM Capacitor Process Logic FEOL
[[1] Y. Yamagata, CICC, 2006. [2] K. Tu, IEDM, 2011.] 22 Capacitor Under Bitline (CUB) & DT eDRAM
BL BLi+1 Contact
Gate
BLi Active
BLi ISO ISO Pitch
WLi WLi+1 WLi+2 WLi+3
Cell Size ~ 32F2. CPP_ISO CPP_PG
• Cell height is determined by isolation pitch & GC-AA overlay. Height ~ 4F. • Cell width is limited by CPP and poly pitch. Width ~ 8F. • Cell PG device gate length and width limited by retention leakage and operation speed, respectively. PG device Lg = 2F~3F, W = 2F~3F. 23 ML eDRAM Technology: COB+Deep CT
M1 (Cu)
Triple Stacked BLC Contact Capacitor BL (W)
GC [Y. Yamagata, CICC, 2006.] n+ n+ STI
• BL (Tungsten) dedicated metal process equipment required.
• CBL and RBL decoupled with cell capacitance: Good for eDRAM’s low voltage and high speed operation. But cell capacitor height limited by M1 contact’s aspect ratio. For logic part, M1C limits logic’s high speed & low voltage performance. 24 Capacitor Over Bitline (COB) eDRAM
BLi+1
BL BLi+1 Contact Gate BLi Active
BLi
WLi WLi+1 WLi+2 WLi+3 WLi+4
Cell Size ~ 40F2. • Cell height ~ 4F, cell width ~ 10F. • AA space, BL width and BL-SN spacing are the critical rules.
25 SRAM, eDRAM, & DRAM Cell Scaling Trend
SRAM
eDRAM
]
2 DRAM m m 0.0228
0.008 Cell Size [ Size Cell
6F2
0.0006 4F2 Design Rule F [nm] 0.0004 26 Memory Cell Size Factor Trend
190.1 228 167.0 170.9 134.9
123.5 2.85x 3.7x 80 52.5 5.0x 44.6 36.4 27.3
8 Cell Size Factor Factor Size Cell 6 6 6 4
Design Rule F [nm] 27 Memory Market Positioning
L1 Cache
<1nS
L2
Cache
<5nS eDRAM
Speed L3 Cache 3-10nS
<10nS
DRAM
>30nS Memory Size [Mb/mm2] 28 New Memory Technology: Stt-RAM
[S. Chung, IEDM, 2010]
• MTJ (magnetic Tunneling Junction) provides good scalability (<6F2) and high speed performance with data non-volatility and zero retention power.
29 L3 Cache Memory Scenario
CPU
L1/L2 cache CPU SRAM CPU L1/L2 cache CPU SRAM L1/L2 cache SRAM L1/L2 cache SRAM L3 cache + SRAM L3 cache External + eDRAM L3 cache External eDRAM L3 cache DRAM/Stt-RAM
30 Conclusion
1. SRAM cell’s scalability metrics are determined by “genuine” performance
of cell transistors (Ion, Ioff, & VTH).
2. “Divide and rule the DRAM”: Scaling on 1T1C cell and SA VTH could be optimized separately. 3. SRAM is too fat to fit into sub-20nm generation technology. New architecture innovation needed or to be replaced by new technologies in L2$/L3$ applications. 4. DRAM scaling in sub-20nm generations will be continued by innovation in Cb/Cs scaling, Hi-K MiM, & highly matched sense amp device technology. 5. eDRAM’s macro size benefit against SRAM is narrowing down. More matured process & design to be developed.
31 Thank you
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