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One-Transistor Dynamic Random-Access Memory Based on Gate-All-Around Junction-Less Field-Effect Transistor with a Si/Sige Heterostructure

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One-Transistor Dynamic Random-Access Memory Based on Gate-All-Around Junction-Less Field-Effect Transistor with a Si/Sige Heterostructure electronics Article One-Transistor Dynamic Random-Access Memory Based on Gate-All-Around Junction-Less Field-Effect Transistor with a Si/SiGe Heterostructure Young Jun Yoon 1 , Jae Sang Lee 1, Dong-Seok Kim 1, Sang Ho Lee 2 and In Man Kang 2,* 1 Korea Multi-purpose Accelerator Complex, Korea Atomic Energy Research Institute, Gyeongju 38180, Korea; [email protected] (Y.J.Y.); [email protected] (J.S.L.); [email protected] (D.-S.K.) 2 School of Electronic and Electrical Engineering, Kyungpook National University, Daegu 41566, Korea; [email protected] * Correspondence: [email protected]; Tel.: +82-053-950-5513 Received: 19 November 2020; Accepted: 11 December 2020; Published: 13 December 2020 Abstract: This paper presents a one-transistor dynamic random-access memory (1T-DRAM) cell based on a gate-all-around junction-less field-effect transistor (GAA-JLFET) with a Si/SiGe heterostructure for high-density memory applications. The proposed 1T-DRAM achieves the sensing margin using the difference in hole density in the body region between ‘1’ and ‘0’ states. The Si/SiGe heterostructure forms a quantum well in the body and reduces the band-to-band tunneling (BTBT) barrier between the body and drain. Compared with the performances of the 1T-DRAM with Si homo-structure, the proposed 1T-DRAM improves the sensing margin and retention time because its storage ability is enhanced by the quantum well. In addition, the thin BTBT barrier reduced the bias condition for the program operation. The proposed 1T-DRAM showed a high potential for memory applications by obtaining a high read current ratio at ‘1’ and ‘0’ states about 108 and a long retention time above 10 ms. Keywords: junction-less field-effect transistor; gate-all-around; one-transistor dynamic random-access memory; Si/SiGe heterostructure 1. Introduction As the electronics industry continuously expands through various applications, such as smart devices, cloud computing, artificial intelligence, and the Internet of things (IoT), the demand for the scaling of dynamic random-access memory (DRAM) for high-density storage and high-performance rises [1–5]. However, DRAMs typically consist of one-transistor (1T) and one-capacitor (1C). Such devices have a scaling limitation because the relatively large size of the capacitor cannot be reduced while maintaining its charge retention characteristics. Therefore, one-transistor dynamic random-access memory (1T-DRAMs), sometimes called capacitorless DRAMs, because the memory operation is realized using the floating body effect instead of the capacitor, have been studied for next-generation DRAM technology [6–10]. Both a silicon-on-insulator (SOI) single-gate structure [11,12] and a double-gate structure [13,14] can be employed for realizing a 1T-DRAM. However, these structures have many limitations in terms of integration density, price competitiveness, and compatibility with the fabrication process. In this paper, we present a 1T-DRAM based on a gate-all-around junction-less field-effect transistor (GAA-JLFET) with a Si/SiGe heterostructure. The GAA-JLFET is one of the main next-generation structures for improving the chip integration density and performance. The Si/SiGe heterojunction was employed to improve the charge storage ability and reduce the bias conditions of the program operation. Electronics 2020, 9, 2134; doi:10.3390/electronics9122134 www.mdpi.com/journal/electronics Electronics 2020, 9, x FOR PEER REVIEW 2 of 12 Electronicsheterojunction2020, 9, 2134was employed to improve the charge storage ability and reduce the bias conditions2 of 12of the program operation. The memory characteristics such as the sensing margin and retention time Thewere memory obtained characteristics using the 3-dimensional such as the sensing(3D) technology margin and computer-aided retention time design were obtained(TCAD) usingsimulator the 3-dimensionaland were investigated (3D) technology to verify computer-aidedtheir potential for design memory (TCAD) applications. simulator and were investigated to verify their potential for memory applications. 2. Device Structure and Simulation Method 2. DeviceFigure Structure 1a shows and a Simulation 3D schematic Method and cross-sectional diagram of the GAA-JLFET-based 1T-DRAM.Figure1 aThe shows round a 3D nanowire schematic had and cross-sectionala radius of 10 diagram nm and of theconsisted GAA-JLFET-based of the n-type 1T-DRAM. Si/SiGe Theheterostructure. round nanowire A low had Ge a radiuscontent of in 10 SiGe nm of and 0.2 consisted was determined of the n-type from Si the/SiGe lattice heterostructure. mismatch between A low GeSi and content SiGe. in Doping SiGe of concentrations 0.2 was determined of Si drain, from SiGe the latticebody, and mismatch Si source between regions Si were and SiGe.5 × 1019 Doping cm−3, 1 concentrations× 1018 cm−3, and of Si5 drain,× 1019 SiGecm−3, body, respectively. and Si source The body regions region were was 5 10depleted19 cm 3 ,by 1 a 10high-gate18 cm 3, × − × − andwork-function5 1019 cm of3 ,5.0respectively. eV at a gate-to-source The body region voltage was (V depletedGS) of 0 V by (off-state) a high-gate [15,16]. work-function The depleted of 5.0 body eV × − atregion a gate-to-source was used as voltage a hole (V chargeGS) of 0 storage V (off-state) area. [15 A, 16valence]. The depletedband offset body formed region across was used the as Si/SiGe a hole chargeinterface. storage In general, area. A the valence band bandalignment offset of formed the Si/SiGe across heterojunction the Si/SiGe interface. make a In high general, valence the bandband alignmentoffset [17]. ofAs the shown Si/SiGe in heterojunctionFigure 1b, the make1T-DRAM a high obtained valence banda deep off quantumset [17]. Aswell shown in the in SiGe Figure body1b, theregion 1T-DRAM induced obtained by a high a valence deep quantum band offset. well It in is theimportant SiGe body because region the inducedquantum by well a high can improve valence bandthe retention offset. It characteristics is important because of a 1T-DRAM the quantum [18]. The well thickness can improve of the the gate retention dielectric characteristics HfO2 was 2 ofnm. a 1T-DRAMWe designed [18 ].a Thelong thickness channel oflength the gate of 100 dielectric nm. A HfOlong2 channelwas 2 nm. length We designed can improve a long a channelstorage lengthability ofbecause 100 nm. a size A long of storage channel area length is related can improve to a cha annel storage length ability of the because proposed a size 1T-DRAM. of storage Therefore, area is related the tointegration a channel density length ofof the the proposed 1T-DRAM 1T-DRAM. can be improved Therefore, by the designing integration vertical density GAA of theor stacked 1T-DRAM lateral can beGAA improved structures. by designing The gate vertical length GAA (LG) orand stacked underlap lateral length GAA structures.(Lunderlap) were The gate70 nm length and ( L15G) andnm, underlaprespectively. length The (L underlaprole of )the were underlap 70 nm and structure 15 nm, respectively.was to reduce The the role electric of the underlapfield generated structure at wasthe tobody/drain reduce the and electric source/body field generated interfaces, at the which body/drain arose and due source to the/body Shockley-Read-Hall interfaces, which arose(SRH) due and to thetrap-assisted Shockley-Read-Hall tunneling (SRH)(TAT) andrecombination trap-assisted [19–21]. tunneling The (TAT) underlap recombination structure can [19 –increase21]. The the underlap biases structurefor band-to-band can increase tunneling the biases (BTBT), for which band-to-band was used tunneling for forming (BTBT), electron-hole which was pairs used (EHPs) for forming as the electron-holeprogram principle pairs in (EHPs) the 1T-DRAM. as the program The Si/SiGe principle heterojunction in the 1T-DRAM. reduced The the Sibias/SiGe conditions heterojunction for the reducedprogram the operation bias conditions because for its the high program valence operation band of becausefset can itsinduce high valencea higher band BTBT off setrate can than induce a Si ahomojunction higher BTBT [22,23]. rate than a Si homojunction [22,23]. (a) Figure 1. Cont. Electronics 2020, 9, 2134 3 of 12 Electronics 2020, 9, x FOR PEER REVIEW 3 of 12 (b) FigureFigure 1.1. ((aa)) 3D3D schematicschematic andand cross-sectioncross-section ofof thethe GAA-JLFET-basedGAA-JLFET-based 1T-DRAM.1T-DRAM. ((bb)) EnergyEnergy bandband diagramsdiagrams underunder the the gate gate dielectric dielectric of the of GAA-JLFET-based the GAA-JLFET-based 1T-DRAMs 1T-DRAMs with di ffwitherent bodydifferent materials body atmaterialsVGS of 0 at V V andGS ofV 0DS Vof and 0V. VDS of 0 V. InIn order order to to evaluate evaluate the memorythe memory performance, performanc a simulatione, a simulation was carried was outcarried using out TCAD using Sentaurus, TCAD whichSentaurus, is the which simulation is the package simulation offered package by Synopsys offered toby develop Synopsys and to optimized develop semiconductorand optimized devicessemiconductor [24]. Sentaurus devices TCAD [24]. isSentaurus capable of TCAD simulating is ca numericallypable of simulati electricalng andnumerically thermal characteristicselectrical and ofthermal devices. characteristics Various physical of devices. models, Various such as SRHphysical recombination, models, such TAT, as BTBT,SRH re andcombination, quantum confinement TAT, BTBT, eandffects, quantum were employed confinement in the effects, simulation were employed to obtain reliable in the simulation characteristics to obtain of 1T-DRAMs. reliable characteristics In SRH and 5 6 TATof 1T-DRAMs. models, the In electron SRH and and TAT hole lifetimesmodels, the in Si electron were 1 and10− holes and lifetimes 3 10− ins, Si respectively were 1 × 10 [25−5 ].s and In case 3 × 6 × ×7 of SiGe,−6 the electron lifetime of 5 10 s and hole lifetime of 5 10 −6 s were set because the smaller−7 10 s, respectively [25].
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