One-Transistor Dynamic Random-Access Memory Based on Gate-All-Around Junction-Less Field-Eﬀect Transistor with a Si/Sige Heterostructure

electronics

Article One-Transistor Dynamic Random-Access Memory Based on Gate-All-Around Junction-Less Field-Eﬀect Transistor with a Si/SiGe Heterostructure

Young Jun Yoon 1 , Jae Sang Lee 1, Dong-Seok Kim 1, Sang Ho Lee 2 and In Man Kang 2,*

1 Korea Multi-purpose Accelerator Complex, Korea Atomic Energy Research Institute, Gyeongju 38180, Korea; [email protected] (Y.J.Y.); [email protected] (J.S.L.); [email protected] (D.-S.K.) 2 School of Electronic and Electrical Engineering, Kyungpook National University, Daegu 41566, Korea; [email protected] * Correspondence: [email protected]; Tel.: +82-053-950-5513

Received: 19 November 2020; Accepted: 11 December 2020; Published: 13 December 2020

Abstract: This paper presents a one-transistor dynamic random-access memory (1T-DRAM) cell based on a gate-all-around junction-less field-effect transistor (GAA-JLFET) with a Si/SiGe heterostructure for high-density memory applications. The proposed 1T-DRAM achieves the sensing margin using the difference in hole density in the body region between ‘1’ and ‘0’ states. The Si/SiGe heterostructure forms a quantum well in the body and reduces the band-to-band tunneling (BTBT) barrier between the body and drain. Compared with the performances of the 1T-DRAM with Si homo-structure, the proposed 1T-DRAM improves the sensing margin and retention time because its storage ability is enhanced by the quantum well. In addition, the thin BTBT barrier reduced the bias condition for the program operation. The proposed 1T-DRAM showed a high potential for memory applications by obtaining a high read current ratio at ‘1’ and ‘0’ states about 108 and a long retention time above 10 ms.

Keywords: junction-less ﬁeld-eﬀect transistor; gate-all-around; one-transistor dynamic random-access memory; Si/SiGe heterostructure

1. Introduction As the electronics industry continuously expands through various applications, such as smart devices, cloud computing, artificial intelligence, and the Internet of things (IoT), the demand for the scaling of dynamic random-access memory (DRAM) for high-density storage and high-performance rises [1–5]. However, DRAMs typically consist of one-transistor (1T) and one-capacitor (1C). Such devices have a scaling limitation because the relatively large size of the capacitor cannot be reduced while maintaining its charge retention characteristics. Therefore, one-transistor dynamic random-access memory (1T-DRAMs), sometimes called capacitorless DRAMs, because the memory operation is realized using the floating body effect instead of the capacitor, have been studied for next-generation DRAM technology [6–10]. Both a silicon-on-insulator (SOI) single-gate structure [11,12] and a double-gate structure [13,14] can be employed for realizing a 1T-DRAM. However, these structures have many limitations in terms of integration density, price competitiveness, and compatibility with the fabrication process. In this paper, we present a 1T-DRAM based on a gate-all-around junction-less field-effect transistor (GAA-JLFET) with a Si/SiGe heterostructure. The GAA-JLFET is one of the main next-generation structures for improving the chip integration density and performance. The Si/SiGe heterojunction was employed to improve the charge storage ability and reduce the bias conditions of the program operation.

Electronics 2020, 9, 2134; doi:10.3390/electronics9122134 www.mdpi.com/journal/electronics Electronics 2020, 9, x FOR PEER REVIEW 2 of 12

Electronicsheterojunction2020, 9, 2134was employed to improve the charge storage ability and reduce the bias conditions2 of 12of the program operation. The memory characteristics such as the sensing margin and retention time Thewere memory obtained characteristics using the 3-dimensional such as the sensing(3D) technology margin and computer-aided retention time design were obtained(TCAD) usingsimulator the 3-dimensionaland were investigated (3D) technology to verify computer-aidedtheir potential for design memory (TCAD) applications. simulator and were investigated to verify their potential for memory applications. 2. Device Structure and Simulation Method 2. DeviceFigure Structure 1a shows and a Simulation 3D schematic Method and cross-sectional diagram of the GAA-JLFET-based 1T-DRAM.Figure1 aThe shows round a 3D nanowire schematic had and cross-sectionala radius of 10 diagram nm and of theconsisted GAA-JLFET-based of the n-type 1T-DRAM. Si/SiGe Theheterostructure. round nanowire A low had Ge a radiuscontent of in 10 SiGe nm of and 0.2 consisted was determined of the n-type from Si the/SiGe lattice heterostructure. mismatch between A low GeSi and content SiGe. in Doping SiGe of concentrations 0.2 was determined of Si drain, from SiGe the latticebody, and mismatch Si source between regions Si were and SiGe.5 × 1019 Doping cm−3, 1 concentrations× 1018 cm−3, and of Si5 drain,× 1019 SiGecm−3, body, respectively. and Si source The body regions region were was 5 10depleted19 cm 3 ,by 1 a 10high-gate18 cm 3, × − × − andwork-function5 1019 cm of3 ,5.0respectively. eV at a gate-to-source The body region voltage was (V depletedGS) of 0 V by (off-state) a high-gate [15,16]. work-function The depleted of 5.0 body eV × − atregion a gate-to-source was used as voltage a hole (V chargeGS) of 0 storage V (off-state) area. [15 A, 16valence]. The depletedband offset body formed region across was used the as Si/SiGe a hole chargeinterface. storage In general, area. A the valence band bandalignment offset of formed the Si/SiGe across heterojunction the Si/SiGe interface. make a In high general, valence the bandband alignmentoffset [17]. ofAs the shown Si/SiGe in heterojunctionFigure 1b, the make1T-DRAM a high obtained valence banda deep off quantumset [17]. Aswell shown in the in SiGe Figure body1b, theregion 1T-DRAM induced obtained by a high a valence deep quantum band offset. well It in is theimportant SiGe body because region the inducedquantum by well a high can improve valence bandthe retention offset. It characteristics is important because of a 1T-DRAM the quantum [18]. The well thickness can improve of the the gate retention dielectric characteristics HfO2 was 2 ofnm. a 1T-DRAMWe designed [18 ].a Thelong thickness channel oflength the gate of 100 dielectric nm. A HfOlong2 channelwas 2 nm. length We designed can improve a long a channelstorage lengthability ofbecause 100 nm. a size A long of storage channel area length is related can improve to a cha annel storage length ability of the because proposed a size 1T-DRAM. of storage Therefore, area is related the tointegration a channel density length ofof the the proposed 1T-DRAM 1T-DRAM. can be improved Therefore, by the designing integration vertical density GAA of theor stacked 1T-DRAM lateral can beGAA improved structures. by designing The gate vertical length GAA (LG) orand stacked underlap lateral length GAA structures.(Lunderlap) were The gate70 nm length and ( L15G) andnm, underlaprespectively. length The (L underlaprole of )the were underlap 70 nm and structure 15 nm, respectively.was to reduce The the role electric of the underlapfield generated structure at wasthe tobody/drain reduce the and electric source/body field generated interfaces, at the which body/drain arose and due source to the/body Shockley-Read-Hall interfaces, which arose(SRH) due and to thetrap-assisted Shockley-Read-Hall tunneling (SRH)(TAT) andrecombination trap-assisted [19–21]. tunneling The (TAT) underlap recombination structure can [19 –increase21]. The the underlap biases structurefor band-to-band can increase tunneling the biases (BTBT), for which band-to-band was used tunneling for forming (BTBT), electron-hole which was pairs used (EHPs) for forming as the electron-holeprogram principle pairs in (EHPs) the 1T-DRAM. as the program The Si/SiGe principle heterojunction in the 1T-DRAM. reduced The the Sibias/SiGe conditions heterojunction for the reducedprogram the operation bias conditions because for its the high program valence operation band of becausefset can itsinduce high valencea higher band BTBT off setrate can than induce a Si ahomojunction higher BTBT [22,23]. rate than a Si homojunction [22,23].

(a)

Figure 1. Cont.

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(b)

FigureFigure 1.1. ((aa)) 3D3D schematicschematic andand cross-sectioncross-section ofof thethe GAA-JLFET-basedGAA-JLFET-based 1T-DRAM.1T-DRAM. ((bb)) EnergyEnergy bandband diagramsdiagrams underunder the the gate gate dielectric dielectric of the of GAA-JLFET-based the GAA-JLFET-based 1T-DRAMs 1T-DRAMs with di ﬀwitherent bodydifferent materials body atmaterialsVGS of 0 at V V andGS ofV 0DS Vof and 0V. VDS of 0 V.

InIn order order to to evaluate evaluate the memorythe memory performance, performanc a simulatione, a simulation was carried was outcarried using out TCAD using Sentaurus, TCAD whichSentaurus, is the which simulation is the package simulation offered package by Synopsys offered toby develop Synopsys and to optimized develop semiconductorand optimized devicessemiconductor [24]. Sentaurus devices TCAD [24]. isSentaurus capable of TCAD simulating is ca numericallypable of simulati electricalng andnumerically thermal characteristicselectrical and ofthermal devices. characteristics Various physical of devices. models, Various such as SRHphysical recombination, models, such TAT, as BTBT,SRH re andcombination, quantum confinement TAT, BTBT, eandffects, quantum were employed confinement in the effects, simulation were employed to obtain reliable in the simulation characteristics to obtain of 1T-DRAMs. reliable characteristics In SRH and 5 6 TATof 1T-DRAMs. models, the In electron SRH and and TAT hole lifetimesmodels, the in Si electron were 1 and10− holes and lifetimes 3 10− ins, Si respectively were 1 × 10 [25−5 ].s and In case 3 × 6 × ×7 of SiGe,−6 the electron lifetime of 5 10 s and hole lifetime of 5 10 −6 s were set because the smaller−7 10 s, respectively [25]. In case of× SiGe,− the electron lifetime of 5× × 10− s and hole lifetime of 5 × 10 s recombinationwere set because lifetime the insmaller SiGe thanrecombination that in Si can lifetime be caused in SiGe the by than growth that processesin Si can [26be]. caused The lifetimes the by ingrowth Si and processes SiGe were [26]. significantly The lifetimes reduced in by Si theand doping SiGe concentrationwere significantly and inner reduced electric by field.the doping concentration and inner electric field. 3. Results and Discussion 3. ResultsFigure and2 shows Discussion the transfer curves of the 1T-DRAM at the temperatures of 300 K and 358 K. I 16 µ The 1T-DRAMFigure 2 shows exhibited the atransfer low off -statecurves current of the 1T-DRA ( off) of aboutM at the 10− temperaturesA/ m and a of high 300 thresholdK and 358 voltage K. The (Vth) at a drain-to-source voltage (VDS) of 0.1 V. These results indicate that the body region was fully 1T-DRAM exhibited a low off-state current (Ioff) of about 10−16 A/μm and a high threshold voltage depleted by the gate metal at a VGS of 0 V. Here, full depletion can improve the retention characteristics (Vth) at a drain-to-source voltage (VDS) of 0.1 V. These results indicate that the body region was fully of the 1T-DRAM because it reduces the recombination rate. When the temperature rose from 300 K to depleted by the gate metal at a VGS of 0 V. Here, full depletion can improve the retention I 358characteristics K, the off increased of the 1T-DRAM because a because high temperature it reduces leadsthe recombination to faster carrier rate. generation. When the An temperature increase in carrier density can degenerate the retention characteristics due to the increase in recombination. rose from 300 K to 358 K, the Ioff increased because a high temperature leads to faster carrier generation. An increase in carrier density can degenerate the retention characteristics due to the increase in recombination.

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Figure 2. Transfer curves of the GAA-JLFET-based 1T-DRAM1T-DRAM atat temperaturestemperatures ofof 300300 KK andand 358358 K.K. Figure 2. Transfer curves of the GAA-JLFET-based 1T-DRAM at temperatures of 300 K and 358 K. FigureFigure3 shows 3 shows the transientthe transient characteristics characteristics of the of 1T-DRAMs the 1T-DRAMs with Si andwith SiGe Si and bodies SiGe for bodies memory for operationsmemoryFigure operations at3 theshows temperature theat thetransient temperature of 300 characteristics K. The of bias 300 conditions K. of The the bias1T-DRAMs for theconditions operation with for statesSi the and operation are SiGe summarized bodies states for inare memoryTablesummarized1. First, operations the in Table program at the1. First, (writetemperature the ‘1’) program operation of 300 (write K. was The‘1’) performed operationbias conditions using was performed BTBT for the between operation using the BTBT bodystates between and are summarizeddrainthe body regions and in to Table setdrain the 1. regions 1T-DRAMsFirst, the to program set to ‘1’the state, 1T-DRAMs(write as shown‘1’) operation to in ‘1’ Figure state, was4a. asperformed The shown thin tunnelingin using Figure BTBT barrier4a. between The was thin theformedtunneling body when and barrier voltages drain was regionsV formed= to 1.0 whenset V the and voltages 1T-DRAMsV = V1.5G_P V= to− were1.0 ‘1’ V appliedstate, and VasD_P at shown the= 1.5 gate V inwere and Figuredrain, applied 4a. respectively, Theat the thin gate G_P − D_P tunnelingasand shown drain, barrier in respectively, Figure was4b. formed The as tunneling shownwhen voltagesin Figure barrier V G_P4b. width = The−1.0 was tunnelingV and reduced VD_P barrier = by 1.5 the V width were Si /SiGe appliedwas heterojunction.reduced at the bygate the andTheSi/SiGe drain, holes heterojunction. generatedrespectively, by asBTBTThe shown holes were in generated storedFigure under 4b. by The BT the BTtunneling valence were stored bandbarrier ofunder thewidth bodythe was valence region, reduced band while by of the the Si/SiGegeneratedbody heterojunction.region, electrons while ﬂowed theThe generated throughholes generated the electrons drain by region. flowBTBTed Thewere through ‘1’ stored state the ofunder 1T-DRAMdrain the region. valence was The completed band ‘1’ ofstate the by of body region, while the generated electrons flowed through the drain region. The ‘1’ state of storing1T-DRAM the hole was chargescompleted in theby storing body region. the hole The charges read current in the body at ‘1’ region. state (I R1The) of read the current 1T-DRAM at ‘1’ with state 1T-DRAM was completed by storing the hole charges in the body region. The read current at ‘1’ state the(IR1 Si) /ofSiGe the heterojunction 1T-DRAM with increased, the Si/SiGe whereas heterojunctionIR1 of the DRAMincreased, with whereas the Si homojunction IR1 of the DRAM was with almost the (unchanged.IR1Si) homojunctionof the 1T-DRAM This iswas due with almost to the the unchanged.Si/SiGe diﬀerence heterojunction of This the is tunneling due increased,to the barrier difference whereas width. of ThetheIR1 oftunneling 1T-DRAM the DRAM barrier with with thewidth. the Si SihomojunctionThe homojunction 1T-DRAM obtained waswith almost the a Si small unchanged.homojunction hole density This obtained afteris due writing toa smallthe difference a hole ‘1’ operation density of the after because tunneling writing a lowbarrier a ‘1’ BTBT operation width. was Theinducedbecause 1T-DRAM by a alow relatively with BTBT the was thick Si homojunctioninduced tunneling by barrier.a relativelyobtained Thus, athick thesmall 1T-DRAMtunneling hole density withbarrier. after the Thus, Si writing homojunction the a1T-DRAM ‘1’ operation needs with a becausehigherthe Si bias homojunctiona low to writeBTBT the was needs ‘1’ induced operation. a higher by biasa relatively to write thickthe ‘1’ tunneling operation. barrier. Thus, the 1T-DRAM with the Si homojunction needs a higher bias to write the ‘1’ operation.

Figure 3. Transient characteristics of the GAA-JLFET-based 1T-DRAMs with diﬀerent body materials Figure 3. Transient characteristics of the GAA-JLFET-based 1T-DRAMs with different body materials at the temperature of 300 K. The read/hold/write operation time is 10 ns. Figureat the 3. temperature Transient characteristics of 300 K. The of read the/hold/write GAA-JLFET-ba operationsed 1T-DRAMs time is 10 ns.with different body materials at the temperature of 300 K. The read/hold/write operation time is 10 ns.

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Table 1. Bias conditions for memory operations.

Operation Write ‘1’ Write ‘0’ Read Hold Gate Voltage (V ) [V] 1.0 1.0 0.7 0 G − Drain Voltage Electronics 2020, 9, x FOR PEER REVIEW 1.5 1.5 0.1 0 5 of 12 (VD) [V] −

(a) (b)

Figure 4. (a) A schematic diagram and (b) the energy band diagram for the write ‘1’ operation. VG_P

and VD_P are −1.0 V and 1.5 V, respectively.

Table 1. Bias conditions for memory operations.

Operation Write ‘1’ Write ‘0’ Read Hold (a) (b) Gate Voltage (VG) [V] −1.0 1.0 0.7 0 FigureFigure 4.4.( a(a)) A A schematic schematicDrain diagram diagram Voltage and and ( b )( theb) the energy energy band band diagram diagram for the for write the write ‘1’ operation. ‘1’ operation.VG_P andVG_P 1.5 −1.5 0.1 0 Vand VareD_P are1.0 − V1.0 and V and 1.5 V,1.5 respectively. V, respectively. D_P − (VD) [V] It can be removed with the erase (write ‘0’) operation, as shown in Figure5a. Here, the energy It can be removed withTable the erase 1. Bias (write conditions ‘0’) op foreration, memory as operations. shown in Figure 5a. Here, the energy band of the drain was raised by the applied gate voltage (VG_E) of 1.0 V and the drain voltage (VD_E) band of the drain was raisedOperation by the applied gate Write voltage ‘1’ Write (VG_E )‘0’ of 1.0 Read V and Hold the drain voltage (VD_E) of of 1.5 V, as shown in Figure5b. The holes stored in the body region moved through the drain region −1.5− V, as shown in GateFigure Voltage 5b. The (V holesG) [V] stored −1.0 in the body1.0 region moved0.7 through0 the drain region because the potential barrier for the hole was removed by the inﬂuence of the negative VD_E value. because the potential barrier for the hole was removed by the influence of the negative VD_E value. After the write ‘0’ operation,Drain the Voltage hole density in the body region of the 1T-DRAM was smaller than After the write ‘0’ operation, the hole density in1.5 the body− region1.5 of0.1 the 1T-DRAM0 was smaller than that at the ‘1’ state. (VD) [V] that at the ‘1’ state. It can be removed with the erase (write ‘0’) operation, as shown in Figure 5a. Here, the energy band of the drain was raised by the applied gate voltage (VG_E) of 1.0 V and the drain voltage (VD_E) of −1.5 V, as shown in Figure 5b. The holes stored in the body region moved through the drain region because the potential barrier for the hole was removed by the influence of the negative VD_E value. After the write ‘0’ operation, the hole density in the body region of the 1T-DRAM was smaller than that at the ‘1’ state.

(a) (b)

FigureFigure 5. 5.( a()a A) A schematic schematic diagram diagram and and (b) ( theb) the energy energy band band diagram diagram for the for write the write ‘0’ operation. ‘0’ operation.VG_E and VG_E Vand VareD_E 1.0 are V 1.0 and V and1.5 − V,1.5 respectively. V, respectively. D_E − Here, the difference in hole density between ‘1’ and ‘0’ states induced the changing depletion region in the center of the body, as shown in Figure 6a. At the ‘1’ state, the potential barrier height (a) (b)

Figure 5. (a) A schematic diagram and (b) the energy band diagram for the write ‘0’ operation. VG_E

and VD_E are 1.0 V and −1.5 V, respectively.

Here, the difference in hole density between ‘1’ and ‘0’ states induced the changing depletion region in the center of the body, as shown in Figure 6a. At the ‘1’ state, the potential barrier height

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ElectronicsHere, 2020 the, 9, dix FORfference PEER inREVIEW hole density between ‘1’ and ‘0’ states induced the changing depletion6 of 12 region in the center of the body, as shown in Figure6a. At the ‘1’ state, the potential barrier height was reducedwas reduced because because the stored the stored holes removedholes removed the depletion the depletion area from area the fr centerom the of center the body, of the as shownbody, inas Figureshown6 b.in VariationsFigure 6b. Variations in the current in the were current caused were by thecaused di ff erenceby the indifference the potential in the barrier potential heights barrier at ‘1’heights and ‘0’ at states.‘1’ and As ‘0’ shown states. byAs theshown electron by the and electron hole density and hole distribution density distribution in Figure6b,c, in theFigures electron 6b,c, densitythe electron in the density center ofin the bodycenter at of the the ‘1’ body state at is the higher ‘1’ state than is that higher at the than ‘0’ statethat at because the ‘0’ thestate depletion because regionthe depletion was reduced region by was a high reduced hole by density. a high Both hole hole dens andity. electronBoth hole densities and electron at the densities ‘0’ state were at the low. ‘0’ ThestateIR1 wereof 1T-DRAM low. The I isR1 higherof 1T-DRAM than that is higher at the ‘0’ than state that (IR0 at) the due ‘0’ to state the lowering (IR0) due of to the the potential lowering barrier. of the Aspotential a result, barrier. the sensing As a result, margin the of thesensing 1T-DRAM margin with of the the 1T-DRAM SiGe body iswith 0.39 theµA SiGe/µm atbody the biasis 0.39 condition μA/μm ofat thethe readbias operationcondition (gateof the voltage read operationVG_R = 0.7 (gate V and voltage drain V voltageG_R = 0.7V VD_R and= drain0.1 V). voltage The sensing VD_R = margin 0.1 V). wasThe definedsensing asmargin the di ffwaserence defined between as theIR1 differenceand IR0. The between 1T-DRAM IR1 and with IR0 the. The SiGe 1T-DRAM body achieved with the a higher SiGe sensingbody achieved margin a than higher the 1T-DRAMsensing margin with thethan Si the body 1T because-DRAM ofwith the the effi Siciency body of because BTBT and of the the efficiency presence ofof theBTBT quantum and the well. presence In addition, of the quantumIR1 and IR0 well.in the In addition, proposed I 1T-DRAMR1 and IR0 in are the easily proposed distinguishable 1T-DRAM due are toeasily a high distinguishableIR1/IR0 ratio of due 22.3. to a high IR1/IR0 ratio of 22.3.

(a)

(b)

Figure 6. Cont.

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(c) (d) Figure 6. (a) A schematic(c) diagram and (b) the energy band diagrams(d) for the read ‘1’ and ‘0’ operations. Simulated results for (c) the hole density distribution and (d) the electron density FigureFigure 6.6.( a()a A) A schematic schematic diagram diagram and and (b) the (b) energy the energy band diagramsband diagrams for the readfor ‘1’the and read ‘0’ operations.‘1’ and ‘0’ distribution for the read ‘1’ and ‘0’ operations are also provided. VG_R and VD_R are 0.7 V and 0.1 V, Simulatedoperations. results Simulated for (c )results the hole for density (c) the distribution hole density and (distributiond) the electron and density (d) the distribution electron density for the respectively. readdistribution ‘1’ and ‘0’for operations the read ‘1’ are and also ‘0’ provided. operationsVG_R are andalsoV provided.D_R are 0.7 V VG_R and and 0.1 VD_R V, respectively.are 0.7 V and 0.1 V, respectively. Figure 7 shows the read currents IR at ‘1’ and ‘0’ states as functions of VG_R. When VG_R was 0.2 V, Figure7 shows the read currents IR at ‘1’ and ‘0’ states as functions of VG_R. When VG_R was 0.2 V, the 1T-DRAM obtained a very high IR1/IR0 ratio of about8 108. As VG_R increased, IR0 rose gradually the 1T-DRAMFigure 7 shows obtained the aread very currents high IR1 IR/ IatR0 ‘1’ratio and of ‘0’ about states 10 as. functions As VG_R increased,of VG_R. WhenIR0 roseVG_R graduallywas 0.2 V, because a high VG_R formed a channel. When a VG_R above 0.8 V was applied, the difference between becausethe 1T-DRAM a high VobtainedG_R formed a very a channel. high IR1 When/IR0 ratio a V G_Rof aboutabove 10 0.88. VAs was VG_R applied, increased, thedi IR0ﬀ erencerose gradually between IR1 and IR0 disappeared because the storage region was removed with the depletion region. IbecauseR1 and I R0a highdisappeared VG_R formed because a channel. the storage When region a VG_R was above removed 0.8 V was with applied, the depletion the difference region. between IR1 and IR0 disappeared because the storage region was removed with the depletion region.

Figure 7. Read currents IR1 and IR0 as functions of VG_R at the temperature of 300 K. Figure 7. Read currents IR1 and IR0 as functions of VG_R at the temperature of 300 K.

Figure8aFigure shows 7. the ReadIR1 currentsand IR0 IR1of and the IR0 1T-DRAM as functions as of functions VG_R at the of temperature hold time at of the 300 temperatures K. of Figure 8a shows the IR1 and IR0 of the 1T-DRAM as functions of hold time at the temperatures of 300 K and 358 K. At the former temperature, the IR1 and IR0 values were maintained for a long time. 300 K and 358 K. At the former temperature, the IR1 and IR0 values were maintained for a long time. TwoFigure factors 8a helped shows to the achieve IR1 and such IR0 of excellent the 1T-DRAM retention as functions characteristics. of hold The time Si at/SiGe the heterostructuretemperatures of Two factors helped to achieve such excellent retention characteristics. The Si/SiGe heterostructure quantum300 K and well 358 suppressedK. At the former the di temperature,ffusion of the the stored IR1 and hole IR0charges, values were as shown maintained in Figure for 8ab, long and time. the quantum well suppressed the diffusion of the stored hole charges, as shown in Figure 8b, and the underlapTwo factors structure helped minimized to achieve thesuch carrier excellent recombination retention characteristics. and generation The across Si/SiGe the sourceheterostructure/gate and underlap structure minimized the carrier recombination and generation across the source/gate and drainquantum/gate well interfaces. suppressed As holdthe diffusio time increased,n of the storedIR1 decreased hole charges, because as shown recombination in Figure reduced 8b, and thethe drain/gate interfaces. As hold time increased, IR1 decreased because recombination reduced the hole holeunderlap density. structure The increase minimized in IR0 thewas carrier influenced recombination by carrier and generation generation between across the bodysource/gate/drain andand density. The increase in IR0 was influenced by carrier generation between the body/drain and bodydrain/gate/source interfaces. interfaces, As which hold was time caused increased, by the IR1 SRH decreased and TAT because mechanisms recombination while holding reduced the ‘0’the state, hole body/source interfaces, which was caused by the SRH and TAT mechanisms while holding the ‘0’ asdensity. shown The in Figure increase8c. Atin theIR0 temperaturewas influenced of 358 by K carrier (approximately generation 85 between◦C), there the were body/drain no significant and body/sourcestate, as shown interfaces, in Figure which 8c. was At causedthe temperatur by the SRHe of and358 TATK (approximately mechanisms while 85 °C), holding there thewere ‘0’ no state, as shown in Figure 8c. At the temperature of 358 K (approximately 85 °C), there were no

Electronics 2020, 9, 2134 8 of 12

Electronics 2020, 9, x FOR PEER REVIEW 8 of 12 changes in the IR1 and IR0 values up to 10 ms due to the reduction in carrier recombination and significant changes in the IR1 and IR0 values up to 10 ms due to the reduction in carrier recombination generation rates caused by the underlap structure. and generation rates caused by the underlap structure.

(a)

(b) (c)

FigureFigure 8. 8. ((aa)) ReadRead currentscurrents IR1 andand IR0IR0 asas functions functions ofof hold hold time time at atthe the temperatures temperatures of 300 of 300 K and K and 358 358K. ( K.b) (Theb) The energy energy band band diagrams diagrams for for the the hold hold operation operation at at (b (b) )‘1’ ‘1’ and and ( (cc)) ‘0’ ‘0’ states states are also provided.provided.

TheTheV VG_HG_H and VD_H areare both both at at 0 0V. V.

TheThe retentionretention characteristicscharacteristics ofof thethe proposedproposed 1T-DRAM1T-DRAM areare betterbetter thanthan thosethose ofof thethe 1T-DRAM 1T-DRAM withwith a a Si Si body, body, as as shown shown in in Figure Figure9a. 9a. Here, Here, the the retention retention time time is is defined defined as as the the time time elapsed elapsed until until thethe sensing sensing margin margin reaches reaches 50% 50% of of its its initial initial value. value. WhenWhen thethe temperaturetemperature waswas 300300 K,K, the the 1T-DRAM 1T-DRAM withwith aa SiGe SiGe body body retained retained thethe sensingsensing marginmargin forfora a hold hold time time above above 100 100 ms, ms, whereas whereas the the sensing sensing marginmargin ofof the the 1T-DRAM 1T-DRAM with with a a Si Si body body sharply sharply decreased decreased after after a a hold hold time time of of 1 1 ms. ms. The The retention retention characteristicscharacteristics ofof thethe 1T-DRAM1T-DRAM was was a affectedffected by by the the di diffusionffusion and and recombination recombination mechanisms mechanisms of of the the storedstored holes. holes. The The recombination recombination rate rate in the in proposed the proposed 1T-DRAM 1T-DRAM was higher was than higher that than of the that 1T-DRAM of the with1T-DRAM a Si body with due a Si to body the high due storedto the high hole stored density, hole as showndensity, in as Figure shown9b. in However, Figure 9b. the However, proposed the 1T-DRAMproposed obtained1T-DRAM a longobtained retention a long time retention because thetime diff usionbecause of thethe holesdiffusion was suppressedof the holes by thewas valencesuppressed band by off setthe betweenvalence band Si and offset SiGe. between As a result, Si and the SiGe. diffusion As a mechanisms result, the diffusion were the dominatingmechanisms factorswere the reducing dominating the retention factors reducing time. Although the retentio the sensingn time. marginAlthough was the reduced sensing at margin the temperature was reduced of 358at the K, thetemperature proposed 1T-DRAMof 358 K, the achieved proposed a retention 1T-DRA timeM achieved above 10 a ms.retention These time results above demonstrate 10 ms. These that theresults proposed demonstrate device has that a high the potentialproposed for device embedded has memorya high applications.potential for embedded memory applications.

ElectronicsElectronics 20202020, ,99, ,x 2134 FOR PEER REVIEW 9 9of of 12 12

(a)

(b)

FigureFigure 9. 9. (a(a) )Comparison Comparison of of sensing marginsmargins asas functions functions of of hold hold time time between between 1T-DRAMs 1T-DRAMs with with Si and Si andSiGe SiGe body body at temperatures at temperatures of 300 of K 300 and K 358 and K. 358 (b) K. Recombination (b) Recombination rates in rates 1T-DRAMs in 1T-DRAMs with Si andwith SiGe Si andbody SiGe for body the hold for the operation hold operation at the ‘1’ at state the (hold‘1’ state time (hold= 10 time ns) and= 10 temperaturesns) and temperatures of 300 K. of 300 K.

TheThe performances performances of of the the 1T-DRAM with thethe SiSi/SiG/SiGee heterojunctionheterojunction were were substantially substantially a ffaffectedected by bythe the valence valence band band offset offset between between Si and Si SiGe,and SiGe which, which can be can changed be changed by the variationby the variation of Ge content of Ge in contentSiGe. In in addition, SiGe. In we addition, investigated we theinvestigated effects of Gethe content effects in of the Ge SiGe content body in on the the SiGe sensing body margin on the and sensingretention margin time ofand the retention 1T-DRAM, time as of shown the 1T-DRAM, in Figure as10 .shown With the in Figure increase 10. in With Ge content, the increase the sensing in Ge content,margin the of the sensing 1T-DRAM margin drastically of the 1T-DRAM increased. drasti Thiscally result increased. was due toThis a high result BTBT was rate, due whichto a high was BTBTformed rate, by which the increased was formed valence by the band increased offset between valence Siband and offset SiGe. between When theSi and higher SiGe. BTBT When occurs, the higherthe sensing BTBT margin occurs, was the improved sensing bymargin a higher was hole impr density.oved by In termsa higher of retention hole density. time, theIn 1T-DRAMterms of retentionwith high time, Ge contentthe 1T-DRAM of 0.4 exhibitedwith higha Ge short content retention of 0.4time exhibited of 7.7 a ms. short Although retention the time high of 7.7 valence ms. Althoughband offset the between high valence Si and SiGeband suppressedoffset between the hole Si and diff usion,SiGe suppressed the recombination the hole rate diffusion, became highthe recombinationat the source/ bodyrate became and body high/drain at interfaces.the source/body As a result,and body/drain the increase interfaces. in the recombination As a result, the rate increasedegraded in thethe retention recombination time of rate the 1T-DRAMdegraded th withe retention high Ge content.time of the Thus, 1T-DRAM an optimum with Ge high content Ge content.in the SiGe Thus, body an wasoptimum 0.3, considering Ge content the in memory the SiGe characteristics body was and0.3, latticeconsidering mismatch the between memory Si characteristicsand SiGe. The and variation lattice of mismatch Ge content between in the proposed Si and 1T-DRAMSiGe. The inducedvariation the of trade-o Ge contentff between in the the proposedsensing margin 1T-DRAM and retentioninduced time.the trade-off The 1T-DRAMs between obtained the sensing the trade-o marginff between and retention the sensing time. margin The 1T-DRAMsand retention obtained time due the to trade-off design parameters,between the such sens asing channel margin doping and retention [27] and time body due thickness to design [28], parameters, such as channel doping [27] and body thickness [28], which affected the stored hole

Electronics 2020, 9, 2134 10 of 12 Electronics 2020, 9, x FOR PEER REVIEW 10 of 12 whichdensity a ﬀandected recombination the stored hole rate density simultaneously. and recombination Therefore, rate simultaneously. the memory Therefore,characteristics the memory of the characteristicsproposed 1T-DRAMs of the proposed can be improved 1T-DRAMs by optimizing can be improved the design by optimizing parameters. the design parameters.

Figure 10. EffectsEffects of of Ge content in the SiGe body on sensing margins and retention times of the 1T-DRAMs atat aa temperaturetemperature ofof 358358 K.K. 4. Conclusions 4. Conclusions The GAA-JLFET-based 1T-DRAM cell with the Si/SiGe heterostructure was presented for The GAA-JLFET-based 1T-DRAM cell with the Si/SiGe heterostructure was presented for high-density memory applications. The efficiency of program operations was realized by BTBT high-density memory applications. The efficiency of program operations was realized by BTBT between the SiGe body and Si drain regions due to the reduction in the tunneling barrier. The proposed between the SiGe body and Si drain regions due to the8 reduction in the tunneling barrier. The 1T-DRAM achieved a high ratio of IR1/IR0 of about 10 at a low VG_R of 0.2 V and VD_R of 0.1 V. proposed 1T-DRAM achieved a high ratio of IR1/IR0 of about 108 at a low VG_R of 0.2 V and VD_R of 0.1 The retention time above 10 ms was obtained at the temperature of 358 K due to the quantum well, V. The retention time above 10 ms was obtained at the temperature of 358 K due to the quantum which was formed by the valence band offset between Si and SiGe. As a result, the proposed 1T-DRAMs well, which was formed by the valence band offset between Si and SiGe. As a result, the proposed is a suitable memory cell for high-density applications because of its nanowire structure and excellent 1T-DRAMs is a suitable memory cell for high-density applications because of its nanowire structure memory performance. and excellent memory performance. Author Contributions: Conceptualization, Y.J.Y. Investigation, Y.J.Y. Data analysis, Y.J.Y., J.S.L., D.-S.K., S.H.L. andAuthor I.M.K. Contributions: Writing—original Conceptualization, draft preparation, Y.J.Y. Y.J.Y. Investigation, Writing—review Y.J.Y. Data and analysis, editing, I.M.K. Y.J.Y., AllJ.S.L., authors D.-S.K., have S.H.L., read and agreedI.M.K. toWriting—original the published version draft pr ofeparation, the manuscript. Y.J.Y. Writing—review and editing, I.M.K. All authors have Funding:read and agreedThis work to the was publis supportedhed version by theof the National manuscript. Research Foundation of Korea (NRF) grant funded by theFunding: Korea This government work was (MSIT) supported (No. by NRF-2020R1A2C1005087) the National Research Foundation and in part of byKorea Samsung (NRF) Electronicsgrant funded Co. by Ltd.the The study was supported by the 4 BK21 project funded by the Ministry of Education, Korea, by the Ministry of Trade,Korea Industrygovernment & Energy (MSIT) (MOTIE) (No. NRF-2020R1A2C1005087) (10080513), and Korea Semiconductor and in part by Research Samsung Consortium Electronics (KSRC) Co. Ltd. support The programstudy was for supported developing by the the future 4 BK21 semiconductor project funded devices. by the This Ministry work was of alsoEducation, supported Korea, by theby KOMACthe Ministry (Korea of Multi-purposeTrade, Industry Accelerator & Energy Complex) (MOTIE) operation (10080513), fund and of KAERIKorea (KoreaSemiconductor Atomic Energy Resear Researchch Consortium Institute). (KSRC) Conflictssupport program of Interest: forThe developing authors declarethe future no conflict semiconductor of interest. devices. This work was also supported by the KOMAC (Korea Multi-purpose Accelerator Complex) operation fund of KAERI (Korea Atomic Energy Research Institute). References Conflicts of Interest: The authors declare no conflict of interest. 1. “More Moore,” IEEE International Roadmap for Device and Systems (IRDS). 2017. Available online: https://irds.ieee.org (accessed on 12 December 2020). References 2. Park, S.-K. Technology Scaling Challenge and Future Prospects of DRAM and NAND Flash Memory. 1. Proc.“More IEEE Moore,” Int. Mem. IEEE Workshop International IMW 2015Roadmap.[CrossRef for De] vice and Systems (IRDS). 2017. Available online: 3. https://irds.ieee.orgLee, S.-H. Technology (accessed scaling challengeson 12 December and opportunities 2020). of memory devices. In Proceedings of the 2016 2. Park,IEEE InternationalS.-K. Technology Electron Scaling Devices Challenge Meeting and (IEDM), Future Prospects San Francisco, of DRAM CA, USA,and NAND 3–7 December Flash Memory. 2016. Proc. 4. IEEEKim, S.K.;Int. Mem. Popovici, Workshop M. Future IMW of 2015 dynamic, doi:10.1109/IMW.2015.7150307. random-access memory as main memory. MRS Bull. 2018, 43, 334–339. 3. Lee,[CrossRef S.-H.] Technology scaling challenges and opportunities of memory devices. In Proceedings of the 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 3–7 December 2016.

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